From: sashiko-bot@kernel.org
To: "Badal Nilawar" <badal.nilawar@intel.com>,
intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header
Date: Fri, 23 Oct 2026 04:30:07 +0000 [thread overview]
Message-ID: <sashiko-outbox-182289@kernel.org> (raw)
In-Reply-To: <20261023043422.681260-18-badal.nilawar@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/xe/cper: cper_init_intel_hdr() never sets unknown sig_id to U32_MAX
--
commit 1eb07867e667177c6634aadbe7bf46699728e40f
Author: Badal Nilawar <badal.nilawar@intel.com>
drm/xe/cper: Initialize Intel-specific section header
This commit defines struct xe_cper_intel_hdr for the Intel GPU error
section of a CPER record and adds helpers in drivers/gpu/drm/xe/xe_cper.c
to initialize it from a RAS error counter response.
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index a9044e708caca..3d7657517223a 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +static bool is_valid_sigid(u32 sigid)
> +{
> + return sigid != U32_MAX;
> +}
> +
> static bool is_hw_sigid(enum xe_sigid sigid)
> {
> return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_BATCH);
> }
>
> +static void cper_init_intel_hdr(struct xe_device *xe,
> + const struct xe_ras_error_class *counter,
> + u64 first_timestamp, u32 sig_id, u32 error_count,
> + struct xe_cper_intel_hdr *ihdr)
> +{
> + ihdr->counter = *counter;
> + ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
> +
> + if (first_timestamp) {
> + ihdr->first_timestamp = first_timestamp;
> + ihdr->validation_bits |= XE_CPER_VALID_FIRST_TIMESTAMP;
> + }
> +
> + if (is_valid_sigid(sig_id)) {
> + ihdr->sig_id = sig_id;
> + ihdr->validation_bits |= XE_CPER_VALID_SIG_ID;
> + }
[Severity: Medium]
In drivers/gpu/drm/xe/xe_cper_types.h, struct xe_cper_intel_hdr documents
sig_id as:
/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
u32 sig_id;
However, cper_emit_counter() zero-initializes struct xe_cper_intel_hdr ihdr
before calling cper_init_intel_hdr(). When sig_id is U32_MAX,
is_valid_sigid(sig_id) returns false and skips the assignment, leaving
ihdr->sig_id as 0 instead of U32_MAX.
Conversely, if INTEL_SIGID_INVALID (0) is passed, is_valid_sigid(sig_id)
returns true, leaving ihdr->sig_id as 0 while also setting
XE_CPER_VALID_SIG_ID in ihdr->validation_bits.
Should cper_init_intel_hdr() explicitly set ihdr->sig_id to U32_MAX when
sig_id is unknown, and should is_valid_sigid() also reject
INTEL_SIGID_INVALID?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261023043422.681260-15-badal.nilawar@intel.com?part=3
next prev parent reply other threads:[~2026-10-23 4:30 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 4:34 [PATCH v5 00/13] Add CPER logging support for CRI Badal Nilawar
2026-10-23 4:24 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 4:26 ` ✓ CI.KUnit: success " Patchwork
2026-10-23 4:34 ` [PATCH v5 01/13] drm/xe/cper: Add CPER reporting entry point for xe_log Badal Nilawar
2026-10-24 11:38 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 02/13] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
2026-10-24 11:50 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 03/13] drm/xe/cper: Initialize Intel-specific section header Badal Nilawar
2026-10-23 4:30 ` sashiko-bot [this message]
2026-10-26 5:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 04/13] drm/xe/cper: Construct CPER record for hardware errors Badal Nilawar
2026-10-26 9:54 ` Raag Jadav
2026-10-27 3:34 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 05/13] drm/xe/cper: Log CPER records for aggregate counter retrieval Badal Nilawar
2026-10-26 11:31 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 06/13] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
2026-10-26 12:29 ` Raag Jadav
2026-10-27 4:21 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 07/13] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
2026-10-26 12:47 ` Raag Jadav
2026-10-26 18:31 ` Nilawar, Badal
2026-10-27 1:29 ` Raag Jadav
2026-10-27 6:03 ` Nilawar, Badal
2026-10-23 4:34 ` [PATCH v5 08/13] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-10-23 6:24 ` Mallesh, Koujalagi
2026-10-27 12:43 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 09/13] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-10-23 6:16 ` Mallesh, Koujalagi
2026-10-26 12:57 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 10/13] drm/xe/xe_ras: Report correctable " Badal Nilawar
2026-10-26 15:17 ` Raag Jadav
2026-10-27 4:13 ` Raag Jadav
2026-10-23 4:34 ` [PATCH v5 11/13] drm/xe/xe_ras: Report unknown " Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 12/13] drm/xe/xe_ras: Add support to retrieve info queue data Badal Nilawar
2026-10-23 4:34 ` [PATCH v5 13/13] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
2026-10-23 6:34 ` ✓ Xe.CI.FULL: success for Add CPER logging support for CRI (rev5) Patchwork
2026-10-23 6:35 ` ✓ Xe.CI.BAT: " Patchwork
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