From: Marcelo Tosatti <mtosatti@redhat.com>
To: James Sullivan <sullivan.james.f@gmail.com>
Cc: kvm@vger.kernel.org, gleb@kernel.org, pbonzini@redhat.com
Subject: Re: [PATCH RFC 0/9] Implement handling of RH=1 for MSI delivery in KVM
Date: Mon, 16 Mar 2015 22:11:23 -0300 [thread overview]
Message-ID: <20150317011123.GA6255@amt.cnet> (raw)
In-Reply-To: <1426377624-2046-1-git-send-email-sullivan.james.f@gmail.com>
On Sat, Mar 14, 2015 at 06:00:15PM -0600, James Sullivan wrote:
> This series of patches extends the KVM interrupt delivery mechanism
> to correctly account for the MSI Redirection Hint bit. The RH bit is
> used in logical destination mode to indicate that the delivery of the
> interrupt shall only be to the lowest priority candidate LAPIC.
>
> Currently, there is no handling of the MSI RH bit in the KVM interrupt
> delivery mechanism. This patch implements the following logic:
>
> * DM=0, RH=* : Physical destination mode. Interrupt is delivered to
> the LAPIC with the matching APIC ID. (Subject to
> the usual restrictions, i.e. no broadcast dest)
> * DM=1, RH=0 : Logical destination mode without redirection. Interrupt
> is delivered to all LAPICs in the logical group
> specified by the IRQ's destination map and delivery
> mode.
"When RH is 0, the interrupt is directed to the processor listed in the
Destination ID field."
> * DM=1, RH=1 : Logical destination mode with redirection. Interrupt
> is delivered only to the lowest priority LAPIC in the
> logical group specified by the dest map and the
> delivery mode. Delivery semantics are otherwise
> specified by the delivery_mode of the IRQ, which
> is unchanged.
>
> In other words, the RH bit is ignored in physical destination mode, and
> when it is set in logical destination mode causes delivery to only apply
> to the lowest priority processor in the logical group. The IA32 manual
> is in slight contradiction with itself on this matter, but this patch
> agrees with this interpretation of the RH bit:
>
> https://software.intel.com/en-us/forums/topic/288883
>
> This patch has passed some rudimentary tests using an SMP QEMU guest and
> virtio sourced MSIs, but I haven't done experiments with passing through
> PCI hardware (intend to start working on this).
>
> Let me know your thoughts.
>
> -James
>
> --
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prev parent reply other threads:[~2015-03-17 1:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-15 0:00 [PATCH RFC 0/9] Implement handling of RH=1 for MSI delivery in KVM James Sullivan
2015-03-15 0:00 ` [PATCH 1/9] Extended kvm_lapic_irq struct with 'bool redir_hint' for MSI delivery James Sullivan
2015-03-15 0:00 ` [PATCH 2/9] Set irq->msi_redir_hint = 1 in kvm_set_msi_irq if RH=1 James Sullivan
2015-03-15 0:00 ` [PATCH 3/9] Set default value for msi_redir_hint=false in ioapic_service James Sullivan
2015-03-15 0:00 ` [PATCH 4/9] Set default value for msi_redir_hint=false in apic_send_ipi James Sullivan
2015-03-15 0:00 ` [PATCH 5/9] Set default value for msi_redir_hint=false in kvm_pv_kick_cpu_op James Sullivan
2015-03-15 0:00 ` [PATCH 6/9] Deliver to only low-prio cpu in kvm_irq_delivery_to_apic_fast when MSI RH=1 James Sullivan
2015-03-15 0:00 ` [PATCH 7/9] Prevent delivery to non-lowest priority vcpus in kvm_irq_delivery_to_apic James Sullivan
2015-03-15 0:00 ` [PATCH 8/9] Removed TODO in kvm_set_msi_irq James Sullivan
2015-03-15 0:00 ` [PATCH 9/9] Print value of msi_redir_hint in debug dump of irq in apic_send_ipi James Sullivan
2015-03-16 15:30 ` [PATCH RFC 0/9] Implement handling of RH=1 for MSI delivery in KVM Radim Krčmář
2015-03-17 1:11 ` Marcelo Tosatti [this message]
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