[kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support

[kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support

[Samuel Holland]

Here are a few patches which are just enough to run the SBI unit tests
in a bare metal environment, under U-Boot on boards with a UART needing
32-bit MMIO (which is a rather common configuration in my experience).
Though I wonder if we should prefer the SBI debug console extension for
puts() output when available.

Samuel Holland (3):
  riscv: Add Image header to flat binaries
  riscv: Rate limit UART output to avoid FIFO overflows
  riscv: Support UARTs with different I/O widths

 lib/riscv/io.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
 riscv/cstart.S | 16 +++++++++++++++-
 2 files changed, 60 insertions(+), 3 deletions(-)

-- 
2.39.3 (Apple Git-146)

[kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries

[Samuel Holland]

This allows flat binaries to be understood by U-Boot's booti command and
its PXE boot flow.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
 riscv/cstart.S | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/riscv/cstart.S b/riscv/cstart.S
index b7ee9b9c..106737a1 100644
--- a/riscv/cstart.S
+++ b/riscv/cstart.S
@@ -39,15 +39,29 @@
  * The hartid of the current core is in a0
  * The address of the devicetree is in a1
  *
- * See Linux kernel doc Documentation/riscv/boot.rst
+ * See Linux kernel doc Documentation/arch/riscv/boot.rst and
+ * Documentation/arch/riscv/boot-image-header.rst
  */
 .global start
 start:
+	j	1f
+	.balign	8
+	.dword	0				// text offset
+	.dword	stacktop - ImageBase		// image size
+	.dword	0				// flags
+	.word	(0 << 16 | 2 << 0)		// version
+	.word	0				// res1
+	.dword	0				// res2
+	.ascii	"RISCV\0\0\0"			// magic
+	.ascii	"RSC\x05"			// magic2
+	.word	0				// res3
+
 	/*
 	 * Stash the hartid in scratch and shift the dtb address into a0.
 	 * thread_info_init() will later promote scratch to point at thread
 	 * local storage.
 	 */
+1:
 	csrw	CSR_SSCRATCH, a0
 	mv	a0, a1
 
-- 
2.39.3 (Apple Git-146)

Re: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries

[Andrew Jones]

On Mon, Dec 09, 2024 at 10:44:40PM -0600, Samuel Holland wrote:
> This allows flat binaries to be understood by U-Boot's booti command and
> its PXE boot flow.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>  riscv/cstart.S | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/riscv/cstart.S b/riscv/cstart.S
> index b7ee9b9c..106737a1 100644
> --- a/riscv/cstart.S
> +++ b/riscv/cstart.S
> @@ -39,15 +39,29 @@
>   * The hartid of the current core is in a0
>   * The address of the devicetree is in a1
>   *
> - * See Linux kernel doc Documentation/riscv/boot.rst
> + * See Linux kernel doc Documentation/arch/riscv/boot.rst and
> + * Documentation/arch/riscv/boot-image-header.rst
>   */
>  .global start
>  start:
> +	j	1f
> +	.balign	8
> +	.dword	0				// text offset

When I added a header like this for the bpi I needed the text offset to be
0x200000, like Linux has it.  Did you do something to avoid that?

> +	.dword	stacktop - ImageBase		// image size
> +	.dword	0				// flags
> +	.word	(0 << 16 | 2 << 0)		// version
> +	.word	0				// res1
> +	.dword	0				// res2
> +	.ascii	"RISCV\0\0\0"			// magic
> +	.ascii	"RSC\x05"			// magic2
> +	.word	0				// res3
> +
>  	/*
>  	 * Stash the hartid in scratch and shift the dtb address into a0.
>  	 * thread_info_init() will later promote scratch to point at thread
>  	 * local storage.
>  	 */
> +1:
>  	csrw	CSR_SSCRATCH, a0
>  	mv	a0, a1
>  
> -- 
> 2.39.3 (Apple Git-146)
>

Thanks,
drew

Re: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries

[Samuel Holland]

Hi Drew,

On 2024-12-18 4:13 AM, Andrew Jones wrote:
> On Mon, Dec 09, 2024 at 10:44:40PM -0600, Samuel Holland wrote:
>> This allows flat binaries to be understood by U-Boot's booti command and
>> its PXE boot flow.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>  riscv/cstart.S | 16 +++++++++++++++-
>>  1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/riscv/cstart.S b/riscv/cstart.S
>> index b7ee9b9c..106737a1 100644
>> --- a/riscv/cstart.S
>> +++ b/riscv/cstart.S
>> @@ -39,15 +39,29 @@
>>   * The hartid of the current core is in a0
>>   * The address of the devicetree is in a1
>>   *
>> - * See Linux kernel doc Documentation/riscv/boot.rst
>> + * See Linux kernel doc Documentation/arch/riscv/boot.rst and
>> + * Documentation/arch/riscv/boot-image-header.rst
>>   */
>>  .global start
>>  start:
>> +	j	1f
>> +	.balign	8
>> +	.dword	0				// text offset
> 
> When I added a header like this for the bpi I needed the text offset to be
> 0x200000, like Linux has it.  Did you do something to avoid that?

It turns out that U-Boot on my board is configured to ignore the first 0x200000
bytes of DRAM entirely, so the binary ended up at the right address for the
wrong reason. I can send a v2 with this field changed to 0x200000 (which also
works on my board).

Regards,
Samuel

>> +	.dword	stacktop - ImageBase		// image size
>> +	.dword	0				// flags
>> +	.word	(0 << 16 | 2 << 0)		// version
>> +	.word	0				// res1
>> +	.dword	0				// res2
>> +	.ascii	"RISCV\0\0\0"			// magic
>> +	.ascii	"RSC\x05"			// magic2
>> +	.word	0				// res3
>> +
>>  	/*
>>  	 * Stash the hartid in scratch and shift the dtb address into a0.
>>  	 * thread_info_init() will later promote scratch to point at thread
>>  	 * local storage.
>>  	 */
>> +1:
>>  	csrw	CSR_SSCRATCH, a0
>>  	mv	a0, a1
>>  
>> -- 
>> 2.39.3 (Apple Git-146)
>>
> 
> Thanks,
> drew

Re: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries

[Andrew Jones]

On Wed, Dec 18, 2024 at 05:06:09PM -0600, Samuel Holland wrote:
> Hi Drew,
> 
> On 2024-12-18 4:13 AM, Andrew Jones wrote:
> > On Mon, Dec 09, 2024 at 10:44:40PM -0600, Samuel Holland wrote:
> >> This allows flat binaries to be understood by U-Boot's booti command and
> >> its PXE boot flow.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >>  riscv/cstart.S | 16 +++++++++++++++-
> >>  1 file changed, 15 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/riscv/cstart.S b/riscv/cstart.S
> >> index b7ee9b9c..106737a1 100644
> >> --- a/riscv/cstart.S
> >> +++ b/riscv/cstart.S
> >> @@ -39,15 +39,29 @@
> >>   * The hartid of the current core is in a0
> >>   * The address of the devicetree is in a1
> >>   *
> >> - * See Linux kernel doc Documentation/riscv/boot.rst
> >> + * See Linux kernel doc Documentation/arch/riscv/boot.rst and
> >> + * Documentation/arch/riscv/boot-image-header.rst
> >>   */
> >>  .global start
> >>  start:
> >> +	j	1f
> >> +	.balign	8
> >> +	.dword	0				// text offset
> > 
> > When I added a header like this for the bpi I needed the text offset to be
> > 0x200000, like Linux has it.  Did you do something to avoid that?
> 
> It turns out that U-Boot on my board is configured to ignore the first 0x200000
> bytes of DRAM entirely, so the binary ended up at the right address for the
> wrong reason. I can send a v2 with this field changed to 0x200000 (which also
> works on my board).

Sounds good.

Thanks,
drew

> 
> Regards,
> Samuel
> 
> >> +	.dword	stacktop - ImageBase		// image size
> >> +	.dword	0				// flags
> >> +	.word	(0 << 16 | 2 << 0)		// version
> >> +	.word	0				// res1
> >> +	.dword	0				// res2
> >> +	.ascii	"RISCV\0\0\0"			// magic
> >> +	.ascii	"RSC\x05"			// magic2
> >> +	.word	0				// res3
> >> +
> >>  	/*
> >>  	 * Stash the hartid in scratch and shift the dtb address into a0.
> >>  	 * thread_info_init() will later promote scratch to point at thread
> >>  	 * local storage.
> >>  	 */
> >> +1:
> >>  	csrw	CSR_SSCRATCH, a0
> >>  	mv	a0, a1
> >>  
> >> -- 
> >> 2.39.3 (Apple Git-146)
> >>
> > 
> > Thanks,
> > drew
> 

Re: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries

[Andrew Jones]

On Wed, Dec 18, 2024 at 05:06:09PM -0600, Samuel Holland wrote:
> Hi Drew,
> 
> On 2024-12-18 4:13 AM, Andrew Jones wrote:
> > On Mon, Dec 09, 2024 at 10:44:40PM -0600, Samuel Holland wrote:
> >> This allows flat binaries to be understood by U-Boot's booti command and
> >> its PXE boot flow.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >>  riscv/cstart.S | 16 +++++++++++++++-
> >>  1 file changed, 15 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/riscv/cstart.S b/riscv/cstart.S
> >> index b7ee9b9c..106737a1 100644
> >> --- a/riscv/cstart.S
> >> +++ b/riscv/cstart.S
> >> @@ -39,15 +39,29 @@
> >>   * The hartid of the current core is in a0
> >>   * The address of the devicetree is in a1
> >>   *
> >> - * See Linux kernel doc Documentation/riscv/boot.rst
> >> + * See Linux kernel doc Documentation/arch/riscv/boot.rst and
> >> + * Documentation/arch/riscv/boot-image-header.rst
> >>   */
> >>  .global start
> >>  start:
> >> +	j	1f
> >> +	.balign	8
> >> +	.dword	0				// text offset
> > 
> > When I added a header like this for the bpi I needed the text offset to be
> > 0x200000, like Linux has it.  Did you do something to avoid that?
> 
> It turns out that U-Boot on my board is configured to ignore the first 0x200000
> bytes of DRAM entirely, so the binary ended up at the right address for the
> wrong reason. I can send a v2 with this field changed to 0x200000 (which also
> works on my board).

I made this change while applying to riscv/sbi

https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi

Thanks,
drew

> 
> Regards,
> Samuel
> 
> >> +	.dword	stacktop - ImageBase		// image size
> >> +	.dword	0				// flags
> >> +	.word	(0 << 16 | 2 << 0)		// version
> >> +	.word	0				// res1
> >> +	.dword	0				// res2
> >> +	.ascii	"RISCV\0\0\0"			// magic
> >> +	.ascii	"RSC\x05"			// magic2
> >> +	.word	0				// res3
> >> +
> >>  	/*
> >>  	 * Stash the hartid in scratch and shift the dtb address into a0.
> >>  	 * thread_info_init() will later promote scratch to point at thread
> >>  	 * local storage.
> >>  	 */
> >> +1:
> >>  	csrw	CSR_SSCRATCH, a0
> >>  	mv	a0, a1
> >>  
> >> -- 
> >> 2.39.3 (Apple Git-146)
> >>
> > 
> > Thanks,
> > drew
> 

[kvm-unit-tests PATCH 2/3] riscv: Rate limit UART output to avoid FIFO overflows

[Samuel Holland]

This is necessary when running tests on bare metal.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
 lib/riscv/io.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/lib/riscv/io.c b/lib/riscv/io.c
index b3f587bb..8d684ccd 100644
--- a/lib/riscv/io.c
+++ b/lib/riscv/io.c
@@ -13,6 +13,9 @@
 #include <asm/setup.h>
 #include <asm/spinlock.h>
 
+#define UART_LSR_OFFSET		5
+#define UART_LSR_THRE		0x20
+
 /*
  * Use this guess for the uart base in order to make an attempt at
  * having earlier printf support. We'll overwrite it with the real
@@ -76,8 +79,11 @@ void io_init(void)
 void puts(const char *s)
 {
 	spin_lock(&uart_lock);
-	while (*s)
+	while (*s) {
+		while (!(readb(uart0_base + UART_LSR_OFFSET) & UART_LSR_THRE))
+			;
 		writeb(*s++, uart0_base);
+	}
 	spin_unlock(&uart_lock);
 }
 
-- 
2.39.3 (Apple Git-146)

[kvm-unit-tests PATCH 3/3] riscv: Support UARTs with different I/O widths

[Samuel Holland]

Integration of ns16550-compatible UARTs is often done with 16 or 32-bit wide
registers. Add support for these using the standard DT properties.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
 lib/riscv/io.c | 41 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/lib/riscv/io.c b/lib/riscv/io.c
index 8d684ccd..011b5b1d 100644
--- a/lib/riscv/io.c
+++ b/lib/riscv/io.c
@@ -25,8 +25,34 @@
  */
 #define UART_EARLY_BASE ((u8 *)(unsigned long)CONFIG_UART_EARLY_BASE)
 static volatile u8 *uart0_base = UART_EARLY_BASE;
+static u32 uart0_reg_shift = 1;
+static u32 uart0_reg_width = 1;
 static struct spinlock uart_lock;
 
+static u32 uart0_read(u32 num)
+{
+	u32 offset = num << uart0_reg_shift;
+
+	if (uart0_reg_width == 1)
+		return readb(uart0_base + offset);
+	else if (uart0_reg_width == 2)
+		return readw(uart0_base + offset);
+	else
+		return readl(uart0_base + offset);
+}
+
+static void uart0_write(u32 num, u32 val)
+{
+	u32 offset = num << uart0_reg_shift;
+
+	if (uart0_reg_width == 1)
+		writeb(val, uart0_base + offset);
+	else if (uart0_reg_width == 2)
+		writew(val, uart0_base + offset);
+	else
+		writel(val, uart0_base + offset);
+}
+
 static void uart0_init_fdt(void)
 {
 	const char *compatible[] = {"ns16550a"};
@@ -50,6 +76,17 @@ static void uart0_init_fdt(void)
 			abort();
 		}
 	} else {
+		const fdt32_t *val;
+		int len;
+
+		val = fdt_getprop(dt_fdt(), ret, "reg-shift", &len);
+		if (len == sizeof(*val))
+			uart0_reg_shift = fdt32_to_cpu(*val);
+
+		val = fdt_getprop(dt_fdt(), ret, "reg-io-width", &len);
+		if (len == sizeof(*val))
+			uart0_reg_width = fdt32_to_cpu(*val);
+
 		ret = dt_pbus_translate_node(ret, 0, &base);
 		assert(ret == 0);
 	}
@@ -80,9 +117,9 @@ void puts(const char *s)
 {
 	spin_lock(&uart_lock);
 	while (*s) {
-		while (!(readb(uart0_base + UART_LSR_OFFSET) & UART_LSR_THRE))
+		while (!(uart0_read(UART_LSR_OFFSET) & UART_LSR_THRE))
 			;
-		writeb(*s++, uart0_base);
+		uart0_write(0, *s++);
 	}
 	spin_unlock(&uart_lock);
 }
-- 
2.39.3 (Apple Git-146)

Re: [kvm-unit-tests PATCH 3/3] riscv: Support UARTs with different I/O widths

[Andrew Jones]

On Mon, Dec 09, 2024 at 10:44:42PM -0600, Samuel Holland wrote:
> Integration of ns16550-compatible UARTs is often done with 16 or 32-bit wide
> registers. Add support for these using the standard DT properties.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>  lib/riscv/io.c | 41 +++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 39 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/riscv/io.c b/lib/riscv/io.c
> index 8d684ccd..011b5b1d 100644
> --- a/lib/riscv/io.c
> +++ b/lib/riscv/io.c
> @@ -25,8 +25,34 @@
>   */
>  #define UART_EARLY_BASE ((u8 *)(unsigned long)CONFIG_UART_EARLY_BASE)
>  static volatile u8 *uart0_base = UART_EARLY_BASE;
> +static u32 uart0_reg_shift = 1;

I changed this to 0 (8-bit default).

Thanks,
drew

Re: [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support

[Andrew Jones]

On Mon, Dec 09, 2024 at 10:44:39PM -0600, Samuel Holland wrote:
> Here are a few patches which are just enough to run the SBI unit tests
> in a bare metal environment, under U-Boot on boards with a UART needing
> 32-bit MMIO (which is a rather common configuration in my experience).
> Though I wonder if we should prefer the SBI debug console extension for
> puts() output when available.

Hi Samuel,

Thanks for this! I think using SBI debug console is probably the best
choice. That's what I decided to do for booting on the bananapi. We
can keep the uart improvements though for a best effort fallback
when DBCN isn't available.

Thanks,
drew

> 
> Samuel Holland (3):
>   riscv: Add Image header to flat binaries
>   riscv: Rate limit UART output to avoid FIFO overflows
>   riscv: Support UARTs with different I/O widths
> 
>  lib/riscv/io.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
>  riscv/cstart.S | 16 +++++++++++++++-
>  2 files changed, 60 insertions(+), 3 deletions(-)
> 
> -- 
> 2.39.3 (Apple Git-146)
> 

[kvm-unit-tests PATCH 4/3] riscv: Support using SBI DBCN for the console

[Andrew Jones]

We don't want to add support for lots of UARTs nor lots of support
for UARTs. Thankfully SBI may have the DBCN extension, allowing us
to use that instead when our simple UART support is insufficient.

Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
---
 configure      | 17 +++++++++++------
 lib/riscv/io.c | 16 ++++++++++++++++
 2 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/configure b/configure
index 06532a89f9c7..52904d3aa45b 100755
--- a/configure
+++ b/configure
@@ -31,6 +31,7 @@ gen_se_header=
 enable_dump=no
 page_size=
 earlycon=
+console=
 efi=
 efi_direct=
 
@@ -78,7 +79,7 @@ usage() {
 	                           4k [default], 16k, 64k for arm64.
 	                           4k [default], 64k for ppc64.
 	    --earlycon=EARLYCON
-				   Specify the UART name, type and address (optional).
+	                           Specify the UART name, type and address used for the earlycon (optional).
 	                           The specified address will overwrite the UART address set by
 	                           the --target option. EARLYCON can be one of (case sensitive):
 	               uart[8250],mmio,ADDR
@@ -89,6 +90,9 @@ usage() {
 	                           Specify a PL011 compatible UART at address ADDR. Supported
 	                           register stride is 32 bit only.
 	                           (arm/arm64 and riscv32/riscv64 only)
+	    --console=CONSOLE
+	                           Specify the device used for output (optional).
+	               sbi         Use SBI DBCN (riscv only)
 	    --[enable|disable]-efi Boot and run from UEFI (disabled by default, x86_64 and arm64 only)
 	    --[enable|disable]-werror
 	                           Select whether to compile with the -Werror compiler flag
@@ -175,6 +179,9 @@ while [[ $optno -le $argc ]]; do
 	--earlycon)
 	    earlycon="$arg"
 	    ;;
+	--console)
+	    console="$arg"
+	    ;;
 	--enable-efi)
 	    efi=y
 	    ;;
@@ -503,10 +510,8 @@ cat <<EOF >> lib/config.h
 
 EOF
 elif [ "$arch" = "riscv32" ] || [ "$arch" = "riscv64" ]; then
-cat <<EOF >> lib/config.h
-
-#define CONFIG_UART_EARLY_BASE ${uart_early_addr}
-
-EOF
+    echo "#define CONFIG_UART_EARLY_BASE ${uart_early_addr}" >> lib/config.h
+    [ "$console" = "sbi" ] && echo "#define CONFIG_SBI_CONSOLE" >> lib/config.h
+    echo >> lib/config.h
 fi
 echo "#endif" >> lib/config.h
diff --git a/lib/riscv/io.c b/lib/riscv/io.c
index 011b5b1dc1d4..c8ebfa1c7bb8 100644
--- a/lib/riscv/io.c
+++ b/lib/riscv/io.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2023, Ventana Micro Systems Inc., Andrew Jones <ajones@ventanamicro.com>
  */
 #include <libcflat.h>
+#include <bitops.h>
 #include <config.h>
 #include <devicetree.h>
 #include <asm/io.h>
@@ -29,6 +30,7 @@ static u32 uart0_reg_shift = 1;
 static u32 uart0_reg_width = 1;
 static struct spinlock uart_lock;
 
+#ifndef CONFIG_SBI_CONSOLE
 static u32 uart0_read(u32 num)
 {
 	u32 offset = num << uart0_reg_shift;
@@ -52,6 +54,7 @@ static void uart0_write(u32 num, u32 val)
 	else
 		writel(val, uart0_base + offset);
 }
+#endif
 
 static void uart0_init_fdt(void)
 {
@@ -113,6 +116,18 @@ void io_init(void)
 	}
 }
 
+#ifdef CONFIG_SBI_CONSOLE
+void puts(const char *s)
+{
+	phys_addr_t addr = virt_to_phys((void *)s);
+	unsigned long hi = upper_32_bits(addr);
+	unsigned long lo = lower_32_bits(addr);
+
+	spin_lock(&uart_lock);
+	sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, strlen(s), lo, hi, 0, 0, 0);
+	spin_unlock(&uart_lock);
+}
+#else
 void puts(const char *s)
 {
 	spin_lock(&uart_lock);
@@ -123,6 +138,7 @@ void puts(const char *s)
 	}
 	spin_unlock(&uart_lock);
 }
+#endif
 
 /*
  * Defining halt to take 'code' as an argument guarantees that it will
-- 
2.48.1

Re: [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support

[Andrew Jones]

On Mon, Dec 09, 2024 at 10:44:39PM -0600, Samuel Holland wrote:
> Here are a few patches which are just enough to run the SBI unit tests
> in a bare metal environment, under U-Boot on boards with a UART needing
> 32-bit MMIO (which is a rather common configuration in my experience).
> Though I wonder if we should prefer the SBI debug console extension for
> puts() output when available.
> 
> Samuel Holland (3):
>   riscv: Add Image header to flat binaries
>   riscv: Rate limit UART output to avoid FIFO overflows
>   riscv: Support UARTs with different I/O widths
> 
>  lib/riscv/io.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
>  riscv/cstart.S | 16 +++++++++++++++-
>  2 files changed, 60 insertions(+), 3 deletions(-)
> 
> -- 
> 2.39.3 (Apple Git-146)
>

Added patch 4/3 to allow SBI DBCN to be used for the console and applied
to riscv/sbi

https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi

Thanks,
drew

Re: [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support

[Andrew Jones]

On Mon, Dec 09, 2024 at 10:44:39PM -0600, Samuel Holland wrote:
> Here are a few patches which are just enough to run the SBI unit tests
> in a bare metal environment, under U-Boot on boards with a UART needing
> 32-bit MMIO (which is a rather common configuration in my experience).
> Though I wonder if we should prefer the SBI debug console extension for
> puts() output when available.
> 
> Samuel Holland (3):
>   riscv: Add Image header to flat binaries
>   riscv: Rate limit UART output to avoid FIFO overflows
>   riscv: Support UARTs with different I/O widths
> 
>  lib/riscv/io.c | 47 +++++++++++++++++++++++++++++++++++++++++++++--
>  riscv/cstart.S | 16 +++++++++++++++-
>  2 files changed, 60 insertions(+), 3 deletions(-)
> 
> -- 
> 2.39.3 (Apple Git-146)
>

Merged.

Thanks,
drew