From: Magnus Kulke <magnuskulke@linux.microsoft.com>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, "Magnus Kulke" <magnuskulke@microsoft.com>,
"Wei Liu" <liuwe@microsoft.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Cédric Le Goater" <clg@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Wei Liu" <wei.liu@kernel.org>,
"Magnus Kulke" <magnuskulke@linux.microsoft.com>,
"Alex Williamson" <alex@shazbot.org>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Marcelo Tosatti" <mtosatti@redhat.com>
Subject: [PATCH 25/34] target/i386/mshv: migrate STIMER state
Date: Fri, 17 Apr 2026 12:56:09 +0200 [thread overview]
Message-ID: <20260417105618.3621-26-magnuskulke@linux.microsoft.com> (raw)
In-Reply-To: <20260417105618.3621-1-magnuskulke@linux.microsoft.com>
This part of Synic state is retrieved via a mem-aligned page. We declare
the required space (size reference: rust-vmm/mshv) as a buffer on the VM
state struct for inclusion in a migration.
Other than other SynIC features, STIMER doesn't depend on SCONTROL being
set.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
---
include/system/mshv_int.h | 2 ++
target/i386/cpu.h | 5 ++++
target/i386/machine.c | 20 +++++++++++++++
target/i386/mshv/mshv-cpu.c | 12 +++++++++
target/i386/mshv/synic.c | 51 +++++++++++++++++++++++++++++++++++++
5 files changed, 90 insertions(+)
diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h
index 80df4030c5..7d685fc647 100644
--- a/include/system/mshv_int.h
+++ b/include/system/mshv_int.h
@@ -125,5 +125,7 @@ int mshv_set_simp(int cpu_fd, const uint8_t *page);
int mshv_get_siefp(int cpu_fd, uint8_t *page);
int mshv_set_siefp(int cpu_fd, const uint8_t *page);
bool mshv_synic_enabled(const CPUState *cpu);
+int mshv_get_synthetic_timers(int cpu_fd, uint8_t *state);
+int mshv_set_synthetic_timers(int cpu_fd, const uint8_t *state);
#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d010d26146..4ad4a35ce9 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -45,6 +45,10 @@
#define ELF_MACHINE_UNAME "i686"
#endif
+#ifdef CONFIG_MSHV
+#define MSHV_STIMERS_STATE_SIZE 200
+#endif
+
enum {
R_EAX = 0,
R_ECX = 1,
@@ -2295,6 +2299,7 @@ typedef struct CPUArchState {
#if defined(CONFIG_MSHV)
uint8_t hv_simp_page[HV_HYP_PAGE_SIZE];
uint8_t hv_siefp_page[HV_HYP_PAGE_SIZE];
+ uint8_t hv_synthetic_timers_state[MSHV_STIMERS_STATE_SIZE];
#endif
uint64_t mcg_cap;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index f94cc544b3..38ccbbe19d 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -10,6 +10,7 @@
#include "exec/watchpoint.h"
#include "system/kvm.h"
#include "system/kvm_xen.h"
+#include "system/mshv.h"
#include "system/tcg.h"
#include "qemu/error-report.h"
@@ -953,6 +954,24 @@ static const VMStateDescription vmstate_msr_hyperv_reenlightenment = {
};
#ifdef CONFIG_MSHV
+
+static bool mshv_synthetic_timers_needed(void *opaque)
+{
+ /* Always migrate synthetic timers */
+ return mshv_enabled();
+}
+
+static const VMStateDescription vmstate_mshv_synthetic_timers = {
+ .name = "cpu/mshv_synthetic_timers",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = mshv_synthetic_timers_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BUFFER(env.hv_synthetic_timers_state, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static bool mshv_synic_vp_state_needed(void *opaque)
{
X86CPU *cpu = opaque;
@@ -1942,6 +1961,7 @@ const VMStateDescription vmstate_x86_cpu = {
#endif
#ifdef CONFIG_MSHV
&vmstate_mshv_synic_vp_state,
+ &vmstate_mshv_synthetic_timers,
#endif
NULL
}
diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
index 36549857ae..9ce66e9aa1 100644
--- a/target/i386/mshv/mshv-cpu.c
+++ b/target/i386/mshv/mshv-cpu.c
@@ -135,6 +135,12 @@ static int get_synic_state(CPUState *cpu)
int cpu_fd = mshv_vcpufd(cpu);
int ret;
+ ret = mshv_get_synthetic_timers(cpu_fd, env->hv_synthetic_timers_state);
+ if (ret < 0) {
+ error_report("failed to get synthetic timers");
+ return -1;
+ }
+
/* SIMP/SIEFP can only be read when SynIC is enabled */
if (!mshv_synic_enabled(cpu)) {
return 0;
@@ -1039,6 +1045,12 @@ static int set_synic_state(const CPUState *cpu)
int cpu_fd = mshv_vcpufd(cpu);
int ret;
+ ret = mshv_set_synthetic_timers(cpu_fd, env->hv_synthetic_timers_state);
+ if (ret < 0) {
+ error_report("failed to set synthetic timers state");
+ return -1;
+ }
+
/* SIMP/SIEFP can only be written when SynIC is enabled */
if (!mshv_synic_enabled(cpu)) {
return 0;
diff --git a/target/i386/mshv/synic.c b/target/i386/mshv/synic.c
index 8f9fee6ed7..4c629adc3a 100644
--- a/target/i386/mshv/synic.c
+++ b/target/i386/mshv/synic.c
@@ -54,6 +54,57 @@ static int set_vp_state(int cpu_fd, const struct mshv_get_set_vp_state *state)
return 0;
}
+int mshv_get_synthetic_timers(int cpu_fd, uint8_t *state)
+{
+ int ret;
+ void *buffer;
+ struct mshv_get_set_vp_state args = {0};
+
+ buffer = qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE);
+ args.buf_ptr = (uint64_t)buffer;
+ args.buf_sz = HV_HYP_PAGE_SIZE;
+ args.type = MSHV_VP_STATE_SYNTHETIC_TIMERS;
+
+ ret = get_vp_state(cpu_fd, &args);
+
+ if (ret < 0) {
+ qemu_vfree(buffer);
+ error_report("failed to get synthetic timers");
+ return -1;
+ }
+
+ memcpy(state, buffer, MSHV_STIMERS_STATE_SIZE);
+ qemu_vfree(buffer);
+
+ return 0;
+}
+
+int mshv_set_synthetic_timers(int cpu_fd, const uint8_t *state)
+{
+ int ret;
+ void *buffer;
+ struct mshv_get_set_vp_state args = {0};
+
+ buffer = qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE);
+ memset(buffer, 0, HV_HYP_PAGE_SIZE);
+ args.buf_ptr = (uint64_t)buffer;
+ args.buf_sz = HV_HYP_PAGE_SIZE;
+ args.type = MSHV_VP_STATE_SYNTHETIC_TIMERS;
+
+ assert(state);
+ memcpy(buffer, state, MSHV_STIMERS_STATE_SIZE);
+
+ ret = set_vp_state(cpu_fd, &args);
+ qemu_vfree(buffer);
+
+ if (ret < 0) {
+ error_report("failed to set synthetic timers");
+ return -1;
+ }
+
+ return 0;
+}
+
int mshv_get_simp(int cpu_fd, uint8_t *page)
{
int ret;
--
2.34.1
next prev parent reply other threads:[~2026-04-17 10:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 10:55 [PATCH 00/34] Add migration support to the MSHV accelerator Magnus Kulke
2026-04-17 10:55 ` [PATCH 01/34] target/i386/mshv: use arch_load/store_reg fns Magnus Kulke
2026-04-17 10:55 ` [PATCH 02/34] target/i386/mshv: use generic FPU/xcr0 state Magnus Kulke
2026-04-17 10:55 ` [PATCH 03/34] target/i386/mshv: impl init/load/store_vcpu_state Magnus Kulke
2026-04-17 10:55 ` [PATCH 04/34] accel/accel-irq: add AccelRouteChange abstraction Magnus Kulke
2026-04-17 10:55 ` [PATCH 05/34] accel/accel-irq: add generic begin_route_changes Magnus Kulke
2026-04-17 10:55 ` [PATCH 06/34] accel/accel-irq: add generic commit_route_changes Magnus Kulke
2026-04-17 10:55 ` [PATCH 07/34] accel/mshv: add irq_routes to state Magnus Kulke
2026-04-17 10:55 ` [PATCH 08/34] accel/mshv: update s->irq_routes in add_msi_route Magnus Kulke
2026-04-17 10:55 ` [PATCH 09/34] accel/mshv: update s->irq_routes in update_msi_route Magnus Kulke
2026-04-17 10:55 ` [PATCH 10/34] accel/mshv: update s->irq_routes in release_virq Magnus Kulke
2026-04-17 10:55 ` [PATCH 11/34] accel/mshv: use s->irq_routes in commit_routes Magnus Kulke
2026-04-17 10:55 ` [PATCH 12/34] accel/mshv: reserve ioapic routes on s->irq_routes Magnus Kulke
2026-04-17 10:55 ` [PATCH 13/34] accel/mshv: remove redundant msi controller Magnus Kulke
2026-04-17 10:55 ` [PATCH 14/34] target/i386/mshv: move apic logic into own file Magnus Kulke
2026-04-17 10:55 ` [PATCH 15/34] target/i386/mshv: remove redundant apic helpers Magnus Kulke
2026-04-17 10:56 ` [PATCH 16/34] target/i386/mshv: migrate LAPIC state Magnus Kulke
2026-04-17 11:54 ` Mohamed Mediouni
2026-04-20 11:37 ` Magnus Kulke
2026-04-17 10:56 ` [PATCH 17/34] target/i386/mshv: move msr code to arch Magnus Kulke
2026-04-17 10:56 ` [PATCH 18/34] accel/mshv: store partition proc features Magnus Kulke
2026-04-17 10:56 ` [PATCH 19/34] target/i386/mshv: expose msvh_get_generic_regs Magnus Kulke
2026-04-17 10:56 ` [PATCH 20/34] target/i386/mshv: migrate MSRs Magnus Kulke
2026-04-17 10:56 ` [PATCH 21/34] target/i386/mshv: migrate MTRR MSRs Magnus Kulke
2026-04-17 10:56 ` [PATCH 22/34] target/i386/mshv: migrate Synic SINT MSRs Magnus Kulke
2026-04-17 10:56 ` [PATCH 23/34] target/i386/mshv: migrate CET/SS MSRs Magnus Kulke
2026-04-17 10:56 ` [PATCH 24/34] target/i386/mshv: migrate SIMP and SIEFP state Magnus Kulke
2026-04-17 10:56 ` Magnus Kulke [this message]
2026-04-17 10:56 ` [PATCH 26/34] accel/mshv: introduce SaveVMHandler Magnus Kulke
2026-04-17 10:56 ` [PATCH 27/34] accel/mshv: write synthetic MSRs after migration Magnus Kulke
2026-04-17 10:56 ` [PATCH 28/34] accel/mshv: migrate REFERENCE_TIME Magnus Kulke
2026-04-17 10:56 ` [PATCH 29/34] target/i386/mshv: migrate pending ints/excs Magnus Kulke
2026-04-17 10:56 ` [PATCH 30/34] target/i386: add de/compaction to xsave_helper Magnus Kulke
2026-04-17 11:56 ` Mohamed Mediouni
2026-04-18 17:46 ` Mohamed Mediouni
2026-04-20 12:02 ` Magnus Kulke
2026-04-17 10:56 ` [PATCH 31/34] target/i386/mshv: migrate XSAVE state Magnus Kulke
2026-04-17 10:56 ` [PATCH 32/34] target/i386/mshv: reconstruct hflags after load Magnus Kulke
2026-04-17 10:56 ` [PATCH 33/34] target/i386/mshv: migrate MP_STATE Magnus Kulke
2026-04-17 10:56 ` [PATCH 34/34] accel/mshv: enable dirty page tracking Magnus Kulke
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