Re: [PATCH v6 8/8] KVM: selftests: Add PERF_METRICS and fixed counter 3 tests

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The newly added test for PERF_METRICS writes a non-zero value (0xdeaddead) to MSR_PERF_METRICS and expects to read it back verbatim, which violates Intel's architectural rules and will cause a #GP exception on hardware.
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commit 35ae6d43235ee910691fc703d1aee89a9dbe653a
Author: Zide Chen <zide.chen@intel.com>

KVM: selftests: Add PERF_METRICS and fixed counter 3 tests

This patch adds a test case to exercise IA32_PERF_METRICS, verifying
architectural support for Topdown Level 1 metrics. It also extends the
PMU selftest to cover Intel fixed counter 3 by bumping the max fixed
counters and validating basic functionality.

> diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/testing/selftests/kvm/x86/pmu_counters_test.c
> --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c
> +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c
[ ... ]
> @@ -318,6 +322,75 @@ static void guest_test_arch_event(u8 idx)
>  				FIXED_PMC_GLOBAL_CTRL_ENABLE(i));
>  }
>  
> +static void __guest_test_perf_metrics(void)
> +{
[ ... ]
> +	/* Sanity check after PERF_METRICS disabled. */
> +	__asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS}));
> +	GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), metrics);
> +	wrmsr(MSR_PERF_METRICS, 0xdeaddead);
> +
> +	GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), 0xdeaddead);
> +}

[Severity: Medium]
Will this write to MSR_PERF_METRICS cause a #GP exception on hardware?

According to the Intel SDM, software should only write 0 to clear the metrics,
and writing a non-zero value like 0xdeaddead may trigger a general protection
fault. 

If this occurs on a host where MSR_PERF_METRICS writes are passed through
to the physical CPU, could it cause the guest to crash with an unhandled
#GP(0) exception and fail the selftest?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260629231938.15129-1-zide.chen@intel.com?part=8