Re: [PATCH v3 26/40] KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing Context Synchronization Event (ISB) after writing to the VDPEND system register.
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commit 3d6631fff5db53c3f7f6517ea282e7e87b142f9a
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls

This commit introduces hypercalls to manage SPI and LPI pending states for a
VM using the GIC VDPEND and GIC VDRCFG system instructions. It wraps these
EL2-only instructions for NVHE/hVHE configurations to allow the hypervisor
to inject interrupts and query deactivated states.

[ ... ]

> diff --git a/arch/arm64/kvm/hyp/vgic-v5-sr.c b/arch/arm64/kvm/hyp/vgic-v5-sr.c
> index 46992a6c2cacb..c50e6ae93ba3f 100644
> --- a/arch/arm64/kvm/hyp/vgic-v5-sr.c
> +++ b/arch/arm64/kvm/hyp/vgic-v5-sr.c
> @@ -149,3 +149,23 @@ void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if)
>  {
>  	write_sysreg_s(cpu_if->vgic_icsr, SYS_ICC_ICSR_EL1);
>  }
> +
> +void __vgic_v5_vdpend(u32 intid, bool pending, u16 vm)
> +{
> +	u64 value;
> +
> +	value = intid & (GICV5_GIC_VDPEND_ID_MASK | GICV5_GIC_VDPEND_TYPE_MASK);
> +	value |= FIELD_PREP(GICV5_GIC_VDPEND_PENDING_MASK, pending);
> +	value |= FIELD_PREP(GICV5_GIC_VDPEND_VM_MASK, vm);
> +	gic_insn(value, VDPEND);
> +}

[Severity: High]
Is a context synchronization event needed immediately after this system register
write?

When __vgic_v5_vdpend() completes the write via gic_insn(), it returns directly.
Without an explicit isb() before returning, could the CPU pipeline be left in
an undefined architectural state for subsequent instructions?

For comparison, the __vgic_v5_vdrcfg() implementation in this same patch
includes an isb() immediately after its gic_insn() call.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260703154811.3355680-1-sascha.bischoff@arm.com?part=26