Re: [PATCH v3 40/40] Documentation: KVM: Add the VGICv5 IRS save/restore sequences

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Crucial MMIO register restore ordering constraints detailed in the commit message are omitted from the added documentation, which can lead to failed guest restoration.
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commit 79d8bc0db4bccb0f97ab687e528e56b0455f7ae3
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

Documentation: KVM: Add the VGICv5 IRS save/restore sequences

This commit documents the required sequences for saving and restoring
the state of the virtual GICv5 IRS to avoid failures when restoring a guest.

> diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst

[ ... ]

> +IRS Restore Sequence:
> +---------------------
> +
> +The following ordering must be followed when restoring the virtual GICv5 and
> +IRS:

[ ... ]

> +e) Restore guest memory.
> +f) Restore the IRS MMIO register state by issuing KVM_SET_DEVICE_ATTR on
> +   KVM_DEV_ARM_VGIC_GRP_IRS_REGS. KVM uses the restored IRS_IST_CFGR and
> +   IRS_IST_BASER state to allocate the LPI IST during the following step.
> +g) Restore the ISTs by issuing KVM_SET_DEVICE_ATTR on

[Severity: Medium]
The commit message notes that IRS_IDx registers must be restored first,
and that IRS_IST_CFGR must be restored prior to IRS_IST_BASER. Should these
intra-group ordering constraints be explicitly mentioned in step f?

Without these constraints documented here, userspace implementers might
restore the MMIO registers in an arbitrary or address-sequential order,
which the commit message states will almost certainly fail to restore a guest
capable of handling interrupts correctly.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260703154811.3355680-1-sascha.bischoff@arm.com?part=40