Re: [PATCH v3 38/40] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The documentation for the -EINVAL error condition is incomplete, missing validation failures and uninitialized VCPU conditions.
- [Low] The documentation incorrectly lists IRS_IDR3 and IRS_IDR4 as exceptions to the rule that writes to read-only registers are ignored.
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commit da96eb3893a4c95a449b213ede4d5106eb17a5a3
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs

Document the KVM_DEV_ARM_VGIC_GRP_IRS_REGS attribute group used to
read and write the virtual IRS's MMIO register state. This provides a
GICv5-specific interface for state that is conceptually similar to the
VGICv3 ITS register interface, but uses IRS terminology instead of ITS.

> diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> index e2045b09f27d0..217a1ecfbdc5f 100644
> --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> @@ -141,3 +141,39 @@ Groups:
>      ICC_CR0_EL1
>      ICC_PCR_EL1
>      =======================  ===================================================

[ ... ]

> +      Writes to read-only registers are ignored by the kernel except for:
> +
> +      - IRS_IDR0 - IRS_IDR2 and IRS_IDR5 - IRS_IDR7: These are sanity checked to
> +        ensure that they match a sane config.
> +      - IRS_IDR3 and IRS_IDR4: These are RAZ/WI as nested virtualization is not
> +        supported.

[Severity: Low]
This isn't a bug, but is it correct to list IRS_IDR3 and IRS_IDR4 as
exceptions to the rule that writes to read-only registers are ignored?

Since RAZ/WI means write-ignored, shouldn't they just fall under the general
rule rather than being listed as an exception?

[ ... ]

> +  Errors:
> +
> +    =======  =================================================================
> +    -ENXIO   Offset does not correspond to any supported register
> +    -EFAULT  Invalid user pointer for attr->addr
> +    -EINVAL  Offset is not 32-bit aligned for 32-bit MMIO registers, or not
> +             64-bit aligned for 64-bit registers

[Severity: Low]
This isn't a bug, but is the description for -EINVAL fully complete?

Does the kernel also return -EINVAL for validation failures on the
sanity-checked registers mentioned above, or if userspace attempts to
configure the IRS before any VCPUs are created?

> +    -EBUSY   VGIC is not initialized, or one or more VCPUs are running
> +    =======  =================================================================

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Sashiko AI review · https://sashiko.dev/#/patchset/20260703154811.3355680-1-sascha.bischoff@arm.com?part=38