Re: [PATCH v3 23/40] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The GICv5 ICH_CONTEXTR_EL2.IRICHPPIDIS hardware state becomes stale when the guest dynamically changes the IRS enable state.
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commit d313992de37684fea236b00103b87412260608d1
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state

This commit updates the GICv5 ICH_CONTEXTR_EL2 register's IRICHPPIDIS field
to reflect the hypervisor's IRS enable state. It applies this state during
vgic_v5_load() to control the delivery of SPIs and LPIs to the guest.

> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index 2df61426cc714..ffb0500a4c9a7 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> @@ -1058,6 +1058,7 @@ void vgic_v5_flush_ppi_state(struct kvm_vcpu *vcpu)
>  
>  void vgic_v5_load(struct kvm_vcpu *vcpu)
>  {
> +	bool irichppidis = !vcpu->kvm->arch.vgic.enabled;
>  	struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5;
>  	u16 vm = vgic_v5_vm_id(vcpu->kvm);
>  	u16 vpe = vgic_v5_vpe_id(vcpu);

[ ... ]

>  	cpu_if->vgic_contextr = FIELD_PREP(ICH_CONTEXTR_EL2_V, true) |
> +				FIELD_PREP(ICH_CONTEXTR_EL2_IRICHPPIDIS, irichppidis) |
>  				FIELD_PREP(ICH_CONTEXTR_EL2_VPE, vpe) |
>  				FIELD_PREP(ICH_CONTEXTR_EL2_VM, vm);

[Severity: High]
Does this leave the hardware state stale when the guest dynamically changes
the IRS enable state?

When the guest toggles the IRS enable state by writing to GICV5_IRS_CR0,
the MMIO handler triggers a sequence like this:

vgic_v5_mmio_write_irs_misc()
    kvm_arm_halt_guest(vcpu->kvm);
    vgic->enabled = !!(val & GICV5_IRS_CR0_IRSEN);
    kvm_arm_resume_guest(vcpu->kvm);

Because kvm_arm_halt_guest() simply sends KVM_REQ_SLEEP and
kvm_arm_resume_guest() immediately clears the pause flag, running vCPUs
that exit to handle the request will see pause == false in
kvm_vcpu_sleep().

They will then re-enter the guest without calling schedule(), which
bypasses kvm_arch_vcpu_put() and kvm_arch_vcpu_load(). This means
vgic_v5_load() is never called to update cpu_if->vgic_contextr with the
new irichppidis state.

Should there be a mechanism to force a GICv5 context reload (similar to
KVM_REQ_RELOAD_GICv4) to ensure the updated register value is applied?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260703154811.3355680-1-sascha.bischoff@arm.com?part=23