Re: [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Inconsistent handling of ID bit counts likely miscalculates `max_vms` by a factor of 2.
--

--- Patch [7]: [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame ---
commit 2b896f2ac90e022fb55d61f670ccdb056cff2664
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame
    
The host irqchip driver provides KVM with a pointer to an IRS's config
frame. This commit extracts and stashes the VM and IST capabilities
from IRS_IDR2, IRS_IDR3, and IRS_IDR4 into a capability structure.

> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index d4789ff3e7402..3f7b132110114 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
[ ... ]
> @@ -34,6 +35,45 @@ static void vgic_v5_get_implemented_ppis(void)
>  	__assign_bit(GICV5_ARCH_PPI_PMUIRQ, ppi_caps.impl_ppi_mask, system_supports_pmuv3());
>  }
>  
> +static u32 irs_readl_relaxed(const u32 reg_offset)
> +{
> +	return readl_relaxed(irs_caps.irs_base + reg_offset);
> +}
> +
> +static void vgic_v5_irs_extract_vm_caps(const struct gic_kvm_info *info)
> +{
> +	u64 idr;
> +
[ ... ]
> +	idr = irs_readl_relaxed(GICV5_IRS_IDR3);
> +
> +	irs_caps.max_vms = BIT(FIELD_GET(GICV5_IRS_IDR3_VM_ID_BITS, idr));

[Severity: Medium]
Should this have a + 1 applied to the field value, similar to how VPE_ID_BITS
is handled below? 

GIC architecture ID bit fields canonically store the number of bits minus 1.
If VM_ID_BITS follows the same pattern, omitting the + 1 will result in KVM
calculating exactly half of the actual maximum number of VMs supported by the
hardware, leading to premature resource exhaustion.

> +	irs_caps.two_level_vmt_support = (idr & GICV5_IRS_IDR3_VMT_LEVELS);
> +
> +	if (idr & GICV5_IRS_IDR3_VMD)
> +		irs_caps.vmd_size = BIT(FIELD_GET(GICV5_IRS_IDR3_VMD_SZ, idr));
> +	else
> +		irs_caps.vmd_size = 0;
> +
> +	idr = irs_readl_relaxed(GICV5_IRS_IDR4);
> +
> +	irs_caps.vped_size = BIT(FIELD_GET(GICV5_IRS_IDR4_VPED_SZ, idr));
> +	/* Field stores VPE_ID_BITS - 1 */
> +	irs_caps.max_vpes = BIT(FIELD_GET(GICV5_IRS_IDR4_VPE_ID_BITS, idr) + 1);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=7