Re: [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Mismatch between test comment and implementation regarding VPE1's role.
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--- Patch [47]: [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests ---
commit bf269c88145be7a460a3fb9663a58422687addf2
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: selftests: Add VGICv5 LPI delivery tests

This commit adds a two-VPE VGICv5 LPI delivery test. It exercises the virtual
IRS ID registers and IST base configuration path before checking interrupt
delivery between the VPEs using a host-backed, unity-mapped userspace memslot.

> diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c
> --- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
> +++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c

[ ... ]

> @@ -1179,6 +1365,54 @@ static void test_vgic_v5_spis(void)

[ ... ]

> +static void test_vgic_v5_lpis(void)
> +{

[ ... ]

> +	/* VPE0 programs a linear LPI IST from the virtual IRS ID registers. */
> +	ret = run_vcpu(vcpus[0]);
> +	TEST_ASSERT(!ret, "Failed to run GICv5 LPI vCPU0");
> +	TEST_ASSERT(get_ucall(vcpus[0], &uc) == UCALL_SYNC &&
> +		    uc.args[1] == GUEST_CMD_IS_READY,
> +		    "GICv5 LPI vCPU0 did not become ready");
> +
> +	/* VPE1 observes the IST and enables the LPIs it will receive/send. */
> +	ret = run_vcpu(vcpus[1]);

[Severity: Low]
This comment indicates that VPE1 will enable the LPIs it receives and sends.
However, looking at guest_lpi_code(), the LPI configuration via
gicv5_configure_test_lpis() is restricted strictly to VPE0:

	if (!vcpu_id) {
		gicv5_enable_irs();
		gicv5_configure_lpi_ist();
		gicv5_configure_test_lpis();
		WRITE_ONCE(lpi_ist_ready, true);
	}

Could this comment in test_vgic_v5_lpis() be updated to accurately reflect
that only VPE0 performs the LPI configuration step?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=47