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From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	"Oliver Upton" <oupton@kernel.org>,
	"Marc Zyngier" <maz@kernel.org>
Subject: Re: [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call
Date: Fri, 24 Jul 2026 11:34:59 +0000	[thread overview]
Message-ID: <20260724113500.A5DD31F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260724104819.1296803-26-sascha.bischoff@arm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] Missing validation of the host-provided VMID allows the untrusted host to arbitrarily inject interrupts into protected VMs.
--

--- Patch [25]: [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call ---
commit c4db8b94f24a778070a5db75c24059095bae959b
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Add GIC VDPEND hyp call

This commit adds a hypercall to wrap the GIC VDPEND system instruction, allowing
the hypervisor to manage SPI and LPI pending states for VMs. This instruction is
executable only from EL2 and provides a way to inject interrupts into guests.

> diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
> index 09756f71df08e..8f9cc3cd422aa 100644
> --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c
> +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
[ ... ]
> @@ -719,6 +719,15 @@ static void handle___vgic_v5_restore_vmcr_apr(struct kvm_cpu_context *host_ctxt)
>  	__vgic_v5_restore_vmcr_apr(kern_hyp_va(cpu_if));
>  }
>  
> +static void handle___vgic_v5_vdpend(struct kvm_cpu_context *host_ctxt)
> +{
> +	DECLARE_REG(u32, intid, host_ctxt, 1);
> +	DECLARE_REG(bool, pending, host_ctxt, 2);
> +	DECLARE_REG(u16, vm, host_ctxt, 3);
> +
> +	__vgic_v5_vdpend(intid, pending, vm);

[Severity: Critical]
Does this code introduce a regression by allowing an untrusted host to
arbitrarily inject interrupts into protected VMs?

The hypercall handler extracts the vm argument from the untrusted host context
and acts on it without any validation against protected VM ownership.

Since this hypercall is directly reachable from the untrusted host under pKVM,
the host could supply the VMID of a protected guest in the vm parameter.

> +}
> +
>  typedef void (*hcall_t)(struct kvm_cpu_context *);
>  
>  #define HANDLE_FUNC(x)	[__KVM_HOST_SMCCC_FUNC_##x] = (hcall_t)handle_##x

> diff --git a/arch/arm64/kvm/hyp/vgic-v5-sr.c b/arch/arm64/kvm/hyp/vgic-v5-sr.c
> index 46992a6c2cacb..94746317ca79f 100644
> --- a/arch/arm64/kvm/hyp/vgic-v5-sr.c
> +++ b/arch/arm64/kvm/hyp/vgic-v5-sr.c
[ ... ]
> @@ -149,3 +149,13 @@ void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if)
>  {
>  	write_sysreg_s(cpu_if->vgic_icsr, SYS_ICC_ICSR_EL1);
>  }
> +
> +void __vgic_v5_vdpend(u32 intid, bool pending, u16 vm)
> +{
> +	u64 value;
> +
> +	value = intid & (GICV5_GIC_VDPEND_ID_MASK | GICV5_GIC_VDPEND_TYPE_MASK);
> +	value |= FIELD_PREP(GICV5_GIC_VDPEND_PENDING_MASK, pending);
> +	value |= FIELD_PREP(GICV5_GIC_VDPEND_VM_MASK, vm);
> +	gic_insn(value, VDPEND);

[Severity: Critical]
Could the unvalidated vm parameter cause a regression by violating guest
integrity and isolation here?

The unvalidated vm parameter is packaged directly into the VDPEND system
instruction, modifying the interrupt state of the targeted VM.

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=25

  reply	other threads:[~2026-07-24 11:35 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30   ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45   ` sashiko-bot
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34   ` sashiko-bot [this message]
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48   ` sashiko-bot
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
     [not found] ` <20260724104819.1296803-35-sascha.bischoff@arm.com>
2026-07-24 11:46   ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI sashiko-bot
     [not found] ` <20260724104819.1296803-31-sascha.bischoff@arm.com>
2026-07-24 11:52   ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() sashiko-bot
     [not found] ` <20260724104819.1296803-36-sascha.bischoff@arm.com>
2026-07-24 12:02   ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs sashiko-bot
     [not found] ` <20260724104819.1296803-42-sascha.bischoff@arm.com>
2026-07-24 12:02   ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS attribute tests sashiko-bot
     [not found] ` <20260724104819.1296803-33-sascha.bischoff@arm.com>
2026-07-24 12:05   ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region sashiko-bot
     [not found] ` <20260724104819.1296803-43-sascha.bischoff@arm.com>
2026-07-24 12:06   ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS attribute tests sashiko-bot
     [not found] ` <20260724104819.1296803-32-sascha.bischoff@arm.com>
2026-07-24 12:09   ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors sashiko-bot
     [not found] ` <20260724104819.1296803-47-sascha.bischoff@arm.com>
2026-07-24 12:15   ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests sashiko-bot
     [not found] ` <20260724104819.1296803-48-sascha.bischoff@arm.com>
2026-07-24 12:18   ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests sashiko-bot
     [not found] ` <20260724104819.1296803-38-sascha.bischoff@arm.com>
2026-07-24 12:19   ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs sashiko-bot
     [not found] ` <20260724104819.1296803-30-sascha.bischoff@arm.com>
2026-07-24 12:19   ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd sashiko-bot

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