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From: Andrew Jones <drjones@redhat.com>
To: pbonzini@redhat.com
Cc: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Subject: [PULL kvm-unit-tests 36/39] arm/arm64: ITS: INT functional tests
Date: Sat,  4 Apr 2020 16:37:28 +0200	[thread overview]
Message-ID: <20200404143731.208138-37-drjones@redhat.com> (raw)
In-Reply-To: <20200404143731.208138-1-drjones@redhat.com>

From: Eric Auger <eric.auger@redhat.com>

Triggers LPIs through the INT command.

the test checks the LPI hits the right CPU and triggers
the right LPI intid, ie. the translation is correct.

Updates to the config table also are tested, along with inv
and invall commands.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
---
 arm/gic.c         | 217 +++++++++++++++++++++++++++++++++++++++++++---
 arm/unittests.cfg |   7 ++
 2 files changed, 213 insertions(+), 11 deletions(-)

diff --git a/arm/gic.c b/arm/gic.c
index 649ed81d33e1..54ae83d26eb9 100644
--- a/arm/gic.c
+++ b/arm/gic.c
@@ -159,6 +159,87 @@ static void ipi_handler(struct pt_regs *regs __unused)
 	}
 }
 
+static void setup_irq(irq_handler_fn handler)
+{
+	gic_enable_defaults();
+#ifdef __arm__
+	install_exception_handler(EXCPTN_IRQ, handler);
+#else
+	install_irq_handler(EL1H_IRQ, handler);
+#endif
+	local_irq_enable();
+}
+
+#if defined(__aarch64__)
+struct its_event {
+	int cpu_id;
+	int lpi_id;
+};
+
+struct its_stats {
+	struct its_event expected;
+	struct its_event observed;
+};
+
+static struct its_stats lpi_stats;
+
+static void lpi_handler(struct pt_regs *regs __unused)
+{
+	u32 irqstat = gic_read_iar();
+	int irqnr = gic_iar_irqnr(irqstat);
+
+	gic_write_eoir(irqstat);
+	assert(irqnr >= 8192);
+	smp_rmb(); /* pairs with wmb in lpi_stats_expect */
+	lpi_stats.observed.cpu_id = smp_processor_id();
+	lpi_stats.observed.lpi_id = irqnr;
+	smp_wmb(); /* pairs with rmb in check_lpi_stats */
+}
+
+static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id)
+{
+	lpi_stats.expected.cpu_id = exp_cpu_id;
+	lpi_stats.expected.lpi_id = exp_lpi_id;
+	lpi_stats.observed.cpu_id = -1;
+	lpi_stats.observed.lpi_id = -1;
+	smp_wmb(); /* pairs with rmb in handler */
+}
+
+static void check_lpi_stats(const char *msg)
+{
+	int i;
+
+	for (i = 0; i < 50; i++) {
+		mdelay(100);
+		smp_rmb(); /* pairs with wmb in lpi_handler */
+		if (lpi_stats.observed.cpu_id == lpi_stats.expected.cpu_id &&
+		    lpi_stats.observed.lpi_id == lpi_stats.expected.lpi_id) {
+			report(true, "%s", msg);
+			return;
+		}
+	}
+
+	if (lpi_stats.observed.cpu_id == -1 && lpi_stats.observed.lpi_id == -1) {
+		report_info("No LPI received whereas (cpuid=%d, intid=%d) "
+			    "was expected", lpi_stats.expected.cpu_id,
+			    lpi_stats.expected.lpi_id);
+	} else {
+		report_info("Unexpected LPI (cpuid=%d, intid=%d)",
+			    lpi_stats.observed.cpu_id,
+			    lpi_stats.observed.lpi_id);
+	}
+	report(false, "%s", msg);
+}
+
+static void secondary_lpi_test(void)
+{
+	setup_irq(lpi_handler);
+	cpumask_set_cpu(smp_processor_id(), &ready);
+	while (1)
+		wfi();
+}
+#endif
+
 static void gicv2_ipi_send_self(void)
 {
 	writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR);
@@ -216,17 +297,6 @@ static void ipi_test_smp(void)
 	report_prefix_pop();
 }
 
-static void setup_irq(irq_handler_fn handler)
-{
-	gic_enable_defaults();
-#ifdef __arm__
-	install_exception_handler(EXCPTN_IRQ, handler);
-#else
-	install_irq_handler(EL1H_IRQ, handler);
-#endif
-	local_irq_enable();
-}
-
 static void ipi_send(void)
 {
 	setup_irq(ipi_handler);
@@ -521,6 +591,7 @@ static void gic_test_mmio(void)
 #if defined(__arm__)
 
 static void test_its_introspection(void) {}
+static void test_its_trigger(void) {}
 
 #else /* __aarch64__ */
 
@@ -559,6 +630,126 @@ static void test_its_introspection(void)
 	report_info("collection table entry_size = 0x%x", coll_baser->esz);
 }
 
+static int its_prerequisites(int nb_cpus)
+{
+	int cpu;
+
+	if (!gicv3_its_base()) {
+		report_skip("No ITS, skip ...");
+		return -1;
+	}
+
+	if (nr_cpus < nb_cpus) {
+		report_skip("Test requires at least %d vcpus", nb_cpus);
+		return -1;
+	}
+
+	stats_reset();
+
+	setup_irq(lpi_handler);
+
+	for_each_present_cpu(cpu) {
+		if (cpu == 0)
+			continue;
+		smp_boot_secondary(cpu, secondary_lpi_test);
+	}
+	wait_on_ready();
+
+	its_enable_defaults();
+
+	return 0;
+}
+
+static void test_its_trigger(void)
+{
+	struct its_collection *col3, *col2;
+	struct its_device *dev2, *dev7;
+
+	if (its_prerequisites(4))
+		return;
+
+	dev2 = its_create_device(2 /* dev id */, 8 /* nb_ites */);
+	dev7 = its_create_device(7 /* dev id */, 8 /* nb_ites */);
+
+	col3 = its_create_collection(3 /* col id */, 3/* target PE */);
+	col2 = its_create_collection(2 /* col id */, 2/* target PE */);
+
+	gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT);
+	gicv3_lpi_set_config(8196, LPI_PROP_DEFAULT);
+
+	report_prefix_push("int");
+	/*
+	 * dev=2, eventid=20  -> lpi= 8195, col=3
+	 * dev=7, eventid=255 -> lpi= 8196, col=2
+	 * Trigger dev2, eventid=20 and dev7, eventid=255
+	 * Check both LPIs hit
+	 */
+
+	its_send_mapd(dev2, true);
+	its_send_mapd(dev7, true);
+
+	its_send_mapc(col3, true);
+	its_send_mapc(col2, true);
+
+	its_send_invall(col2);
+	its_send_invall(col3);
+
+	its_send_mapti(dev2, 8195 /* lpi id */, 20 /* event id */, col3);
+	its_send_mapti(dev7, 8196 /* lpi id */, 255 /* event id */, col2);
+
+	lpi_stats_expect(3, 8195);
+	its_send_int(dev2, 20);
+	check_lpi_stats("dev=2, eventid=20  -> lpi= 8195, col=3");
+
+	lpi_stats_expect(2, 8196);
+	its_send_int(dev7, 255);
+	check_lpi_stats("dev=7, eventid=255 -> lpi= 8196, col=2");
+
+	report_prefix_pop();
+
+	report_prefix_push("inv/invall");
+
+	/*
+	 * disable 8195, check dev2/eventid=20 does not trigger the
+	 * corresponding LPI
+	 */
+	gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT & ~LPI_PROP_ENABLED);
+	its_send_inv(dev2, 20);
+
+	lpi_stats_expect(-1, -1);
+	its_send_int(dev2, 20);
+	check_lpi_stats("dev2/eventid=20 does not trigger any LPI");
+
+	/*
+	 * re-enable the LPI but willingly do not call invall
+	 * so the change in config is not taken into account.
+	 * The LPI should not hit
+	 */
+	gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT);
+	lpi_stats_expect(-1, -1);
+	its_send_int(dev2, 20);
+	check_lpi_stats("dev2/eventid=20 still does not trigger any LPI");
+
+	/* Now call the invall and check the LPI hits */
+	its_send_invall(col3);
+	lpi_stats_expect(3, 8195);
+	its_send_int(dev2, 20);
+	check_lpi_stats("dev2/eventid=20 now triggers an LPI");
+
+	report_prefix_pop();
+
+	report_prefix_push("mapd valid=false");
+	/*
+	 * Unmap device 2 and check the eventid 20 formerly
+	 * attached to it does not hit anymore
+	 */
+
+	its_send_mapd(dev2, false);
+	lpi_stats_expect(-1, -1);
+	its_send_int(dev2, 20);
+	check_lpi_stats("no LPI after device unmap");
+	report_prefix_pop();
+}
 #endif
 
 int main(int argc, char **argv)
@@ -592,6 +783,10 @@ int main(int argc, char **argv)
 		report_prefix_push(argv[1]);
 		gic_test_mmio();
 		report_prefix_pop();
+	} else if (!strcmp(argv[1], "its-trigger")) {
+		report_prefix_push(argv[1]);
+		test_its_trigger();
+		report_prefix_pop();
 	} else if (strcmp(argv[1], "its-introspection") == 0) {
 		report_prefix_push(argv[1]);
 		test_its_introspection();
diff --git a/arm/unittests.cfg b/arm/unittests.cfg
index fff37f9fb5e6..47f9446adcc3 100644
--- a/arm/unittests.cfg
+++ b/arm/unittests.cfg
@@ -184,6 +184,13 @@ extra_params = -machine gic-version=3 -append 'its-introspection'
 groups = its
 arch = arm64
 
+[its-trigger]
+file = gic.flat
+smp = $MAX_SMP
+extra_params = -machine gic-version=3 -append 'its-trigger'
+groups = its
+arch = arm64
+
 # Test PSCI emulation
 [psci]
 file = psci.flat
-- 
2.25.1

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  parent reply	other threads:[~2020-04-04 14:39 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-04 14:36 [PULL kvm-unit-tests 00/39] arm/arm64: The old and new Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 01/39] Makefile: Use no-stack-protector compiler options Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 02/39] arm/arm64: psci: Don't run C code without stack or vectors Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 03/39] arm64: timer: Add ISB after register writes Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 04/39] arm64: timer: Add ISB before reading the counter value Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 05/39] arm64: timer: Make irq_received volatile Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 06/39] arm64: timer: EOIR the interrupt after masking the timer Andrew Jones
2020-04-04 14:36 ` [PULL kvm-unit-tests 07/39] arm64: timer: Wait for the GIC to sample timer interrupt state Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 08/39] arm64: timer: Check the " Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 09/39] arm64: timer: Test behavior when timer disabled or masked Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 10/39] arm/arm64: Perform dcache clean + invalidate after turning MMU off Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 11/39] arm/arm64: gic: Move gic_state enumeration to asm/gic.h Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 12/39] arm64: timer: Use the proper RDist register name in GICv3 Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 13/39] arm64: timer: Use existing helpers to access counter/timers Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 14/39] arm64: timer: Speed up gic-timer-state check Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 15/39] arm64: Provide read/write_sysreg_s Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 16/39] arm: pmu: Let pmu tests take a sub-test parameter Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 17/39] arm: pmu: Don't check PMCR.IMP anymore Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 18/39] arm: pmu: Add a pmu struct Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 19/39] arm: pmu: Introduce defines for PMU versions Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 20/39] arm: pmu: Check Required Event Support Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 21/39] arm: pmu: Basic event counter Tests Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 22/39] arm: pmu: Test SW_INCR event count Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 23/39] arm: pmu: Test chained counters Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 24/39] arm: pmu: test 32-bit <-> 64-bit transitions Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 25/39] arm: gic: Introduce gic_irq_set_clr_enable() helper Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 26/39] arm: pmu: Test overflow interrupts Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 27/39] libcflat: Add other size defines Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 28/39] page_alloc: Introduce get_order() Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 29/39] arm/arm64: gic: Introduce setup_irq() helper Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 30/39] arm/arm64: gicv3: Add some re-distributor defines Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 31/39] arm/arm64: gicv3: Set the LPI config and pending tables Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 32/39] arm/arm64: ITS: Introspection tests Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 33/39] arm/arm64: ITS: its_enable_defaults Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 34/39] arm/arm64: ITS: Device and collection Initialization Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 35/39] arm/arm64: ITS: Commands Andrew Jones
2020-04-04 14:37 ` Andrew Jones [this message]
2020-04-04 14:37 ` [PULL kvm-unit-tests 37/39] arm/run: Allow Migration tests Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 38/39] arm/arm64: ITS: migration tests Andrew Jones
2020-04-04 14:37 ` [PULL kvm-unit-tests 39/39] arm/arm64: ITS: pending table migration test Andrew Jones
2020-04-07 15:28 ` [PULL kvm-unit-tests 00/39] arm/arm64: The old and new Paolo Bonzini

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