From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
<kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
kvm@vger.kernel.org
Subject: [PATCH v4 11/16] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
Date: Sun, 13 Nov 2022 16:38:27 +0000 [thread overview]
Message-ID: <20221113163832.3154370-12-maz@kernel.org> (raw)
In-Reply-To: <20221113163832.3154370-1-maz@kernel.org>
Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
the PMUver field can be altered and be at most the one that was
initially computed for the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1d887fe289d8..3cbcda665d23 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1242,6 +1242,45 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
return 0;
}
+static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ u8 pmuver, host_pmuver;
+ bool valid_pmu;
+
+ host_pmuver = kvm_arm_pmu_get_pmuver_limit();
+
+ /*
+ * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
+ * as it doesn't promise more than what the HW gives us. We
+ * allow an IMPDEF PMU though, only if no PMU is supported
+ * (KVM backward compatibility handling).
+ */
+ pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
+ if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
+ return -EINVAL;
+
+ valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
+
+ /* Make sure view register and PMU support do match */
+ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
+ return -EINVAL;
+
+ /* We can only differ with PMUver, and anything else is an error */
+ val ^= read_id_reg(vcpu, rd);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ if (val)
+ return -EINVAL;
+
+ if (valid_pmu)
+ vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
+ else
+ vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
+
+ return 0;
+}
+
/*
* cpufeature ID register user accessors
*
@@ -1503,7 +1542,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
ID_UNALLOCATED(4,7),
/* CRm=5 */
- ID_SANITISED(ID_AA64DFR0_EL1),
+ { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
+ .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
ID_SANITISED(ID_AA64DFR1_EL1),
ID_UNALLOCATED(5,2),
ID_UNALLOCATED(5,3),
--
2.34.1
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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
<kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
kvm@vger.kernel.org
Cc: James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ricardo Koller <ricarkol@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [PATCH v4 11/16] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace
Date: Sun, 13 Nov 2022 16:38:27 +0000 [thread overview]
Message-ID: <20221113163832.3154370-12-maz@kernel.org> (raw)
Message-ID: <20221113163827.zZdaWK7ViB-3JH-sYoG392a08H8KflHvA0P6Zev1ep8@z> (raw)
In-Reply-To: <20221113163832.3154370-1-maz@kernel.org>
Allow userspace to write ID_AA64DFR0_EL1, on the condition that only
the PMUver field can be altered and be at most the one that was
initially computed for the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/sys_regs.c | 42 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1d887fe289d8..3cbcda665d23 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1242,6 +1242,45 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
return 0;
}
+static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd,
+ u64 val)
+{
+ u8 pmuver, host_pmuver;
+ bool valid_pmu;
+
+ host_pmuver = kvm_arm_pmu_get_pmuver_limit();
+
+ /*
+ * Allow AA64DFR0_EL1.PMUver to be set from userspace as long
+ * as it doesn't promise more than what the HW gives us. We
+ * allow an IMPDEF PMU though, only if no PMU is supported
+ * (KVM backward compatibility handling).
+ */
+ pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), val);
+ if ((pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver > host_pmuver))
+ return -EINVAL;
+
+ valid_pmu = (pmuver != 0 && pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF);
+
+ /* Make sure view register and PMU support do match */
+ if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
+ return -EINVAL;
+
+ /* We can only differ with PMUver, and anything else is an error */
+ val ^= read_id_reg(vcpu, rd);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer);
+ if (val)
+ return -EINVAL;
+
+ if (valid_pmu)
+ vcpu->kvm->arch.dfr0_pmuver.imp = pmuver;
+ else
+ vcpu->kvm->arch.dfr0_pmuver.unimp = pmuver;
+
+ return 0;
+}
+
/*
* cpufeature ID register user accessors
*
@@ -1503,7 +1542,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
ID_UNALLOCATED(4,7),
/* CRm=5 */
- ID_SANITISED(ID_AA64DFR0_EL1),
+ { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg,
+ .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, },
ID_SANITISED(ID_AA64DFR1_EL1),
ID_UNALLOCATED(5,2),
ID_UNALLOCATED(5,3),
--
2.34.1
next prev parent reply other threads:[~2022-11-13 16:46 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 16:38 [PATCH v4 00/16] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 01/16] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 02/16] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-16 7:15 ` Reiji Watanabe
2022-11-16 7:15 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 03/16] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 04/16] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-12-01 16:47 ` Ricardo Koller
2022-12-01 16:47 ` Ricardo Koller
2022-12-01 16:51 ` Ricardo Koller
2022-12-01 16:51 ` Ricardo Koller
2022-12-05 12:05 ` Marc Zyngier
2022-12-05 12:05 ` Marc Zyngier
2022-12-05 18:50 ` Ricardo Koller
2022-12-05 18:50 ` Ricardo Koller
2022-11-13 16:38 ` [PATCH v4 05/16] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-17 6:50 ` Reiji Watanabe
2022-11-17 6:50 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 06/16] KVM: arm64: PMU: Only narrow counters that are not 64bit wide Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-17 6:54 ` Reiji Watanabe
2022-11-17 6:54 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 07/16] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-18 6:16 ` Reiji Watanabe
2022-11-18 6:16 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 08/16] KVM: arm64: PMU: Simplify setting a counter to a specific value Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 09/16] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-18 7:45 ` Reiji Watanabe
2022-11-18 7:45 ` Reiji Watanabe
2022-11-19 12:32 ` Marc Zyngier
2022-11-19 12:32 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 10/16] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier [this message]
2022-11-13 16:38 ` [PATCH v4 11/16] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-11-19 5:31 ` Reiji Watanabe
2022-11-19 5:31 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 12/16] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-19 5:52 ` Reiji Watanabe
2022-11-19 5:52 ` Reiji Watanabe
2022-11-19 12:54 ` Marc Zyngier
2022-11-19 12:54 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 13/16] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-23 5:58 ` Reiji Watanabe
2022-11-23 5:58 ` Reiji Watanabe
2022-11-23 11:11 ` Marc Zyngier
2022-11-23 11:11 ` Marc Zyngier
2022-11-23 17:11 ` Reiji Watanabe
2022-11-23 17:11 ` Reiji Watanabe
2022-11-24 10:17 ` Marc Zyngier
2022-11-24 10:17 ` Marc Zyngier
2022-11-29 3:03 ` Reiji Watanabe
2022-11-29 3:03 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 14/16] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-23 6:07 ` Reiji Watanabe
2022-11-23 6:07 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 15/16] KVM: arm64: PMU: Simplify vcpu computation on perf overflow notification Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-23 6:27 ` Reiji Watanabe
2022-11-23 6:27 ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 16/16] KVM: arm64: PMU: Make kvm_pmc the main data structure Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
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