Re: [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5

[Sascha Bischoff <Sascha.Bischoff@arm.com>]

On Fri, 2026-08-07 at 16:55 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential
> issue(s) to consider:
> - [High] Restricting user-space writes to VGICv5 system registers,
> IRS MMIO registers, and IST state after a VCPU has run prevents VM
> soft reset.
> --
> 
> --- Patch [36]: [PATCH v5 36/49] Documentation: KVM: Document
> KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 ---
> commit 5be826b5b86ddbcfa778f582ad314ba1e4599113
> Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
> 
> Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for
> VGICv5
>     
> This commit documents the KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS API for
> the virtual
> GICv5, defining the register layout, supported system registers, and
> error
> codes.
> 
> > diff --git a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> > b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> > index c782ea4d4609c..7e41d6699538f 100644
> > --- a/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> > +++ b/Documentation/virt/kvm/devices/arm-vgic-v5.rst
> [ ... ]
> > +  Errors:
> > +
> > +    ======= 
> > =============================================================
> > +    -ENXIO   Getting or setting this register is not supported
> > +    -EBUSY   VCPU is running, or write attempted after a VCPU has
> > run
> 
> [Severity: High]
> Does returning -EBUSY when a write is attempted after a VCPU has run
> prevent
> VM soft resets?
> 
> During a soft reset (such as PSCI SYSTEM_RESET), QEMU typically
> pauses the
> vCPUs and rewrites the initial state of the GIC device while the KVM
> VM is
> still considered to have run once, since it doesn't destroy and
> recreate the
> entire KVM VM.
> 
> If KVM enforces this restriction on KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
> and
> other device states, won't this reject QEMU's state restore sequence
> and
> prevent the VM from rebooting gracefully?

This is a good point, but I don't think that we can realistically work
this into the existing APIs.

I think we will actually need an explicit
KVM_DEV_ARM_VGIC_V5_CTRL_RESET or similar, like we already have for the
ITS (KVM_DEV_ARM_ITS_CTRL_RESET). The problem we have is that GICv5
manages the state of interrupts in hardware, so on a reset we pretty
much need to make the VM invalid, tear down the ISTs, reallocate a
clean SPI IST, zero KVM's PPI/SPI shadow state, reset the IRS MMIO
register state, and then make the VM valid again. Either that or we let
state persist across that boundary, in which case YMMV.

Is this something that we'd be happy to address later, or should I work
this into the current series?

> 
> > +    -EINVAL  Invalid mpidr or register value supplied
> > +    ======= 
> > =============================================================
> 
Thanks,
Sascha