From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "sashiko-reviews@lists.linux.dev" <sashiko-reviews@lists.linux.dev>
Cc: "maz@kernel.org" <maz@kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"oupton@kernel.org" <oupton@kernel.org>, nd <nd@arm.com>
Subject: Re: [PATCH v5 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test
Date: Fri, 4 Sep 2026 10:57:56 +0000 [thread overview]
Message-ID: <89f6657a33eb18b9641dbee38ed4b71320e72a16.camel@arm.com> (raw)
In-Reply-To: <20260807175645.0FF0F1F000E9@smtp.kernel.org>
On Fri, 2026-08-07 at 17:56 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential
> issue(s) to consider:
> - [Medium] The VGICv5 sparse vCPU IDs test uses an out-of-bounds vCPU
> ID of 512 to verify GICv5 VPE ID validation, but KVM core globally
> rejects IDs >= 512, making the test a false positive.
> - [Medium] The VGICv5 sparse vCPU IDs test hardcodes a vCPU ID of 17,
> which will cause spurious test failures on hardware that supports 16
> or fewer VPEs per VM.
> --
>
> --- Patch [49]: [PATCH v5 49/49] KVM: selftests: Add VGICv5 sparse
> vCPU IDs test ---
> commit 253db5fcbd1548e3eb0e84e65ece4ca5747e50c2
> Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
>
> KVM: selftests: Add VGICv5 sparse vCPU IDs test
>
> GICv5 uses the userspace-provided vCPU ID as the VPE ID. This must
> work when vCPU IDs are sparse and differ from the dense internal vCPU
> index.
>
> Add a test that creates vCPUs with IDs 17 and 3, verifies that a vCPU
> with ID 512 is rejected after a GICv5 has been created, and runs both
> vCPUs to check that ICC_IAFFIDR_EL1 reports the correct VPE IDs on
> each.
>
> > diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c
> > b/tools/testing/selftests/kvm/arm64/vgic_v5.c
> > index 47e147bc14b87..3eef2d2da595f 100644
> > --- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
> > +++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c
> > @@ -14,6 +14,10 @@
>
> [ ... ]
>
> > +static void test_vgic_v5_sparse_vcpu_ids(void)
> > +{
> > + struct kvm_vcpu *vcpus[VGIC_V5_SPARSE_NR_VCPUS];
> > + const u32 vcpu_ids[VGIC_V5_SPARSE_NR_VCPUS] = {
> > + VGIC_V5_SPARSE_VCPU0_ID,
> > + VGIC_V5_SPARSE_VCPU1_ID,
> > + };
> > + int ret, i;
> > + struct ucall uc;
> > + struct vm_gic v;
> > + u64 attr;
> > +
> > + v.gic_dev_type = KVM_DEV_TYPE_ARM_VGIC_V5;
> > + v.vm = __vm_create(VM_SHAPE_DEFAULT,
> > VGIC_V5_SPARSE_NR_VCPUS, 0);
> > + v.gic_fd = kvm_create_device(v.vm, v.gic_dev_type);
> > +
> > + /*
> > + * A GICv5 VM cannot create a vCPU outside the VPE ID
> > range. We've
> > + * already created a GICv5, so it should reject VCPU
> > creation.
> > + */
> > + ret = __vm_ioctl(v.vm, KVM_CREATE_VCPU,
> > + (void *)(unsigned
> > long)VGIC_V5_SPARSE_TOO_BIG_ID);
> > + TEST_ASSERT(ret < 0 && errno == EINVAL,
> > + "GICv5 accepted vCPU ID %u",
> > VGIC_V5_SPARSE_TOO_BIG_ID);
>
> [Severity: Medium]
> Will this test actually verify the GICv5 validation logic as
> intended?
>
> The test unconditionally calls KVM_CREATE_VCPU with
> VGIC_V5_SPARSE_TOO_BIG_ID
> (which is 512). The KVM core's kvm_vm_ioctl_create_vcpu() will
> immediately
> return -EINVAL because the ID is >= KVM_MAX_VCPU_IDS (which defaults
> to 512
> on ARM64).
>
> This happens before any architecture-specific or GICv5 validation is
> reached,
> potentially making this test a false positive.
Ah, yes. This test is useless. I've dropped it.
>
> > +
> > + /* Now, create two vCPUs with legal, albeit sparse, IDs */
> > + for (i = 0; i < ARRAY_SIZE(vcpus); i++) {
> > + vcpus[i] = vm_vcpu_add(v.vm, vcpu_ids[i],
> > guest_iaffid_code);
> > + TEST_ASSERT(vcpus[i], "Failed to create vCPU %u",
> > vcpu_ids[i]);
>
> [Severity: Medium]
> Could hardcoding the vCPU ID to 17 cause spurious test failures on
> some
> hardware?
>
> The test unconditionally adds a vCPU with ID 17
> (VGIC_V5_SPARSE_VCPU0_ID).
> In KVM ARM64, a VM's max_vcpus is bounded by hardware capabilities
> (for
> example, GICV5_IRS_IDR4_VPE_ID_BITS).
>
> If the hardware supports 16 or fewer VPEs per VM, the KVM_CREATE_VCPU
> ioctl
> for ID 17 will be legitimately rejected by KVM with -EINVAL, which
> triggers
> this TEST_ASSERT and fails the test.
The hardware supports at least 256 VPEs per VM. Anything less is not
allowed as per the specification. Hence, this one is not an issue.
>
> > + }
>
Thanks,
Sascha
prev parent reply other threads:[~2026-09-04 10:58 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-07 11:12 [PATCH v5 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-08-07 11:53 ` sashiko-bot
2026-09-03 14:20 ` Sascha Bischoff
2026-08-07 11:14 ` [PATCH v5 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-08-07 12:01 ` sashiko-bot
2026-09-03 14:22 ` Sascha Bischoff
2026-08-07 13:44 ` Lorenzo Pieralisi
2026-09-03 14:25 ` Sascha Bischoff
2026-08-07 11:14 ` [PATCH v5 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-08-07 12:05 ` sashiko-bot
2026-09-03 14:34 ` Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-08-07 12:17 ` sashiko-bot
2026-09-03 16:33 ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-08-07 12:27 ` sashiko-bot
2026-09-04 6:36 ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-08-07 12:45 ` sashiko-bot
2026-09-04 7:27 ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-08-07 12:50 ` sashiko-bot
2026-09-04 8:00 ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-08-07 13:07 ` sashiko-bot
2026-09-04 8:08 ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-08-07 13:13 ` sashiko-bot
2026-09-04 8:15 ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 12/49] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-08-07 13:30 ` sashiko-bot
2026-09-04 10:03 ` Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-08-07 13:42 ` sashiko-bot
2026-09-04 8:22 ` Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-08-07 14:17 ` sashiko-bot
2026-09-04 8:31 ` Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-08-07 11:22 ` [PATCH v5 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-08-07 14:27 ` sashiko-bot
2026-09-04 8:42 ` Sascha Bischoff
2026-08-07 11:22 ` [PATCH v5 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-08-07 14:34 ` sashiko-bot
2026-09-04 8:47 ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-08-07 14:49 ` sashiko-bot
2026-09-04 8:51 ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-08-07 14:52 ` sashiko-bot
2026-09-04 8:57 ` Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-08-07 15:04 ` sashiko-bot
2026-09-04 9:03 ` Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-08-07 15:14 ` sashiko-bot
2026-09-04 9:28 ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-08-07 15:23 ` sashiko-bot
2026-09-04 9:22 ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-08-07 15:29 ` sashiko-bot
2026-09-04 9:30 ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-08-07 15:40 ` sashiko-bot
2026-09-04 9:47 ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-08-07 16:27 ` sashiko-bot
2026-09-04 10:01 ` Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-08-07 16:20 ` sashiko-bot
2026-09-04 9:59 ` Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-08-07 16:30 ` sashiko-bot
2026-09-04 10:06 ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-08-07 16:48 ` sashiko-bot
2026-09-04 10:23 ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-08-07 16:55 ` sashiko-bot
2026-09-04 11:04 ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-08-07 16:52 ` sashiko-bot
2026-09-04 10:09 ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-08-07 17:12 ` sashiko-bot
2026-09-04 10:15 ` Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-08-07 17:17 ` sashiko-bot
2026-09-04 10:38 ` Sascha Bischoff
2026-08-07 11:34 ` [PATCH v5 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-08-07 17:21 ` sashiko-bot
2026-09-04 10:45 ` Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-08-07 17:39 ` sashiko-bot
2026-09-04 10:48 ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-08-07 17:50 ` sashiko-bot
2026-09-04 10:54 ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
2026-08-07 17:56 ` sashiko-bot
2026-09-04 10:57 ` Sascha Bischoff [this message]
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