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From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Josef Lusticky <josef@lusticky.cz>
Cc: wens@csie.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs.
Date: Wed, 23 Jan 2019 11:36:26 +0100	[thread overview]
Message-ID: <20190123103626.edhd6bqerze5q2sr@flea> (raw)
In-Reply-To: <20190123094334.11030-1-josef@lusticky.cz>


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Hi Joseph,

On Wed, Jan 23, 2019 at 10:43:31AM +0100, Josef Lusticky wrote:
> This patch series adds SPI pinctrl nodes to sun5i SoCs.
> 
> While spi0 is common to all A10s, A13 and GR8 (PATCH 1/3),
> spi2 has alternate pins on the PB bank only on A10s (already in sun5i-a10s.dtsi) and GR8 (PATCH 2/3).
> 
> The spi1_cs1 is only available on A10s (PATCH 3/3).
> 
> The spi1_cs1 is potentially available on GR8 as well
> (at least it is specified in drivers/pinctrl/sunxi/pinctrl-sun5i.c),
> but I was not able to find it in the datasheet.
> The same applies to spi2_cs1.
> 
> Both spi1_cs1 and spi2_cs1 can be added later to sun5i-gr8.dtsi.

Thanks for your patches, unfortunately, in order to keep the DT size
reasonable, if there's no user of the pinctrl node we don't merge
them. If you have a board that would use it, you can still send those
changes at the same time.

Thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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      parent reply	other threads:[~2019-01-23 10:36 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-23  9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
2019-01-23  9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
2019-01-23  9:43 ` [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins Josef Lusticky
2019-01-23  9:43 ` [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin Josef Lusticky
2019-01-23 10:36 ` Maxime Ripard [this message]

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