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From: Josef Lusticky <josef@lusticky.cz>
To: linux-arm-kernel@lists.infradead.org
Cc: maxime.ripard@bootlin.com, wens@csie.org,
	Josef Lusticky <josef@lusticky.cz>
Subject: [PATCH 2/3] ARM: dts: sun5i: GR8: Add SPI2 PB pins
Date: Wed, 23 Jan 2019 10:43:33 +0100	[thread overview]
Message-ID: <20190123094334.11030-3-josef@lusticky.cz> (raw)
In-Reply-To: <20190123094334.11030-1-josef@lusticky.cz>

Add a separate pinctrl nodes for the SPI2 pins on the GR8 PB bank.

Signed-off-by: Josef Lusticky <josef@lusticky.cz>
---
 arch/arm/boot/dts/sun5i-gr8.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi
index 98a8fd5e89e8..a26a6a7d7c6b 100644
--- a/arch/arm/boot/dts/sun5i-gr8.dtsi
+++ b/arch/arm/boot/dts/sun5i-gr8.dtsi
@@ -119,6 +119,16 @@
 		bias-pull-up;
 	};
 
+	spi2_pb_pins: spi2-pb-pins {
+		pins = "PB12", "PB13", "PB14";
+		function = "spi2";
+	};
+
+	spi2_cs0_pb_pin: spi2-cs0-pb-pin {
+		pins = "PB11";
+		function = "spi2";
+	};
+
 	uart1_cts_rts_pins: uart1-cts-rts-pins {
 		pins = "PG5", "PG6";
 		function = "uart1";
-- 
2.20.1


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  parent reply	other threads:[~2019-01-23  9:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-23  9:43 [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Josef Lusticky
2019-01-23  9:43 ` [PATCH 1/3] ARM: dts: sun5i: Add SPI0 pins Josef Lusticky
2019-01-23  9:43 ` Josef Lusticky [this message]
2019-01-23  9:43 ` [PATCH 3/3] ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin Josef Lusticky
2019-01-23 10:36 ` [PATCH 0/3] Add SPI pinctrl nodes to sun5i SoCs Maxime Ripard

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