* [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-28 14:26 ` Will Deacon
2022-06-22 17:43 ` [PATCH v5 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
` (25 subsequent siblings)
26 siblings, 1 reply; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT
I-caches") we removed all the support fir AIVIVT cache types and renamed
all references to the field to say "unknown" since support for AIVIVT
caches was removed from the architecture. Some confusion has resulted since
the corresponding change to the architecture left the value named as
AIVIVT but documented it as reserved in v8, refactor the code so we don't
define the constant instead. This will help with automatic generation of
this register field since it means we care less about the correspondence
with the ARM.
No functional change, the value displayed to userspace is unchanged.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/cache.h | 1 -
arch/arm64/kernel/cpuinfo.c | 27 +++++++++++++++++----------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 7c2181c72116..0cbe75b9e4e5 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -25,7 +25,6 @@
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
#define ICACHE_POLICY_VPIPT 0
-#define ICACHE_POLICY_RESERVED 1
#define ICACHE_POLICY_VIPT 2
#define ICACHE_POLICY_PIPT 3
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 8eff0a34ffd4..7ecf9ffb590b 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -33,12 +33,19 @@
DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
static struct cpuinfo_arm64 boot_cpu_data;
-static const char *icache_policy_str[] = {
- [ICACHE_POLICY_VPIPT] = "VPIPT",
- [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
- [ICACHE_POLICY_VIPT] = "VIPT",
- [ICACHE_POLICY_PIPT] = "PIPT",
-};
+static inline const char *icache_policy_str(int l1ip)
+{
+ switch (l1ip) {
+ case ICACHE_POLICY_VPIPT:
+ return "VPIPT";
+ case ICACHE_POLICY_VIPT:
+ return "VIPT";
+ case ICACHE_POLICY_PIPT:
+ return "PIPT";
+ default:
+ return "RESERVED/UNKNOWN";
+ }
+}
unsigned long __icache_flags;
@@ -342,19 +349,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
u32 l1ip = CTR_L1IP(info->reg_ctr);
switch (l1ip) {
- case ICACHE_POLICY_PIPT:
- break;
case ICACHE_POLICY_VPIPT:
set_bit(ICACHEF_VPIPT, &__icache_flags);
break;
- case ICACHE_POLICY_RESERVED:
case ICACHE_POLICY_VIPT:
/* Assume aliasing */
set_bit(ICACHEF_ALIASING, &__icache_flags);
break;
+ case ICACHE_POLICY_PIPT:
+ default:
+ break;
}
- pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
+ pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
}
static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type
2022-06-22 17:43 ` [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
@ 2022-06-28 14:26 ` Will Deacon
0 siblings, 0 replies; 29+ messages in thread
From: Will Deacon @ 2022-06-28 14:26 UTC (permalink / raw)
To: Mark Brown; +Cc: Catalin Marinas, Mark Rutland, Joey Gouly, linux-arm-kernel
On Wed, Jun 22, 2022 at 06:43:50PM +0100, Mark Brown wrote:
> In 155433cb365ee466 ("arm64: cache: Remove support for ASID-tagged VIVT
> I-caches") we removed all the support fir AIVIVT cache types and renamed
s/fir/for/
> all references to the field to say "unknown" since support for AIVIVT
> caches was removed from the architecture. Some confusion has resulted since
> the corresponding change to the architecture left the value named as
> AIVIVT but documented it as reserved in v8, refactor the code so we don't
> define the constant instead. This will help with automatic generation of
> this register field since it means we care less about the correspondence
> with the ARM.
>
> No functional change, the value displayed to userspace is unchanged.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/cache.h | 1 -
> arch/arm64/kernel/cpuinfo.c | 27 +++++++++++++++++----------
> 2 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index 7c2181c72116..0cbe75b9e4e5 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -25,7 +25,6 @@
> #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
>
> #define ICACHE_POLICY_VPIPT 0
> -#define ICACHE_POLICY_RESERVED 1
> #define ICACHE_POLICY_VIPT 2
> #define ICACHE_POLICY_PIPT 3
>
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index 8eff0a34ffd4..7ecf9ffb590b 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -33,12 +33,19 @@
> DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
> static struct cpuinfo_arm64 boot_cpu_data;
>
> -static const char *icache_policy_str[] = {
> - [ICACHE_POLICY_VPIPT] = "VPIPT",
> - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
> - [ICACHE_POLICY_VIPT] = "VIPT",
> - [ICACHE_POLICY_PIPT] = "PIPT",
> -};
> +static inline const char *icache_policy_str(int l1ip)
> +{
> + switch (l1ip) {
> + case ICACHE_POLICY_VPIPT:
> + return "VPIPT";
> + case ICACHE_POLICY_VIPT:
> + return "VIPT";
> + case ICACHE_POLICY_PIPT:
> + return "PIPT";
> + default:
> + return "RESERVED/UNKNOWN";
> + }
Looks like the indentation has gone wonky here.
> unsigned long __icache_flags;
>
> @@ -342,19 +349,19 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
> u32 l1ip = CTR_L1IP(info->reg_ctr);
>
> switch (l1ip) {
> - case ICACHE_POLICY_PIPT:
> - break;
> case ICACHE_POLICY_VPIPT:
> set_bit(ICACHEF_VPIPT, &__icache_flags);
> break;
> - case ICACHE_POLICY_RESERVED:
> case ICACHE_POLICY_VIPT:
> /* Assume aliasing */
> set_bit(ICACHEF_ALIASING, &__icache_flags);
> break;
Shouldn't we still assume aliasing if we see an I-cache that we don't know
about?
Will
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v5 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
2022-06-22 17:43 ` [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
` (24 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Currently we only accept comments where the # is placed at the start of a
line, allow leading blanks so we can format comments inside definitions in
a more pleasing manner.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/tools/gen-sysreg.awk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index 5c55509eb43f..db461921d256 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -88,7 +88,7 @@ END {
# skip blank lines and comment lines
/^$/ { next }
-/^#/ { next }
+/^[\t ]*#/ { next }
/^SysregFields/ {
change_block("SysregFields", "None", "SysregFields")
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
2022-06-22 17:43 ` [PATCH v5 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
2022-06-22 17:43 ` [PATCH v5 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
` (23 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
In subsequent patches sysreg.h and gpr-num.h will be included from other
headers which can be included from linker scripts (e.g. via cache.h), and
contain assember macro directives that don't work in linker scripts (e.g.
`.macro` and `.irp`).
To avoid needing LINKER_SCRIPT guards in every file which could have a
transitive dependency, add those directly to sysreg.h and gpr-num.h.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/gpr-num.h | 3 +++
arch/arm64/include/asm/sysreg.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/arch/arm64/include/asm/gpr-num.h b/arch/arm64/include/asm/gpr-num.h
index 05da4a7c5788..72c44f63fb41 100644
--- a/arch/arm64/include/asm/gpr-num.h
+++ b/arch/arm64/include/asm/gpr-num.h
@@ -4,12 +4,15 @@
#ifdef __ASSEMBLY__
+#ifndef LINKER_SCRIPT
+
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
.equ .L__gpr_num_x\num, \num
.equ .L__gpr_num_w\num, \num
.endr
.equ .L__gpr_num_xzr, 31
.equ .L__gpr_num_wzr, 31
+#endif /* !LINKER_SCRIPT */
#else /* __ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 42ff95dba6da..6c7be1a2114b 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1219,6 +1219,7 @@
#ifdef __ASSEMBLY__
+#ifndef LINKER_SCRIPT
.macro mrs_s, rt, sreg
__emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
.endm
@@ -1226,6 +1227,7 @@
.macro msr_s, sreg, rt
__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
.endm
+#endif /* !LINKER_SCRIPT */
#else
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (2 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
` (22 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Add a SYS_FIELD_GET() helper to match SYS_FIELD_PREP(), providing a
simplified interface to FIELD_GET() when using the generated defines
with standardized naming.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---
arch/arm64/include/asm/sysreg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6c7be1a2114b..0f5771ac5b94 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1326,6 +1326,9 @@
#endif
+#define SYS_FIELD_GET(reg, field, val) \
+ FIELD_GET(reg##_##field##_MASK, val)
+
#define SYS_FIELD_PREP(reg, field, val) \
FIELD_PREP(reg##_##field##_MASK, val)
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (3 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
` (21 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
cache.h contains some defines which are used to represent fields and
enumeration values which do not follow the standard naming convention used for
when we automatically generate defines for system registers. Update the
names of the constants to reflect standardised naming and move them to
sysreg.h.
There is also a helper CTR_L1IP() which was open coded and has been
converted to use SYS_FIELD_GET().
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/cache.h | 28 +++++++---------------------
arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++
arch/arm64/kernel/alternative.c | 2 +-
arch/arm64/kernel/cpu_errata.c | 2 +-
arch/arm64/kernel/cpufeature.c | 20 ++++++++++----------
arch/arm64/kernel/cpuinfo.c | 12 ++++++------
arch/arm64/kernel/traps.c | 6 +++---
7 files changed, 43 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 0cbe75b9e4e5..3abedf304ec1 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -7,31 +7,17 @@
#include <asm/cputype.h>
#include <asm/mte-def.h>
-
-#define CTR_L1IP_SHIFT 14
-#define CTR_L1IP_MASK 3
-#define CTR_DMINLINE_SHIFT 16
-#define CTR_IMINLINE_SHIFT 0
-#define CTR_IMINLINE_MASK 0xf
-#define CTR_ERG_SHIFT 20
-#define CTR_CWG_SHIFT 24
-#define CTR_CWG_MASK 15
-#define CTR_IDC_SHIFT 28
-#define CTR_DIC_SHIFT 29
+#include <asm/sysreg.h>
#define CTR_CACHE_MINLINE_MASK \
- (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
-
-#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
+ (0xf << CTR_EL0_DMINLINE_SHIFT | \
+ CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
-#define ICACHE_POLICY_VPIPT 0
-#define ICACHE_POLICY_VIPT 2
-#define ICACHE_POLICY_PIPT 3
+#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
#define L1_CACHE_SHIFT (6)
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
#define CLIDR_LOUU_SHIFT 27
#define CLIDR_LOC_SHIFT 24
#define CLIDR_LOUIS_SHIFT 21
@@ -85,7 +71,7 @@ static __always_inline int icache_is_vpipt(void)
static inline u32 cache_type_cwg(void)
{
- return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
+ return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;
}
#define __read_mostly __section(".data..read_mostly")
@@ -119,12 +105,12 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
{
u32 ctr = read_cpuid_cachetype();
- if (!(ctr & BIT(CTR_IDC_SHIFT))) {
+ if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
u64 clidr = read_sysreg(clidr_el1);
if (CLIDR_LOC(clidr) == 0 ||
(CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
- ctr |= BIT(CTR_IDC_SHIFT);
+ ctr |= BIT(CTR_EL0_IDC_SHIFT);
}
return ctr;
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0f5771ac5b94..19c6eabfec7c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1084,6 +1084,21 @@
#define MVFR2_FPMISC_SHIFT 4
#define MVFR2_SIMDMISC_SHIFT 0
+#define CTR_EL0_L1Ip_VPIPT 0
+#define CTR_EL0_L1Ip_VIPT 2
+#define CTR_EL0_L1Ip_PIPT 3
+
+#define CTR_EL0_L1Ip_SHIFT 14
+#define CTR_EL0_L1Ip_MASK 3
+#define CTR_EL0_DminLine_SHIFT 16
+#define CTR_EL0_IminLine_SHIFT 0
+#define CTR_EL0_IminLine_MASK 0xf
+#define CTR_EL0_ERG_SHIFT 20
+#define CTR_EL0_CWG_SHIFT 24
+#define CTR_EL0_CWG_MASK 15
+#define CTR_EL0_IDC_SHIFT 28
+#define CTR_EL0_DIC_SHIFT 29
+
#define DCZID_DZP_SHIFT 4
#define DCZID_BS_SHIFT 0
diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
index 7bbf5104b7b7..9bcaa5eacf16 100644
--- a/arch/arm64/kernel/alternative.c
+++ b/arch/arm64/kernel/alternative.c
@@ -121,7 +121,7 @@ static void clean_dcache_range_nopatch(u64 start, u64 end)
ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
d_size = 4 << cpuid_feature_extract_unsigned_field(ctr_el0,
- CTR_DMINLINE_SHIFT);
+ CTR_EL0_DminLine_SHIFT);
cur = start & ~(d_size - 1);
do {
/*
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index c05cc3b6162e..a0dd3ea8f585 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -187,7 +187,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
int scope)
{
u32 midr = read_cpuid_id();
- bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
+ bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);
const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8d88433de81d..b7cd50eb6d8a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -396,18 +396,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
static const struct arm64_ftr_bits ftr_ctr[] = {
ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
/*
* Linux can handle differing I-cache policies. Userspace JITs will
* make use of *minLine.
* If we have differing I-cache policies, report it as the weakest - VIPT.
*/
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -1480,7 +1480,7 @@ static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
else
ctr = read_cpuid_effective_cachetype();
- return ctr & BIT(CTR_IDC_SHIFT);
+ return ctr & BIT(CTR_EL0_IDC_SHIFT);
}
static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
@@ -1491,7 +1491,7 @@ static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unu
* to the CTR_EL0 on this CPU and emulate it with the real/safe
* value.
*/
- if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
+ if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
}
@@ -1505,7 +1505,7 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
else
ctr = read_cpuid_cachetype();
- return ctr & BIT(CTR_DIC_SHIFT);
+ return ctr & BIT(CTR_EL0_DIC_SHIFT);
}
static bool __maybe_unused
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 7ecf9ffb590b..e44411ff909c 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -36,11 +36,11 @@ static struct cpuinfo_arm64 boot_cpu_data;
static inline const char *icache_policy_str(int l1ip)
{
switch (l1ip) {
- case ICACHE_POLICY_VPIPT:
+ case CTR_EL0_L1Ip_VPIPT:
return "VPIPT";
- case ICACHE_POLICY_VIPT:
+ case CTR_EL0_L1Ip_VIPT:
return "VIPT";
- case ICACHE_POLICY_PIPT:
+ case CTR_EL0_L1Ip_PIPT:
return "PIPT";
default:
return "RESERVED/UNKNOWN";
@@ -349,14 +349,14 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
u32 l1ip = CTR_L1IP(info->reg_ctr);
switch (l1ip) {
- case ICACHE_POLICY_VPIPT:
+ case CTR_EL0_L1Ip_VPIPT:
set_bit(ICACHEF_VPIPT, &__icache_flags);
break;
- case ICACHE_POLICY_VIPT:
+ case CTR_EL0_L1Ip_VIPT:
/* Assume aliasing */
set_bit(ICACHEF_ALIASING, &__icache_flags);
break;
- case ICACHE_POLICY_PIPT:
+ case CTR_EL0_L1Ip_PIPT:
default:
break;
}
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 9ac7a81b79be..b7fed33981f7 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -579,11 +579,11 @@ static void ctr_read_handler(unsigned long esr, struct pt_regs *regs)
if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
/* Hide DIC so that we can trap the unnecessary maintenance...*/
- val &= ~BIT(CTR_DIC_SHIFT);
+ val &= ~BIT(CTR_EL0_DIC_SHIFT);
/* ... and fake IminLine to reduce the number of traps. */
- val &= ~CTR_IMINLINE_MASK;
- val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
+ val &= ~CTR_EL0_IminLine_MASK;
+ val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK;
}
pt_regs_write_reg(regs, rt, val);
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (4 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 07/27] arm64/mte: Standardise GMID field name definitions Mark Brown
` (20 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
The constants defining field names for DCZID_EL0 do not include the _EL0
that is included as part of our standard naming scheme. In preparation
for automatic generation of the defines add the _EL0 in. No functional
change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 19c6eabfec7c..0af7ee9b314d 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1099,8 +1099,8 @@
#define CTR_EL0_IDC_SHIFT 28
#define CTR_EL0_DIC_SHIFT 29
-#define DCZID_DZP_SHIFT 4
-#define DCZID_BS_SHIFT 0
+#define DCZID_EL0_DZP_SHIFT 4
+#define DCZID_EL0_BS_SHIFT 0
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b7cd50eb6d8a..b9c5b11c17c3 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -453,8 +453,8 @@ static const struct arm64_ftr_bits ftr_mvfr2[] = {
};
static const struct arm64_ftr_bits ftr_dczid[] = {
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
ARM64_FTR_END,
};
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 07/27] arm64/mte: Standardise GMID field name definitions
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (5 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
` (19 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Usually our defines for bitfields in system registers do not include a SYS_
prefix but those for GMID do. In preparation for automatic generation of
defines remove that prefix. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 4 ++--
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/lib/mte.S | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0af7ee9b314d..ae86b422ac74 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -1136,8 +1136,8 @@
#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
/* GMID_EL1 field definitions */
-#define SYS_GMID_EL1_BS_SHIFT 0
-#define SYS_GMID_EL1_BS_SIZE 4
+#define GMID_EL1_BS_SHIFT 0
+#define GMID_EL1_BS_SIZE 4
/* TFSR{,E0}_EL1 bit definitions */
#define SYS_TFSR_EL1_TF0_SHIFT 0
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b9c5b11c17c3..7d838b5f7e20 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -459,7 +459,7 @@ static const struct arm64_ftr_bits ftr_dczid[] = {
};
static const struct arm64_ftr_bits ftr_gmid[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
ARM64_FTR_END,
};
diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S
index eeb9e45bcce8..1b7c93ae7e63 100644
--- a/arch/arm64/lib/mte.S
+++ b/arch/arm64/lib/mte.S
@@ -18,7 +18,7 @@
*/
.macro multitag_transfer_size, reg, tmp
mrs_s \reg, SYS_GMID_EL1
- ubfx \reg, \reg, #SYS_GMID_EL1_BS_SHIFT, #SYS_GMID_EL1_BS_SIZE
+ ubfx \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE
mov \tmp, #4
lsl \reg, \tmp, \reg
.endm
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (6 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 07/27] arm64/mte: Standardise GMID field name definitions Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
` (18 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
The defines used for the pointer authentication feature enumerations do not
follow the naming convention we've decided to use where we name things
after the architecture feature that introduced. Prepare for generating the
defines for the ISA ID registers by updating to use the feature names.
No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 34 ++++++++++++++++-----------------
arch/arm64/kernel/cpufeature.c | 24 +++++++++++------------
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ae86b422ac74..9a7e7b61d3ea 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -721,21 +721,21 @@
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_APA_NI 0x0
-#define ID_AA64ISAR1_APA_ARCHITECTED 0x1
+#define ID_AA64ISAR1_APA_PAuth 0x1
#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
-#define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5
+#define ID_AA64ISAR1_APA_Pauth2 0x3
+#define ID_AA64ISAR1_APA_FPAC 0x4
+#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5
#define ID_AA64ISAR1_API_NI 0x0
-#define ID_AA64ISAR1_API_IMP_DEF 0x1
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5
+#define ID_AA64ISAR1_API_PAuth 0x1
+#define ID_AA64ISAR1_API_EPAC 0x2
+#define ID_AA64ISAR1_API_PAuth2 0x3
+#define ID_AA64ISAR1_API_FPAC 0x4
+#define ID_AA64ISAR1_API_FPACCOMBINE 0x5
#define ID_AA64ISAR1_GPA_NI 0x0
-#define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
+#define ID_AA64ISAR1_GPA_IMP 0x1
#define ID_AA64ISAR1_GPI_NI 0x0
-#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
+#define ID_AA64ISAR1_GPI_IMP 0x1
/* id_aa64isar2 */
#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
@@ -755,14 +755,14 @@
#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
#define ID_AA64ISAR2_APA3_NI 0x0
-#define ID_AA64ISAR2_APA3_ARCHITECTED 0x1
-#define ID_AA64ISAR2_APA3_ARCH_EPAC 0x2
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2 0x3
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC 0x4
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB 0x5
+#define ID_AA64ISAR2_APA3_PAuth 0x1
+#define ID_AA64ISAR2_APA3_EPAC 0x2
+#define ID_AA64ISAR2_APA3_PAuth2 0x3
+#define ID_AA64ISAR2_APA3_FPAC 0x4
+#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5
#define ID_AA64ISAR2_GPA3_NI 0x0
-#define ID_AA64ISAR2_GPA3_ARCHITECTED 0x1
+#define ID_AA64ISAR2_GPA3_IMP 0x1
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7d838b5f7e20..838b3dcd8473 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2317,7 +2317,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_APA_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
+ .min_field_value = ID_AA64ISAR1_APA_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2328,7 +2328,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR2_APA3_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
+ .min_field_value = ID_AA64ISAR2_APA3_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2339,7 +2339,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_API_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
+ .min_field_value = ID_AA64ISAR1_API_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_GPA_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
+ .min_field_value = ID_AA64ISAR1_GPA_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR2_GPA3_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
+ .min_field_value = ID_AA64ISAR2_GPA3_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2377,7 +2377,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_GPI_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
+ .min_field_value = ID_AA64ISAR1_GPI_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2562,15 +2562,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
4, FTR_UNSIGNED,
- ID_AA64ISAR1_APA_ARCHITECTED)
+ ID_AA64ISAR1_APA_PAuth)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
+ 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth)
},
{},
};
@@ -2578,15 +2578,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
+ 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP)
},
{},
};
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (7 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:43 ` [PATCH v5 10/27] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
` (17 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
The architecture refers to the field identifying support for BHB clear as
BC but the kernel has called it CLEARBHB. In preparation for generation of
defines for ID_AA64ISAR2_EL1 rename to use the architecture's naming. No
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/include/asm/sysreg.h | 2 +-
arch/arm64/kernel/cpufeature.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 14a8f3d93add..6472f2badc97 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope)
isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
return cpuid_feature_extract_unsigned_field(isar2,
- ID_AA64ISAR2_CLEARBHB_SHIFT);
+ ID_AA64ISAR2_BC_SHIFT);
}
const struct cpumask *system_32bit_el0_cpumask(void);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9a7e7b61d3ea..478af541410d 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -738,7 +738,7 @@
#define ID_AA64ISAR1_GPI_IMP 0x1
/* id_aa64isar2 */
-#define ID_AA64ISAR2_CLEARBHB_SHIFT 28
+#define ID_AA64ISAR2_BC_SHIFT 28
#define ID_AA64ISAR2_APA3_SHIFT 12
#define ID_AA64ISAR2_GPA3_SHIFT 8
#define ID_AA64ISAR2_RPRES_SHIFT 4
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 838b3dcd8473..0f9c9d8b21a2 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -231,7 +231,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 10/27] arm64/sysreg: Standardise naming for WFxT defines
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (8 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
@ 2022-06-22 17:43 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
` (16 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:43 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
The defines for WFxT refer to the feature as WFXT and use SUPPORTED rather
than IMP. In preparation for automatic generation of defines update these
to be more standard. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 6 +++---
arch/arm64/kernel/cpufeature.c | 8 ++++----
arch/arm64/kvm/sys_regs.c | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 478af541410d..6cd0f3c87267 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -742,7 +742,7 @@
#define ID_AA64ISAR2_APA3_SHIFT 12
#define ID_AA64ISAR2_GPA3_SHIFT 8
#define ID_AA64ISAR2_RPRES_SHIFT 4
-#define ID_AA64ISAR2_WFXT_SHIFT 0
+#define ID_AA64ISAR2_WFxT_SHIFT 0
#define ID_AA64ISAR2_RPRES_8BIT 0x0
#define ID_AA64ISAR2_RPRES_12BIT 0x1
@@ -751,8 +751,8 @@
* reserved, but has not yet been removed from the ARM ARM
* as of ARM DDI 0487G.b.
*/
-#define ID_AA64ISAR2_WFXT_NI 0x0
-#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
+#define ID_AA64ISAR2_WFxT_NI 0x0
+#define ID_AA64ISAR2_WFxT_IMP 0x2
#define ID_AA64ISAR2_APA3_NI 0x0
#define ID_AA64ISAR2_APA3_PAuth 0x1
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0f9c9d8b21a2..83f8e9d360ce 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -237,7 +237,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR2_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR2_WFXT_SHIFT,
+ .field_pos = ID_AA64ISAR2_WFxT_SHIFT,
.field_width = 4,
.matches = has_cpuid_feature,
- .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
+ .min_field_value = ID_AA64ISAR2_WFxT_IMP,
},
{},
};
@@ -2654,7 +2654,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
- HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT),
+ HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c06c0477fab5..f12c6d457677 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1146,7 +1146,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
if (!cpus_have_final_cap(ARM64_HAS_WFXT))
- val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFXT);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT);
break;
case SYS_ID_AA64DFR0_EL1:
/* Limit debug to ARMv8.0 */
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (9 preceding siblings ...)
2022-06-22 17:43 ` [PATCH v5 10/27] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
` (15 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
We have a series of defines for enumeration values we test for in the
fields in ID_AA64SMFR0_EL1 which do not follow our usual convention of
including the EL1 in the name and having _IMP at the end of the basic
"feature present" define. In preparation for automatic register
generation bring the defines into sync with convention, no functional
change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/el2_setup.h | 2 +-
arch/arm64/include/asm/sysreg.h | 30 ++++++++++++++--------------
arch/arm64/kernel/cpufeature.c | 32 +++++++++++++++---------------
3 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 34ceff08cac4..bfd0ad64b598 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -161,7 +161,7 @@
mov x1, #0 // SMCR controls
mrs_s x2, SYS_ID_AA64SMFR0_EL1
- ubfx x2, x2, #ID_AA64SMFR0_FA64_SHIFT, #1 // Full FP in SM?
+ ubfx x2, x2, #ID_AA64SMFR0_EL1_FA64_SHIFT, #1 // Full FP in SM?
cbz x2, .Lskip_sme_fa64_\@
orr x1, x1, SMCR_ELx_FA64_MASK
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6cd0f3c87267..763f0f90dca8 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -834,21 +834,21 @@
#define ID_AA64ZFR0_SVEVER_SVE2 0x1
/* id_aa64smfr0 */
-#define ID_AA64SMFR0_FA64_SHIFT 63
-#define ID_AA64SMFR0_I16I64_SHIFT 52
-#define ID_AA64SMFR0_F64F64_SHIFT 48
-#define ID_AA64SMFR0_I8I32_SHIFT 36
-#define ID_AA64SMFR0_F16F32_SHIFT 35
-#define ID_AA64SMFR0_B16F32_SHIFT 34
-#define ID_AA64SMFR0_F32F32_SHIFT 32
-
-#define ID_AA64SMFR0_FA64 0x1
-#define ID_AA64SMFR0_I16I64 0xf
-#define ID_AA64SMFR0_F64F64 0x1
-#define ID_AA64SMFR0_I8I32 0xf
-#define ID_AA64SMFR0_F16F32 0x1
-#define ID_AA64SMFR0_B16F32 0x1
-#define ID_AA64SMFR0_F32F32 0x1
+#define ID_AA64SMFR0_EL1_FA64_SHIFT 63
+#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52
+#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48
+#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36
+#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35
+#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34
+#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32
+
+#define ID_AA64SMFR0_EL1_FA64_IMP 0x1
+#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf
+#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1
+#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf
+#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1
+#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1
+#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_ECV_SHIFT 60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 83f8e9d360ce..a6c224539ce4 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -298,19 +298,19 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_FA64_SHIFT, 1, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I16I64_SHIFT, 4, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F64F64_SHIFT, 1, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_I8I32_SHIFT, 4, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F16F32_SHIFT, 1, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_B16F32_SHIFT, 1, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
- FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_F32F32_SHIFT, 1, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
ARM64_FTR_END,
};
@@ -2503,9 +2503,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.capability = ARM64_SME_FA64,
.sys_reg = SYS_ID_AA64SMFR0_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64SMFR0_FA64_SHIFT,
+ .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT,
.field_width = 1,
- .min_field_value = ID_AA64SMFR0_FA64,
+ .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP,
.matches = has_cpuid_feature,
.cpu_enable = fa64_kernel_enable,
},
@@ -2657,13 +2657,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I16I64, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F64F64, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_I8I32, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F16F32, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_B16F32, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
- HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_F32F32, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
+ HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
#endif /* CONFIG_ARM64_SME */
{},
};
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (10 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 13/27] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
` (14 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
The various defines for bitfields in ID_AA64ZFR0_EL1 do not follow our
conventions for register field names, they omit the _EL1, they don't use
specific defines for enumeration values and they don't follow the naming
in the architecture in some cases. In preparation for automatic generation
bring them into line with convention. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 40 ++++++++++++++++-----------------
arch/arm64/kernel/cpufeature.c | 38 +++++++++++++++----------------
2 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 763f0f90dca8..899e1e52b2b2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -812,26 +812,26 @@
#define ID_AA64PFR1_MTE_ASYMM 0x3
/* id_aa64zfr0 */
-#define ID_AA64ZFR0_F64MM_SHIFT 56
-#define ID_AA64ZFR0_F32MM_SHIFT 52
-#define ID_AA64ZFR0_I8MM_SHIFT 44
-#define ID_AA64ZFR0_SM4_SHIFT 40
-#define ID_AA64ZFR0_SHA3_SHIFT 32
-#define ID_AA64ZFR0_BF16_SHIFT 20
-#define ID_AA64ZFR0_BITPERM_SHIFT 16
-#define ID_AA64ZFR0_AES_SHIFT 4
-#define ID_AA64ZFR0_SVEVER_SHIFT 0
-
-#define ID_AA64ZFR0_F64MM 0x1
-#define ID_AA64ZFR0_F32MM 0x1
-#define ID_AA64ZFR0_I8MM 0x1
-#define ID_AA64ZFR0_BF16 0x1
-#define ID_AA64ZFR0_SM4 0x1
-#define ID_AA64ZFR0_SHA3 0x1
-#define ID_AA64ZFR0_BITPERM 0x1
-#define ID_AA64ZFR0_AES 0x1
-#define ID_AA64ZFR0_AES_PMULL 0x2
-#define ID_AA64ZFR0_SVEVER_SVE2 0x1
+#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56
+#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52
+#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44
+#define ID_AA64ZFR0_EL1_SM4_SHIFT 40
+#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32
+#define ID_AA64ZFR0_EL1_BF16_SHIFT 20
+#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16
+#define ID_AA64ZFR0_EL1_AES_SHIFT 4
+#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0
+
+#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1
+#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1
+#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1
+#define ID_AA64ZFR0_EL1_BF16_IMP 0x1
+#define ID_AA64ZFR0_EL1_SM4_IMP 0x1
+#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1
+#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1
+#define ID_AA64ZFR0_EL1_AES_IMP 0x1
+#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2
+#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1
/* id_aa64smfr0 */
#define ID_AA64SMFR0_EL1_FA64_SHIFT 63
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a6c224539ce4..08288ad17307 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -276,23 +276,23 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2628,16 +2628,16 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
#ifdef CONFIG_ARM64_SVE
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
- HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
+ HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
#endif
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
#ifdef CONFIG_ARM64_BTI
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 13/27] arm64/sysreg: Remove defines for RPRES enumeration
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (11 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
` (13 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
We have defines for the RPRES enumeration in ID_AA64ISAR2 which do not
follow our normal conventions. Since these defines are never used just
remove them. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 899e1e52b2b2..d3112117b7e6 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -744,8 +744,6 @@
#define ID_AA64ISAR2_RPRES_SHIFT 4
#define ID_AA64ISAR2_WFxT_SHIFT 0
-#define ID_AA64ISAR2_RPRES_8BIT 0x0
-#define ID_AA64ISAR2_RPRES_12BIT 0x1
/*
* Value 0x1 has been removed from the architecture, and is
* reserved, but has not yet been removed from the ARM ARM
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (12 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 13/27] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
` (12 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64ISAR1_EL1 to follow the convention. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/asm_pointer_auth.h | 2 +-
arch/arm64/include/asm/sysreg.h | 62 ++++++-------
arch/arm64/kernel/cpufeature.c | 90 +++++++++----------
arch/arm64/kernel/idreg-override.c | 8 +-
.../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 +++---
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 8 +-
arch/arm64/kvm/sys_regs.c | 8 +-
7 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h
index ead62f7dd269..3b192e04a5dd 100644
--- a/arch/arm64/include/asm/asm_pointer_auth.h
+++ b/arch/arm64/include/asm/asm_pointer_auth.h
@@ -59,7 +59,7 @@ alternative_else_nop_endif
.macro __ptrauth_keys_init_cpu tsk, tmp1, tmp2, tmp3
mrs \tmp1, id_aa64isar1_el1
- ubfx \tmp1, \tmp1, #ID_AA64ISAR1_APA_SHIFT, #8
+ ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8
mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1
ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4
orr \tmp1, \tmp1, \tmp2
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d3112117b7e6..ba9053bc33c2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -705,37 +705,37 @@
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
/* id_aa64isar1 */
-#define ID_AA64ISAR1_I8MM_SHIFT 52
-#define ID_AA64ISAR1_DGH_SHIFT 48
-#define ID_AA64ISAR1_BF16_SHIFT 44
-#define ID_AA64ISAR1_SPECRES_SHIFT 40
-#define ID_AA64ISAR1_SB_SHIFT 36
-#define ID_AA64ISAR1_FRINTTS_SHIFT 32
-#define ID_AA64ISAR1_GPI_SHIFT 28
-#define ID_AA64ISAR1_GPA_SHIFT 24
-#define ID_AA64ISAR1_LRCPC_SHIFT 20
-#define ID_AA64ISAR1_FCMA_SHIFT 16
-#define ID_AA64ISAR1_JSCVT_SHIFT 12
-#define ID_AA64ISAR1_API_SHIFT 8
-#define ID_AA64ISAR1_APA_SHIFT 4
-#define ID_AA64ISAR1_DPB_SHIFT 0
-
-#define ID_AA64ISAR1_APA_NI 0x0
-#define ID_AA64ISAR1_APA_PAuth 0x1
-#define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
-#define ID_AA64ISAR1_APA_Pauth2 0x3
-#define ID_AA64ISAR1_APA_FPAC 0x4
-#define ID_AA64ISAR1_APA_FPACCOMBINE 0x5
-#define ID_AA64ISAR1_API_NI 0x0
-#define ID_AA64ISAR1_API_PAuth 0x1
-#define ID_AA64ISAR1_API_EPAC 0x2
-#define ID_AA64ISAR1_API_PAuth2 0x3
-#define ID_AA64ISAR1_API_FPAC 0x4
-#define ID_AA64ISAR1_API_FPACCOMBINE 0x5
-#define ID_AA64ISAR1_GPA_NI 0x0
-#define ID_AA64ISAR1_GPA_IMP 0x1
-#define ID_AA64ISAR1_GPI_NI 0x0
-#define ID_AA64ISAR1_GPI_IMP 0x1
+#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52
+#define ID_AA64ISAR1_EL1_DGH_SHIFT 48
+#define ID_AA64ISAR1_EL1_BF16_SHIFT 44
+#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
+#define ID_AA64ISAR1_EL1_SB_SHIFT 36
+#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
+#define ID_AA64ISAR1_EL1_GPI_SHIFT 28
+#define ID_AA64ISAR1_EL1_GPA_SHIFT 24
+#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
+#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16
+#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12
+#define ID_AA64ISAR1_EL1_API_SHIFT 8
+#define ID_AA64ISAR1_EL1_APA_SHIFT 5
+#define ID_AA64ISAR1_EL1_DPB_SHIFT 0
+
+#define ID_AA64ISAR1_EL1_APA_NI 0x0
+#define ID_AA64ISAR1_EL1_APA_PAuth 0x1
+#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2
+#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3
+#define ID_AA64ISAR1_EL1_APA_FPAC 0x4
+#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5
+#define ID_AA64ISAR1_EL1_API_NI 0x0
+#define ID_AA64ISAR1_EL1_API_PAuth 0x1
+#define ID_AA64ISAR1_EL1_API_EPAC 0x2
+#define ID_AA64ISAR1_EL1_API_PAuth2 0x3
+#define ID_AA64ISAR1_EL1_API_FPAC 0x4
+#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5
+#define ID_AA64ISAR1_EL1_GPA_NI 0x0
+#define ID_AA64ISAR1_EL1_GPA_IMP 0x1
+#define ID_AA64ISAR1_EL1_GPI_NI 0x0
+#define ID_AA64ISAR1_EL1_GPI_IMP 0x1
/* id_aa64isar2 */
#define ID_AA64ISAR2_BC_SHIFT 28
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 08288ad17307..0d4f0120c516 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -209,24 +209,24 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2132,7 +2132,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
- .field_pos = ID_AA64ISAR1_DPB_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
.field_width = 4,
.min_field_value = 1,
},
@@ -2143,7 +2143,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_DPB_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
.field_width = 4,
.min_field_value = 2,
},
@@ -2303,7 +2303,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.matches = has_cpuid_feature,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
- .field_pos = ID_AA64ISAR1_SB_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
.min_field_value = 1,
@@ -2315,9 +2315,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_APA_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_APA_PAuth,
+ .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2337,9 +2337,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_API_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_API_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_API_PAuth,
+ .min_field_value = ID_AA64ISAR1_EL1_API_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2353,9 +2353,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_GPA_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_GPA_IMP,
+ .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2375,9 +2375,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_GPI_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR1_GPI_IMP,
+ .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
+ .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,
.field_width = 4,
.matches = has_cpuid_feature,
.min_field_value = 1,
@@ -2560,33 +2560,33 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
#ifdef CONFIG_ARM64_PTR_AUTH
static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT,
4, FTR_UNSIGNED,
- ID_AA64ISAR1_APA_PAuth)
+ ID_AA64ISAR1_EL1_APA_PAuth)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
},
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth)
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth)
},
{},
};
static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP)
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT,
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
},
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP)
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,
+ 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP)
},
{},
};
@@ -2614,17 +2614,17 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
- HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
+ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
#ifdef CONFIG_ARM64_SVE
HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c
index 8a2ceb591686..652c19b13588 100644
--- a/arch/arm64/kernel/idreg-override.c
+++ b/arch/arm64/kernel/idreg-override.c
@@ -63,10 +63,10 @@ static const struct ftr_set_desc isar1 __initconst = {
.name = "id_aa64isar1",
.override = &id_aa64isar1_override,
.fields = {
- { "gpi", ID_AA64ISAR1_GPI_SHIFT },
- { "gpa", ID_AA64ISAR1_GPA_SHIFT },
- { "api", ID_AA64ISAR1_API_SHIFT },
- { "apa", ID_AA64ISAR1_APA_SHIFT },
+ { "gpi", ID_AA64ISAR1_EL1_GPI_SHIFT },
+ { "gpa", ID_AA64ISAR1_EL1_GPA_SHIFT },
+ { "api", ID_AA64ISAR1_EL1_API_SHIFT },
+ { "apa", ID_AA64ISAR1_EL1_APA_SHIFT },
{}
},
};
diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index fd55014b3497..46cf9dec21ba 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -176,20 +176,20 @@
)
#define PVM_ID_AA64ISAR1_ALLOW (\
- ARM64_FEATURE_MASK(ID_AA64ISAR1_DPB) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_JSCVT) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_FCMA) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_LRCPC) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_FRINTTS) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_SB) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_SPECRES) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_BF16) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_DGH) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR1_I8MM) \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DPB) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_JSCVT) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FCMA) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_LRCPC) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_FRINTTS) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SB) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_SPECRES) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_BF16) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_DGH) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_I8MM) \
)
#define PVM_ID_AA64ISAR2_ALLOW (\
diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index 35a4331ba5f3..5b77bc1cca0c 100644
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -173,10 +173,10 @@ static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW;
if (!vcpu_has_ptrauth(vcpu))
- allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
+ allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
return id_aa64isar1_el1_sys_val & allow_mask;
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f12c6d457677..ccd973dc346a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1136,10 +1136,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
break;
case SYS_ID_AA64ISAR1_EL1:
if (!vcpu_has_ptrauth(vcpu))
- val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
- ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
+ val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
break;
case SYS_ID_AA64ISAR2_EL1:
if (!vcpu_has_ptrauth(vcpu))
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (13 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
` (11 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64ISAR2_EL1 to follow the convention. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/asm_pointer_auth.h | 2 +-
arch/arm64/include/asm/cpufeature.h | 2 +-
arch/arm64/include/asm/sysreg.h | 34 +++++++++----------
arch/arm64/kernel/cpufeature.c | 34 +++++++++----------
arch/arm64/kernel/idreg-override.c | 4 +--
.../arm64/kvm/hyp/include/nvhe/fixed_config.h | 4 +--
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 4 +--
arch/arm64/kvm/sys_regs.c | 6 ++--
8 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/arch/arm64/include/asm/asm_pointer_auth.h b/arch/arm64/include/asm/asm_pointer_auth.h
index 3b192e04a5dd..13ecc79854ee 100644
--- a/arch/arm64/include/asm/asm_pointer_auth.h
+++ b/arch/arm64/include/asm/asm_pointer_auth.h
@@ -61,7 +61,7 @@ alternative_else_nop_endif
mrs \tmp1, id_aa64isar1_el1
ubfx \tmp1, \tmp1, #ID_AA64ISAR1_EL1_APA_SHIFT, #8
mrs_s \tmp2, SYS_ID_AA64ISAR2_EL1
- ubfx \tmp2, \tmp2, #ID_AA64ISAR2_APA3_SHIFT, #4
+ ubfx \tmp2, \tmp2, #ID_AA64ISAR2_EL1_APA3_SHIFT, #4
orr \tmp1, \tmp1, \tmp2
cbz \tmp1, .Lno_addr_auth\@
mov_q \tmp1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 6472f2badc97..fe59035bdc22 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -673,7 +673,7 @@ static inline bool supports_clearbhb(int scope)
isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
return cpuid_feature_extract_unsigned_field(isar2,
- ID_AA64ISAR2_BC_SHIFT);
+ ID_AA64ISAR2_EL1_BC_SHIFT);
}
const struct cpumask *system_32bit_el0_cpumask(void);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ba9053bc33c2..7f083a2ed7dc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -738,29 +738,29 @@
#define ID_AA64ISAR1_EL1_GPI_IMP 0x1
/* id_aa64isar2 */
-#define ID_AA64ISAR2_BC_SHIFT 28
-#define ID_AA64ISAR2_APA3_SHIFT 12
-#define ID_AA64ISAR2_GPA3_SHIFT 8
-#define ID_AA64ISAR2_RPRES_SHIFT 4
-#define ID_AA64ISAR2_WFxT_SHIFT 0
+#define ID_AA64ISAR2_EL1_BC_SHIFT 28
+#define ID_AA64ISAR2_EL1_APA3_SHIFT 12
+#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8
+#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4
+#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0
/*
* Value 0x1 has been removed from the architecture, and is
* reserved, but has not yet been removed from the ARM ARM
* as of ARM DDI 0487G.b.
*/
-#define ID_AA64ISAR2_WFxT_NI 0x0
-#define ID_AA64ISAR2_WFxT_IMP 0x2
-
-#define ID_AA64ISAR2_APA3_NI 0x0
-#define ID_AA64ISAR2_APA3_PAuth 0x1
-#define ID_AA64ISAR2_APA3_EPAC 0x2
-#define ID_AA64ISAR2_APA3_PAuth2 0x3
-#define ID_AA64ISAR2_APA3_FPAC 0x4
-#define ID_AA64ISAR2_APA3_FPACCOMBINE 0x5
-
-#define ID_AA64ISAR2_GPA3_NI 0x0
-#define ID_AA64ISAR2_GPA3_IMP 0x1
+#define ID_AA64ISAR2_EL1_WFxT_NI 0x0
+#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2
+
+#define ID_AA64ISAR2_EL1_APA3_NI 0x0
+#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1
+#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2
+#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3
+#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4
+#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5
+
+#define ID_AA64ISAR2_EL1_GPA3_NI 0x0
+#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0d4f0120c516..be20100a7d4c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -231,13 +231,13 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
- ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_BC_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 4, 0),
+ FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
- FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
- ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0),
+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
ARM64_FTR_END,
};
@@ -2326,9 +2326,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
.sys_reg = SYS_ID_AA64ISAR2_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR2_APA3_SHIFT,
+ .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR2_APA3_PAuth,
+ .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth,
.matches = has_address_auth_cpucap,
},
{
@@ -2364,9 +2364,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR2_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR2_GPA3_SHIFT,
+ .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT,
.field_width = 4,
- .min_field_value = ID_AA64ISAR2_GPA3_IMP,
+ .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64ISAR2_EL1,
.sign = FTR_UNSIGNED,
- .field_pos = ID_AA64ISAR2_WFxT_SHIFT,
+ .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT,
.field_width = 4,
.matches = has_cpuid_feature,
- .min_field_value = ID_AA64ISAR2_WFxT_IMP,
+ .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP,
},
{},
};
@@ -2565,8 +2565,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
ID_AA64ISAR1_EL1_APA_PAuth)
},
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT,
+ 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,
@@ -2581,8 +2581,8 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
},
{
- HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
- 4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
+ HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT,
+ 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP)
},
{
HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,
@@ -2653,8 +2653,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
#endif /* CONFIG_ARM64_MTE */
HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
- HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
- HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
+ HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
+ HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
#ifdef CONFIG_ARM64_SME
HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c
index 652c19b13588..720a847f7dfe 100644
--- a/arch/arm64/kernel/idreg-override.c
+++ b/arch/arm64/kernel/idreg-override.c
@@ -75,8 +75,8 @@ static const struct ftr_set_desc isar2 __initconst = {
.name = "id_aa64isar2",
.override = &id_aa64isar2_override,
.fields = {
- { "gpa3", ID_AA64ISAR2_GPA3_SHIFT },
- { "apa3", ID_AA64ISAR2_APA3_SHIFT },
+ { "gpa3", ID_AA64ISAR2_EL1_GPA3_SHIFT },
+ { "apa3", ID_AA64ISAR2_EL1_APA3_SHIFT },
{}
},
};
diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 46cf9dec21ba..fa6e466ed57f 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -193,8 +193,8 @@
)
#define PVM_ID_AA64ISAR2_ALLOW (\
- ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3) | \
- ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) \
+ ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3) | \
+ ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) \
)
u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index 5b77bc1cca0c..6b94c3e6ff26 100644
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -186,8 +186,8 @@ static u64 get_pvm_id_aa64isar2(const struct kvm_vcpu *vcpu)
u64 allow_mask = PVM_ID_AA64ISAR2_ALLOW;
if (!vcpu_has_ptrauth(vcpu))
- allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
- ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
+ allow_mask &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
return id_aa64isar2_el1_sys_val & allow_mask;
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ccd973dc346a..c4fb3874b5e2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1143,10 +1143,10 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
break;
case SYS_ID_AA64ISAR2_EL1:
if (!vcpu_has_ptrauth(vcpu))
- val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
- ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
+ val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
+ ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
if (!cpus_have_final_cap(ARM64_HAS_WFXT))
- val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT);
+ val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
break;
case SYS_ID_AA64DFR0_EL1:
/* Limit debug to ARMv8.0 */
--
2.30.2
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (14 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 17/27] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
` (10 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 16 ----------------
arch/arm64/tools/sysreg | 21 +++++++++++++++++++++
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7f083a2ed7dc..a57b4a79a8e9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,7 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
@@ -1082,21 +1081,6 @@
#define MVFR2_FPMISC_SHIFT 4
#define MVFR2_SIMDMISC_SHIFT 0
-#define CTR_EL0_L1Ip_VPIPT 0
-#define CTR_EL0_L1Ip_VIPT 2
-#define CTR_EL0_L1Ip_PIPT 3
-
-#define CTR_EL0_L1Ip_SHIFT 14
-#define CTR_EL0_L1Ip_MASK 3
-#define CTR_EL0_DminLine_SHIFT 16
-#define CTR_EL0_IminLine_SHIFT 0
-#define CTR_EL0_IminLine_MASK 0xf
-#define CTR_EL0_ERG_SHIFT 20
-#define CTR_EL0_CWG_SHIFT 24
-#define CTR_EL0_CWG_MASK 15
-#define CTR_EL0_IDC_SHIFT 28
-#define CTR_EL0_DIC_SHIFT 29
-
#define DCZID_EL0_DZP_SHIFT 4
#define DCZID_EL0_BS_SHIFT 0
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ff5e552f7420..a9f4c157c4be 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -273,6 +273,27 @@ Field 3:1 Level
Field 0 InD
EndSysreg
+Sysreg CTR_EL0 3 3 0 0 1
+Res0 63:38
+Field 37:32 TminLine
+Res1 31
+Res0 30
+Field 29 DIC
+Field 28 IDC
+Field 27:24 CWG
+Field 23:20 ERG
+Field 19:16 DminLine
+Enum 15:14 L1Ip
+ 0b00 VPIPT
+ # This is named as AIVIVT in the ARM but documented as reserved
+ 0b01 RESERVED
+ 0b10 VIPT
+ 0b11 PIPT
+EndEnum
+Res0 13:4
+Field 3:0 IminLine
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 17/27] arm64/sysreg: Convert DCZID_EL0 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (15 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 18/27] arm64/sysreg: Convert GMID " Mark Brown
` (9 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no
functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 5 -----
arch/arm64/tools/sysreg | 6 ++++++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a57b4a79a8e9..e71f85b57cdb 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,8 +461,6 @@
#define SMIDR_EL1_SMPS_SHIFT 15
#define SMIDR_EL1_AFFINITY_SHIFT 0
-#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
-
#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
@@ -1081,9 +1079,6 @@
#define MVFR2_FPMISC_SHIFT 4
#define MVFR2_SIMDMISC_SHIFT 0
-#define DCZID_EL0_DZP_SHIFT 4
-#define DCZID_EL0_BS_SHIFT 0
-
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a9f4c157c4be..c286b62958ea 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -294,6 +294,12 @@ Res0 13:4
Field 3:0 IminLine
EndSysreg
+Sysreg DCZID_EL0 3 3 0 0 7
+Res0 63:5
+Field 4 DZP
+Field 3:0 BS
+EndSysreg
+
Sysreg SVCR 3 3 4 2 2
Res0 63:2
Field 1 ZA
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 18/27] arm64/sysreg: Convert GMID to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (16 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 17/27] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
` (8 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Automatically generate the register definitions for GMID as per DDI0487H.a,
no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 5 +++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e71f85b57cdb..a7ebfa17893a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -454,7 +454,6 @@
#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
-#define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
#define SMIDR_EL1_IMPLEMENTER_SHIFT 24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c286b62958ea..ea3520a347b1 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -257,6 +257,11 @@ Field 5:3 Ctype2
Field 2:0 Ctype1
EndSysreg
+Sysreg GMID_EL1 3 1 0 0 4
+Res0 63:4
+Field 3:0 BS
+EndSysreg
+
Sysreg SMIDR_EL1 3 1 0 0 6
Res0 63:32
Field 31:24 IMPLEMENTER
--
2.30.2
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (17 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 18/27] arm64/sysreg: Convert GMID " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
` (7 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Automatically generate defines for ID_AA64ISAR1_EL1, using the definitions
in DDI0487H.a. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 34 --------------
arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+), 34 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a7ebfa17893a..089e2da3a5a9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -201,7 +201,6 @@
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
-#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
@@ -700,39 +699,6 @@
/* Position the attr at the correct index */
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
-/* id_aa64isar1 */
-#define ID_AA64ISAR1_EL1_I8MM_SHIFT 52
-#define ID_AA64ISAR1_EL1_DGH_SHIFT 48
-#define ID_AA64ISAR1_EL1_BF16_SHIFT 44
-#define ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
-#define ID_AA64ISAR1_EL1_SB_SHIFT 36
-#define ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
-#define ID_AA64ISAR1_EL1_GPI_SHIFT 28
-#define ID_AA64ISAR1_EL1_GPA_SHIFT 24
-#define ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
-#define ID_AA64ISAR1_EL1_FCMA_SHIFT 16
-#define ID_AA64ISAR1_EL1_JSCVT_SHIFT 12
-#define ID_AA64ISAR1_EL1_API_SHIFT 8
-#define ID_AA64ISAR1_EL1_APA_SHIFT 5
-#define ID_AA64ISAR1_EL1_DPB_SHIFT 0
-
-#define ID_AA64ISAR1_EL1_APA_NI 0x0
-#define ID_AA64ISAR1_EL1_APA_PAuth 0x1
-#define ID_AA64ISAR1_EL1_APA_ARCH_EPAC 0x2
-#define ID_AA64ISAR1_EL1_APA_Pauth2 0x3
-#define ID_AA64ISAR1_EL1_APA_FPAC 0x4
-#define ID_AA64ISAR1_EL1_APA_FPACCOMBINE 0x5
-#define ID_AA64ISAR1_EL1_API_NI 0x0
-#define ID_AA64ISAR1_EL1_API_PAuth 0x1
-#define ID_AA64ISAR1_EL1_API_EPAC 0x2
-#define ID_AA64ISAR1_EL1_API_PAuth2 0x3
-#define ID_AA64ISAR1_EL1_API_FPAC 0x4
-#define ID_AA64ISAR1_EL1_API_FPACCOMBINE 0x5
-#define ID_AA64ISAR1_EL1_GPA_NI 0x0
-#define ID_AA64ISAR1_EL1_GPA_IMP 0x1
-#define ID_AA64ISAR1_EL1_GPI_NI 0x0
-#define ID_AA64ISAR1_EL1_GPI_IMP 0x1
-
/* id_aa64isar2 */
#define ID_AA64ISAR2_EL1_BC_SHIFT 28
#define ID_AA64ISAR2_EL1_APA3_SHIFT 12
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ea3520a347b1..164221177079 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -114,6 +114,89 @@ EndEnum
Res0 3:0
EndSysreg
+Sysreg ID_AA64ISAR1_EL1 3 0 0 6 1
+Enum 63:60 LS64
+ 0b0000 NI
+ 0b0001 LS64
+ 0b0010 LS64_V
+ 0b0011 LS64_ACCDATA
+EndEnum
+Enum 59:56 XS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 55:52 I8MM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 51:48 DGH
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 47:44 BF16
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 EBF16
+EndEnum
+Enum 43:40 SPECRES
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 39:36 SB
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 35:32 FRINTTS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 31:28 GPI
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 27:24 GPA
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 LRCPC
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 LRCPC2
+EndEnum
+Enum 19:16 FCMA
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 JSCVT
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 11:8 API
+ 0b0000 NI
+ 0b0001 PAuth
+ 0b0010 EPAC
+ 0b0011 PAuth2
+ 0b0100 FPAC
+ 0b0101 FPACCOMBINE
+EndEnum
+Enum 7:4 APA
+ 0b0000 NI
+ 0b0001 PAuth
+ 0b0010 EPAC
+ 0b0011 PAuth2
+ 0b0100 FPAC
+ 0b0101 FPACCOMBINE
+EndEnum
+Enum 3:0 DPB
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 DPB2
+EndEnum
+EndSysreg
+ 0b0001 IMP
+EndEnum
+EndSysreg
+
Sysreg SCTLR_EL1 3 0 1 0 0
Field 63 TIDCP
Field 62 SPINMASK
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (18 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 21/27] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
` (6 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Automatically generate defines for ID_AA64ISAR2_EL1, using the definitions
in DDI0487H.a. No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 27 ---------------------------
arch/arm64/tools/sysreg | 33 +++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 089e2da3a5a9..a8d882b8e2a2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -201,8 +201,6 @@
#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
-#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
-
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
@@ -699,31 +697,6 @@
/* Position the attr at the correct index */
#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
-/* id_aa64isar2 */
-#define ID_AA64ISAR2_EL1_BC_SHIFT 28
-#define ID_AA64ISAR2_EL1_APA3_SHIFT 12
-#define ID_AA64ISAR2_EL1_GPA3_SHIFT 8
-#define ID_AA64ISAR2_EL1_RPRES_SHIFT 4
-#define ID_AA64ISAR2_EL1_WFxT_SHIFT 0
-
-/*
- * Value 0x1 has been removed from the architecture, and is
- * reserved, but has not yet been removed from the ARM ARM
- * as of ARM DDI 0487G.b.
- */
-#define ID_AA64ISAR2_EL1_WFxT_NI 0x0
-#define ID_AA64ISAR2_EL1_WFxT_IMP 0x2
-
-#define ID_AA64ISAR2_EL1_APA3_NI 0x0
-#define ID_AA64ISAR2_EL1_APA3_PAuth 0x1
-#define ID_AA64ISAR2_EL1_APA3_EPAC 0x2
-#define ID_AA64ISAR2_EL1_APA3_PAuth2 0x3
-#define ID_AA64ISAR2_EL1_APA3_FPAC 0x4
-#define ID_AA64ISAR2_EL1_APA3_FPACCOMBINE 0x5
-
-#define ID_AA64ISAR2_EL1_GPA3_NI 0x0
-#define ID_AA64ISAR2_EL1_GPA3_IMP 0x1
-
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 164221177079..da5e925bf624 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -193,8 +193,41 @@ Enum 3:0 DPB
0b0010 DPB2
EndEnum
EndSysreg
+
+Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2
+Res0 63:28
+Enum 27:24 PAC_frac
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 23:20 BC
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 19:16 MOPS
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 15:12 APA3
+ 0b0000 NI
+ 0b0001 PAuth
+ 0b0010 EPAC
+ 0b0011 PAuth2
+ 0b0100 FPAC
+ 0b0101 FPACCOMBINE
+EndEnum
+Enum 11:8 GPA3
+ 0b0000 NI
0b0001 IMP
EndEnum
+Enum 7:4 RPRES
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 3:0 WFxT
+ 0b0000 NI
+ 0b0010 IMP
+EndEnum
EndSysreg
Sysreg SCTLR_EL1 3 0 1 0 0
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 21/27] arm64/sysreg: Convert LORSA_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (19 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 22/27] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
` (5 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert LORSA_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 8 ++++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a8d882b8e2a2..050e9bfb2250 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,7 +407,6 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
-#define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index da5e925bf624..c1e3a9ceb049 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -515,3 +515,11 @@ EndSysreg
Sysreg TTBR1_EL1 3 0 2 0 1
Fields TTBRx_EL1
EndSysreg
+
+Sysreg LORSA_EL1 3 0 10 4 0
+Res0 63:52
+Field 51:16 SA
+Res0 15:1
+Field 0 Valid
+EndSysreg
+
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 22/27] arm64/sysreg: Convert LOREA_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (20 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 21/27] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 23/27] arm64/sysreg: Convert LORN_EL1 " Mark Brown
` (4 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert LOREA_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 6 ++++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 050e9bfb2250..19d29b02b6b7 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,7 +407,6 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
-#define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c1e3a9ceb049..4c23c65e53d1 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -523,3 +523,9 @@ Res0 15:1
Field 0 Valid
EndSysreg
+Sysreg LOREA_EL1 3 0 10 4 1
+Res0 63:52
+Field 51:48 EA_51_48
+Field 47:16 EA_47_16
+Res0 15:0
+EndSysreg
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 23/27] arm64/sysreg: Convert LORN_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (21 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 22/27] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 24/27] arm64/sysreg: Convert LORC_EL1 " Mark Brown
` (3 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert LORN_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 5 +++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 19d29b02b6b7..2d844cdbe52c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,7 +407,6 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
-#define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c23c65e53d1..ec84a76fe66e 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -529,3 +529,8 @@ Field 51:48 EA_51_48
Field 47:16 EA_47_16
Res0 15:0
EndSysreg
+
+Sysreg LORN_EL1 3 0 10 4 2
+Res0 63:8
+Field 7:0 Num
+EndSysreg
--
2.30.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 24/27] arm64/sysreg: Convert LORC_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (22 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 23/27] arm64/sysreg: Convert LORN_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 25/27] arm64/sysreg: Convert LORID_EL1 " Mark Brown
` (2 subsequent siblings)
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert LORC_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 7 +++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2d844cdbe52c..4b393913be40 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,7 +407,6 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
-#define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ec84a76fe66e..95fcad79b917 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -534,3 +534,10 @@ Sysreg LORN_EL1 3 0 10 4 2
Res0 63:8
Field 7:0 Num
EndSysreg
+
+Sysreg LORC_EL1 3 0 10 4 3
+Res0 63:10
+Field 9:2 DS
+Res0 1
+Field 0 EN
+EndSysreg
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 25/27] arm64/sysreg: Convert LORID_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (23 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 24/27] arm64/sysreg: Convert LORC_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-06-22 17:44 ` [PATCH v5 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert LORID_EL1 to automatic register generation as per DDI0487H.a, no
functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 2 --
arch/arm64/tools/sysreg | 7 +++++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4b393913be40..6be54e9bdfaf 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -407,8 +407,6 @@
#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
-#define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
-
#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 95fcad79b917..13b8f85682af 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -541,3 +541,10 @@ Field 9:2 DS
Res0 1
Field 0 EN
EndSysreg
+
+Sysreg LORID_EL1 3 0 10 4 7
+Res0 63:24
+Field 23:16 LD
+Res0 15:8
+Field 7:0 LR
+EndSysreg
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (24 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 25/27] arm64/sysreg: Convert LORID_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
2022-06-22 17:44 ` [PATCH v5 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 18 ----------------
arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6be54e9bdfaf..6496550ec0c0 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -193,7 +193,6 @@
#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
-#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5)
#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
@@ -760,23 +759,6 @@
#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2
#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1
-/* id_aa64smfr0 */
-#define ID_AA64SMFR0_EL1_FA64_SHIFT 63
-#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52
-#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48
-#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36
-#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35
-#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34
-#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32
-
-#define ID_AA64SMFR0_EL1_FA64_IMP 0x1
-#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf
-#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1
-#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf
-#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1
-#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1
-#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1
-
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_ECV_SHIFT 60
#define ID_AA64MMFR0_FGT_SHIFT 56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 13b8f85682af..b5c4251c6796 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,43 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
+Enum 63 FA64
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 62:60
+Field 59:56 SMEver
+Enum 55:52 I16I64
+ 0b0000 NI
+ 0b1111 IMP
+EndEnum
+Res0 51:49
+Enum 48 F64F64
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 47:40
+Enum 39:36 I8I32
+ 0b0000 NI
+ 0b1111 IMP
+EndEnum
+Enum 35 F16F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Enum 34 B16F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 33
+Enum 32 F32F32
+ 0b0 NI
+ 0b1 IMP
+EndEnum
+Res0 31:0
+EndSysreg
+
Sysreg ID_AA64ISAR0_EL1 3 0 0 6 0
Enum 63:60 RNDR
0b0000 NI
--
2.30.2
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v5 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
2022-06-22 17:43 [PATCH v5 00/27] arm64/sysreg: More system register generation Mark Brown
` (25 preceding siblings ...)
2022-06-22 17:44 ` [PATCH v5 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
@ 2022-06-22 17:44 ` Mark Brown
26 siblings, 0 replies; 29+ messages in thread
From: Mark Brown @ 2022-06-22 17:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Mark Rutland, Joey Gouly, linux-arm-kernel, Mark Brown
Convert ID_AA64ZFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 23 -----------------
arch/arm64/tools/sysreg | 46 +++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6496550ec0c0..b7503b9782d0 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -192,7 +192,6 @@
#define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
-#define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
@@ -737,28 +736,6 @@
#define ID_AA64PFR1_MTE 0x2
#define ID_AA64PFR1_MTE_ASYMM 0x3
-/* id_aa64zfr0 */
-#define ID_AA64ZFR0_EL1_F64MM_SHIFT 56
-#define ID_AA64ZFR0_EL1_F32MM_SHIFT 52
-#define ID_AA64ZFR0_EL1_I8MM_SHIFT 44
-#define ID_AA64ZFR0_EL1_SM4_SHIFT 40
-#define ID_AA64ZFR0_EL1_SHA3_SHIFT 32
-#define ID_AA64ZFR0_EL1_BF16_SHIFT 20
-#define ID_AA64ZFR0_EL1_BitPerm_SHIFT 16
-#define ID_AA64ZFR0_EL1_AES_SHIFT 4
-#define ID_AA64ZFR0_EL1_SVEver_SHIFT 0
-
-#define ID_AA64ZFR0_EL1_F64MM_IMP 0x1
-#define ID_AA64ZFR0_EL1_F32MM_IMP 0x1
-#define ID_AA64ZFR0_EL1_I8MM_IMP 0x1
-#define ID_AA64ZFR0_EL1_BF16_IMP 0x1
-#define ID_AA64ZFR0_EL1_SM4_IMP 0x1
-#define ID_AA64ZFR0_EL1_SHA3_IMP 0x1
-#define ID_AA64ZFR0_EL1_BitPerm_IMP 0x1
-#define ID_AA64ZFR0_EL1_AES_IMP 0x1
-#define ID_AA64ZFR0_EL1_AES_PMULL128 0x2
-#define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1
-
/* id_aa64mmfr0 */
#define ID_AA64MMFR0_ECV_SHIFT 60
#define ID_AA64MMFR0_FGT_SHIFT 56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b5c4251c6796..9ae483ec1e56 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,52 @@
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
# item ACCDATA) though it may be more taseful to do something else.
+Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4
+Res0 63:60
+Enum 59:56 F64MM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 55:52 F32MM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 51:48
+Enum 47:44 I8MM
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Enum 43:40 SM4
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 39:36
+Enum 35:32 SHA3
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 31:24
+Enum 23:20 BF16
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 EBF16
+EndEnum
+Enum 19:16 BitPerm
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+Res0 15:8
+Enum 7:4 AES
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 PMULL128
+EndEnum
+Enum 3:0 SVEver
+ 0b0000 IMP
+ 0b0001 SVE2
+EndEnum
+EndSysreg
+
Sysreg ID_AA64SMFR0_EL1 3 0 0 4 5
Enum 63 FA64
0b0 NI
--
2.30.2
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