* [PATCH v7 1/4] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux
2023-07-28 5:08 [PATCH v7 0/4] Add peripherals for J784S4 Jayesh Choudhary
@ 2023-07-28 5:08 ` Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 2/4] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Jayesh Choudhary
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jayesh Choudhary @ 2023-07-28 5:08 UTC (permalink / raw)
To: nm, vigneshr, s-vadapalli, afd
Cc: kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, rogerq,
a-bhatia1, r-ravikumar, devicetree, linux-kernel,
linux-arm-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: Fix serdes_ln_ctrl node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 11f163e5cadf..8a816563706b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,10 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+
+#include "k3-serdes.h"
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +30,42 @@ l3cache-sram@200000 {
};
};
+ scm_conf: bus@100000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ reg = <0x00004080 0x30>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
+ <J784S4_SERDES0_LANE2_IP3_UNUSED>,
+ <J784S4_SERDES0_LANE3_USB>,
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>,
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
+ <J784S4_SERDES1_LANE2_PCIE0_LANE2>,
+ <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
+ <J784S4_SERDES2_LANE0_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE1_IP2_UNUSED>,
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,
+ <J784S4_SERDES2_LANE3_QSGMII_LANE2>,
+ <J784S4_SERDES4_LANE0_EDP_LANE0>,
+ <J784S4_SERDES4_LANE1_EDP_LANE1>,
+ <J784S4_SERDES4_LANE2_EDP_LANE2>,
+ <J784S4_SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v7 2/4] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes
2023-07-28 5:08 [PATCH v7 0/4] Add peripherals for J784S4 Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 1/4] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
@ 2023-07-28 5:08 ` Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 3/4] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jayesh Choudhary @ 2023-07-28 5:08 UTC (permalink / raw)
To: nm, vigneshr, s-vadapalli, afd
Cc: kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, rogerq,
a-bhatia1, r-ravikumar, devicetree, linux-kernel,
linux-arm-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
J784S4 SoC has 4 Serdes instances along with their respective WIZ
instances. Add device-tree nodes for them and disable them by default.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++
1 file changed, 172 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 8a816563706b..fbf5ab94d785 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -6,9 +6,19 @@
*/
#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
#include "k3-serdes.h"
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ status = "disabled";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 404 6>;
+ assigned-clock-parents = <&k3_clks 404 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x00 0x5060000 0x10000>;
+
+ status = "disabled";
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 404 6>,
+ <&k3_clks 404 6>,
+ <&k3_clks 404 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz1: wiz@5070000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 405 6>;
+ assigned-clock-parents = <&k3_clks 405 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05070000 0x00 0x05070000 0x10000>;
+
+ status = "disabled";
+
+ serdes1: serdes@5070000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05070000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 405 6>,
+ <&k3_clks 405 6>,
+ <&k3_clks 405 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 406 6>;
+ assigned-clock-parents = <&k3_clks 406 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05020000 0x00 0x05020000 0x10000>;
+
+ status = "disabled";
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05020000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz2 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 406 6>,
+ <&k3_clks 406 6>,
+ <&k3_clks 406 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
+ assigned-clocks = <&k3_clks 407 6>;
+ assigned-clock-parents = <&k3_clks 407 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05050000 0x00 0x05050000 0x10000>,
+ <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+
+ status = "disabled";
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05050000 0x010000>,
+ <0x0a030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 407 6>,
+ <&k3_clks 407 6>,
+ <&k3_clks 407 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
main_navss: bus@30000000 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.25.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v7 3/4] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
2023-07-28 5:08 [PATCH v7 0/4] Add peripherals for J784S4 Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 1/4] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 2/4] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Jayesh Choudhary
@ 2023-07-28 5:08 ` Jayesh Choudhary
2023-07-28 5:08 ` [PATCH v7 4/4] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
2023-07-28 21:12 ` [PATCH v7 0/4] Add peripherals for J784S4 Nishanth Menon
4 siblings, 0 replies; 7+ messages in thread
From: Jayesh Choudhary @ 2023-07-28 5:08 UTC (permalink / raw)
To: nm, vigneshr, s-vadapalli, afd
Cc: kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, rogerq,
a-bhatia1, r-ravikumar, devicetree, linux-kernel,
linux-arm-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
same as DSS IP in J721E, so same compatible is being used.
The DP is Cadence MHDP8546.
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index fbf5ab94d785..975661948755 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1749,4 +1749,77 @@ c71_3: dsp@67800000 {
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
};
+
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 217 11>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+ status = "disabled";
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
+ <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
+ <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
+ <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
+ <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
+ <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
+ <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
+ <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
+ <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
+ <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
+ <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
+ <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
+ <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */
+ <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
+ <0x00 0x04af0000 0x00 0x10000>; /* wb */
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v7 4/4] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
2023-07-28 5:08 [PATCH v7 0/4] Add peripherals for J784S4 Jayesh Choudhary
` (2 preceding siblings ...)
2023-07-28 5:08 ` [PATCH v7 3/4] arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node Jayesh Choudhary
@ 2023-07-28 5:08 ` Jayesh Choudhary
2023-07-28 21:12 ` [PATCH v7 0/4] Add peripherals for J784S4 Nishanth Menon
4 siblings, 0 replies; 7+ messages in thread
From: Jayesh Choudhary @ 2023-07-28 5:08 UTC (permalink / raw)
To: nm, vigneshr, s-vadapalli, afd
Cc: kristo, robh+dt, krzysztof.kozlowski+dt, conor+dt, rogerq,
a-bhatia1, r-ravikumar, devicetree, linux-kernel,
linux-arm-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Enable display for J784S4 EVM.
Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for
DP HPD. Add the clock frequency for serdes_refclk.
Add the endpoint nodes to describe connection from:
DSS => MHDP => DisplayPort connector.
Also add the GPIO expander-4 node and pinmux for main_i2c4 which is
required for controlling DP power. Set status for all required nodes
for DP-0 as "okay".
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
[j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 117 +++++++++++++++++++++++
1 file changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 7ad152a1b90f..1145a7f046e2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator-dp0-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ dp0: dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -286,6 +308,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+ >;
+ };
};
&wkup_pmx2 {
@@ -827,3 +862,85 @@ adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
+
+&serdes_refclk {
+ status = "okay";
+ clock-frequency = <100000000>;
+};
+
+&dss {
+ status = "okay";
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v7 0/4] Add peripherals for J784S4
2023-07-28 5:08 [PATCH v7 0/4] Add peripherals for J784S4 Jayesh Choudhary
` (3 preceding siblings ...)
2023-07-28 5:08 ` [PATCH v7 4/4] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Jayesh Choudhary
@ 2023-07-28 21:12 ` Nishanth Menon
2023-07-31 11:04 ` Jayesh Choudhary
4 siblings, 1 reply; 7+ messages in thread
From: Nishanth Menon @ 2023-07-28 21:12 UTC (permalink / raw)
To: Jayesh Choudhary
Cc: vigneshr, s-vadapalli, afd, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, rogerq, a-bhatia1, r-ravikumar,
devicetree, linux-kernel, linux-arm-kernel
On 10:38-20230728, Jayesh Choudhary wrote:
> This series adds support for:
> - SERDES, WIZ DT nodes, Serdes lane control mux
> - DSS and DisplayPort-0 nodes
>
> This support DEPENDS upon another series which was introduced as part
> of discussion in v5. That series[1] moves the ti-serdes headers file
> from bindings to "arch/arm64/boot/dts/ti". (That series is merged in
> linux-next tree)
>
> Changelog v6->v7:
> - change compatible for scm_conf to 'simple-bus'
> - drop main_cpsw node due to driver dependency on [2]
>
> Changelog v5->v6:
> - Change header file according to [1].
> - Add idle-state property in serdes_ln_ctrl node.
> - Fix dtbs_check warning due to clock-frequency property in serdes_refclk
> node by disabling the node in main.dtsi and enabling it in board file
> when the clock-frequency node is actually added.
>
> Changelog v4->v5:
> - rebased the patches on linux-next tip.
>
> Changelog v3->v4:
> - add reg property to serdes_ln_ctrl and fix the node name again to
> get rid of dtbs_check error.
> - reorder reg, reg-names and ranges property for main_cpsw1.
> - correct the order for clocks in serdes_wiz nodes to fix dtbs_check
> warnings.
> - fix indentation in reg, reg-names and clock property for dss node.
> - add comments for the reg type in dss registers.
>
> Changelog v3->v2:
> - fix dtc warnings for 'scm_conf' and 'serdes_ln_ctrl' nodes
> (Checked all the changes of the series with W=12 option during build)
> - added clock-frequency for serdes_refclk along with other EVM changes
> This refclk is being used by all the instances of serdes_wiz which
> are disabled by default. So configuring refclk when the serdes nodes
> are used for the first time is okay.
>
> Changelog v1->v2:
> - Moved J784S4 EVM changes together to the last patch
> (Suggested by Andrew)
>
> v5 patch link:
> <https://lore.kernel.org/all/20230721132029.123881-1-j-choudhary@ti.com/>
>
> [1]: <https://lore.kernel.org/all/20230721125732.122421-1-j-choudhary@ti.com/>
> [2]: <https://lore.kernel.org/all/20230605154153.24025-1-afd@ti.com/>
>
> Rahul T R (2):
> arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
> arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
>
Could you enable AM69-SK as well? is there anything stopping it being part of the series?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v7 0/4] Add peripherals for J784S4
2023-07-28 21:12 ` [PATCH v7 0/4] Add peripherals for J784S4 Nishanth Menon
@ 2023-07-31 11:04 ` Jayesh Choudhary
0 siblings, 0 replies; 7+ messages in thread
From: Jayesh Choudhary @ 2023-07-31 11:04 UTC (permalink / raw)
To: Nishanth Menon
Cc: vigneshr, s-vadapalli, afd, kristo, robh+dt,
krzysztof.kozlowski+dt, conor+dt, rogerq, a-bhatia1, r-ravikumar,
devicetree, linux-kernel, linux-arm-kernel
Hello Nishanth,
On 29/07/23 02:42, Nishanth Menon wrote:
> On 10:38-20230728, Jayesh Choudhary wrote:
>> This series adds support for:
>> - SERDES, WIZ DT nodes, Serdes lane control mux
>> - DSS and DisplayPort-0 nodes
>>
>> This support DEPENDS upon another series which was introduced as part
>> of discussion in v5. That series[1] moves the ti-serdes headers file
>> from bindings to "arch/arm64/boot/dts/ti". (That series is merged in
>> linux-next tree)
>>
>> Changelog v6->v7:
>> - change compatible for scm_conf to 'simple-bus'
>> - drop main_cpsw node due to driver dependency on [2]
>>
[...]
>>
>> v5 patch link:
>> <https://lore.kernel.org/all/20230721132029.123881-1-j-choudhary@ti.com/>
>>
>> [1]: <https://lore.kernel.org/all/20230721125732.122421-1-j-choudhary@ti.com/>
>> [2]: <https://lore.kernel.org/all/20230605154153.24025-1-afd@ti.com/>
>>
>> Rahul T R (2):
>> arm64: dts: ti: k3-j784s4-main: Add DSS and DP-bridge node
>> arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0
>>
>
> Could you enable AM69-SK as well? is there anything stopping it being part of the series?
>
Okay I will add support for AM69-SK too.
Thanks,
-Jayesh
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^ permalink raw reply [flat|nested] 7+ messages in thread