* [PATCH v1 0/2] HWCAP for FEAT_HBC @ 2023-08-01 10:00 Joey Gouly 2023-08-01 10:00 ` [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) Joey Gouly 2023-08-01 10:00 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test Joey Gouly 0 siblings, 2 replies; 8+ messages in thread From: Joey Gouly @ 2023-08-01 10:00 UTC (permalink / raw) To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will Hi, Small series for adding a HWCAP for FEAT_HBC (hinted conditional branches). Thanks, Joey Joey Gouly (2): arm64: add HWCAP for FEAT_HBC (hinted conditional branches) selftests/arm64: add HWCAP2_HBC test arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kernel/cpuinfo.c | 1 + tools/testing/selftests/arm64/abi/hwcap.c | 15 +++++++++++++++ 5 files changed, 20 insertions(+), 1 deletion(-) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) 2023-08-01 10:00 [PATCH v1 0/2] HWCAP for FEAT_HBC Joey Gouly @ 2023-08-01 10:00 ` Joey Gouly 2023-08-01 15:12 ` Will Deacon 2023-08-01 10:00 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test Joey Gouly 1 sibling, 1 reply; 8+ messages in thread From: Joey Gouly @ 2023-08-01 10:00 UTC (permalink / raw) To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using this feature. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 3 ++- arch/arm64/kernel/cpuinfo.c | 1 + 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 692b1ec663b2..521267478d18 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -138,6 +138,7 @@ #define KERNEL_HWCAP_SME_B16B16 __khwcap2_feature(SME_B16B16) #define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) #define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS) +#define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index a2cac4305b1e..53026f45a509 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -103,5 +103,6 @@ #define HWCAP2_SME_B16B16 (1UL << 41) #define HWCAP2_SME_F16F16 (1UL << 42) #define HWCAP2_MOPS (1UL << 43) +#define HWCAP2_HBC (1UL << 44) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f9d456fe132d..ac764c1dac36 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), + HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), #ifdef CONFIG_ARM64_SME HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 58622dc85917..98fda8500535 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", [KERNEL_HWCAP_SME_F16F16] = "smef16f16", [KERNEL_HWCAP_MOPS] = "mops", + [KERNEL_HWCAP_HBC] = "hbc", }; #ifdef CONFIG_COMPAT -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) 2023-08-01 10:00 ` [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) Joey Gouly @ 2023-08-01 15:12 ` Will Deacon 2023-08-02 11:54 ` Joey Gouly 0 siblings, 1 reply; 8+ messages in thread From: Will Deacon @ 2023-08-01 15:12 UTC (permalink / raw) To: Joey Gouly; +Cc: linux-arm-kernel, nd, catalin.marinas Hey Joey, On Tue, Aug 01, 2023 at 11:00:07AM +0100, Joey Gouly wrote: > Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using > this feature. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> [...] > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index f9d456fe132d..ac764c1dac36 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { > static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), > FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), > @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), > HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), > HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), > + HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), > #ifdef CONFIG_ARM64_SME > HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), > HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 58622dc85917..98fda8500535 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = { > [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", > [KERNEL_HWCAP_SME_F16F16] = "smef16f16", > [KERNEL_HWCAP_MOPS] = "mops", > + [KERNEL_HWCAP_HBC] = "hbc", I'm a bit confused from the Arm ARM as to the use of "hbc" vs "bc"... I don't really mind what we go for, but given this is userspace-visible, have you run the string past the toolchain folks at all? I guess I'm wary of what a future extension might look like and whether we'll be stuck with non-architectural terminology such as "hbc2" to advertise it if we go with your suggestion here rather than "bc". Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) 2023-08-01 15:12 ` Will Deacon @ 2023-08-02 11:54 ` Joey Gouly 2023-08-04 13:19 ` Will Deacon 0 siblings, 1 reply; 8+ messages in thread From: Joey Gouly @ 2023-08-02 11:54 UTC (permalink / raw) To: Will Deacon; +Cc: linux-arm-kernel, nd, catalin.marinas On Tue, Aug 01, 2023 at 04:12:30PM +0100, Will Deacon wrote: > Hey Joey, > > On Tue, Aug 01, 2023 at 11:00:07AM +0100, Joey Gouly wrote: > > Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using > > this feature. > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > [...] > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index f9d456fe132d..ac764c1dac36 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { > > static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), > > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), > > ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), > > FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), > > @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > > HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), > > HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), > > HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), > > + HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), > > #ifdef CONFIG_ARM64_SME > > HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), > > HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > > index 58622dc85917..98fda8500535 100644 > > --- a/arch/arm64/kernel/cpuinfo.c > > +++ b/arch/arm64/kernel/cpuinfo.c > > @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = { > > [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", > > [KERNEL_HWCAP_SME_F16F16] = "smef16f16", > > [KERNEL_HWCAP_MOPS] = "mops", > > + [KERNEL_HWCAP_HBC] = "hbc", > > I'm a bit confused from the Arm ARM as to the use of "hbc" vs "bc"... I > don't really mind what we go for, but given this is userspace-visible, have > you run the string past the toolchain folks at all? I guess I'm wary of > what a future extension might look like and whether we'll be stuck with > non-architectural terminology such as "hbc2" to advertise it if we go with > your suggestion here rather than "bc". I just checked LLVM and binutils, they also call it 'hbc'. .arch armv8.7-a+hbc https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/testsuite/gas/aarch64/hbc.s;h=23af6ba8edd662463ae3403e62d94ef838f87fd1;hb=HEAD#l35 https://github.com/llvm/llvm-project/blob/b31be75ff4d1aed94914d5ef53a903d034d5b6ad/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp#L3600 So it seems that's the name that has been settled on? If you're fine with that, I will send a v2 fixing up the inline asm. Thanks, Joey _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) 2023-08-02 11:54 ` Joey Gouly @ 2023-08-04 13:19 ` Will Deacon 0 siblings, 0 replies; 8+ messages in thread From: Will Deacon @ 2023-08-04 13:19 UTC (permalink / raw) To: Joey Gouly; +Cc: linux-arm-kernel, nd, catalin.marinas On Wed, Aug 02, 2023 at 12:54:01PM +0100, Joey Gouly wrote: > On Tue, Aug 01, 2023 at 04:12:30PM +0100, Will Deacon wrote: > > Hey Joey, > > > > On Tue, Aug 01, 2023 at 11:00:07AM +0100, Joey Gouly wrote: > > > Add a HWCAP for FEAT_HBC, so that userspace can make a decision on using > > > this feature. > > > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > > [...] > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > index f9d456fe132d..ac764c1dac36 100644 > > > --- a/arch/arm64/kernel/cpufeature.c > > > +++ b/arch/arm64/kernel/cpufeature.c > > > @@ -222,7 +222,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { > > > static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), > > > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), > > > FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), > > > @@ -2844,6 +2844,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > > > HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), > > > HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), > > > HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), > > > + HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), > > > #ifdef CONFIG_ARM64_SME > > > HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), > > > HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), > > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > > > index 58622dc85917..98fda8500535 100644 > > > --- a/arch/arm64/kernel/cpuinfo.c > > > +++ b/arch/arm64/kernel/cpuinfo.c > > > @@ -126,6 +126,7 @@ static const char *const hwcap_str[] = { > > > [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", > > > [KERNEL_HWCAP_SME_F16F16] = "smef16f16", > > > [KERNEL_HWCAP_MOPS] = "mops", > > > + [KERNEL_HWCAP_HBC] = "hbc", > > > > I'm a bit confused from the Arm ARM as to the use of "hbc" vs "bc"... I > > don't really mind what we go for, but given this is userspace-visible, have > > you run the string past the toolchain folks at all? I guess I'm wary of > > what a future extension might look like and whether we'll be stuck with > > non-architectural terminology such as "hbc2" to advertise it if we go with > > your suggestion here rather than "bc". > > I just checked LLVM and binutils, they also call it 'hbc'. > > .arch armv8.7-a+hbc > > https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/testsuite/gas/aarch64/hbc.s;h=23af6ba8edd662463ae3403e62d94ef838f87fd1;hb=HEAD#l35 > > https://github.com/llvm/llvm-project/blob/b31be75ff4d1aed94914d5ef53a903d034d5b6ad/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp#L3600 > > So it seems that's the name that has been settled on? If you're fine with > that, I will send a v2 fixing up the inline asm. Thanks for checking. If that's what they've gone for, then so be it! Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test 2023-08-01 10:00 [PATCH v1 0/2] HWCAP for FEAT_HBC Joey Gouly 2023-08-01 10:00 ` [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) Joey Gouly @ 2023-08-01 10:00 ` Joey Gouly 2023-08-01 15:09 ` Will Deacon 1 sibling, 1 reply; 8+ messages in thread From: Joey Gouly @ 2023-08-01 10:00 UTC (permalink / raw) To: linux-arm-kernel; +Cc: nd, catalin.marinas, joey.gouly, will Add a test for the newly added HWCAP2_HBC. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- tools/testing/selftests/arm64/abi/hwcap.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index d4ad813fed10..296102cd9192 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -208,6 +208,13 @@ static void svebf16_sigill(void) asm volatile(".inst 0x658aa000" : : : "z0"); } +static void hbc_sigill(void) +{ + /* BC.EQ +4 */ + asm volatile("cmp xzr, xzr\n" + ".inst 0x54000030" : : :); +} + static const struct hwcap_data { const char *name; unsigned long at_hwcap; @@ -386,6 +393,14 @@ static const struct hwcap_data { .hwcap_bit = HWCAP2_SVE_EBF16, .cpuinfo = "sveebf16", }, + { + .name = "HBC", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_HBC, + .cpuinfo = "hbc", + .sigill_fn = hbc_sigill, + .sigill_reliable = true, + }, }; static bool seen_sigill; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test 2023-08-01 10:00 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test Joey Gouly @ 2023-08-01 15:09 ` Will Deacon 2023-08-01 15:26 ` Joey Gouly 0 siblings, 1 reply; 8+ messages in thread From: Will Deacon @ 2023-08-01 15:09 UTC (permalink / raw) To: Joey Gouly; +Cc: linux-arm-kernel, nd, catalin.marinas On Tue, Aug 01, 2023 at 11:00:08AM +0100, Joey Gouly wrote: > Add a test for the newly added HWCAP2_HBC. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > --- > tools/testing/selftests/arm64/abi/hwcap.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c > index d4ad813fed10..296102cd9192 100644 > --- a/tools/testing/selftests/arm64/abi/hwcap.c > +++ b/tools/testing/selftests/arm64/abi/hwcap.c > @@ -208,6 +208,13 @@ static void svebf16_sigill(void) > asm volatile(".inst 0x658aa000" : : : "z0"); > } > > +static void hbc_sigill(void) > +{ > + /* BC.EQ +4 */ > + asm volatile("cmp xzr, xzr\n" > + ".inst 0x54000030" : : :); > +} Do you need a "cc" clobber here, or is that implicit somehow? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test 2023-08-01 15:09 ` Will Deacon @ 2023-08-01 15:26 ` Joey Gouly 0 siblings, 0 replies; 8+ messages in thread From: Joey Gouly @ 2023-08-01 15:26 UTC (permalink / raw) To: Will Deacon; +Cc: linux-arm-kernel, nd, catalin.marinas On Tue, Aug 01, 2023 at 04:09:14PM +0100, Will Deacon wrote: > On Tue, Aug 01, 2023 at 11:00:08AM +0100, Joey Gouly wrote: > > Add a test for the newly added HWCAP2_HBC. > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > --- > > tools/testing/selftests/arm64/abi/hwcap.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c > > index d4ad813fed10..296102cd9192 100644 > > --- a/tools/testing/selftests/arm64/abi/hwcap.c > > +++ b/tools/testing/selftests/arm64/abi/hwcap.c > > @@ -208,6 +208,13 @@ static void svebf16_sigill(void) > > asm volatile(".inst 0x658aa000" : : : "z0"); > > } > > > > +static void hbc_sigill(void) > > +{ > > + /* BC.EQ +4 */ > > + asm volatile("cmp xzr, xzr\n" > > + ".inst 0x54000030" : : :); > > +} > > Do you need a "cc" clobber here, or is that implicit somehow? I do, thanks for pointing that out. Thanks, Joey _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-08-04 13:20 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-01 10:00 [PATCH v1 0/2] HWCAP for FEAT_HBC Joey Gouly 2023-08-01 10:00 ` [PATCH v1 1/2] arm64: add HWCAP for FEAT_HBC (hinted conditional branches) Joey Gouly 2023-08-01 15:12 ` Will Deacon 2023-08-02 11:54 ` Joey Gouly 2023-08-04 13:19 ` Will Deacon 2023-08-01 10:00 ` [PATCH v1 2/2] selftests/arm64: add HWCAP2_HBC test Joey Gouly 2023-08-01 15:09 ` Will Deacon 2023-08-01 15:26 ` Joey Gouly
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