[PATCH 0/3] arm64: dts: ti: k3-am62p/j722s: Add gpio-ranges properties

[PATCH 0/3] arm64: dts: ti: k3-am62p/j722s: Add gpio-ranges properties

[Nishanth Menon]

Hi,

This series was tested on BeagleY-AI[1] using the script[2].

This allows gpiod to request for a gpio that is not in the default GPIO
mux mode and the framework controls the mux over to required GPIO mode.

The series is based off next-20240617.

NOTE: there is also a dtb_warning that is added, which as far as I can
see is either a dtschema bug or a pinctrl-single binding error. more
information in [3]

Jared McArthur (1):
  arm64: dts: ti: k3-j722s: Add gpio-ranges properties

Nishanth Menon (2):
  arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode
  arm64: dts: ti: k3-am62p: Add gpio-ranges properties

 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 14 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi  | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-j722s.dtsi      | 17 +++++++++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h       |  2 ++
 4 files changed, 43 insertions(+)


base-commit: 76db4c64526c5e8ba0f56ad3d890dce8f9b00bbc
[1] https://www.beagleboard.org/boards/beagley-ai
[2] https://gist.github.com/nmenon/4973770cf0df3f02c2e4f7f3d048d80d
[3] https://lore.kernel.org/r/20240618165102.2380159-1-nm@ti.com
-- 
2.43.0

[PATCH 1/3] arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode

[Nishanth Menon]

Introduce a GPIO mux mode macro for easier readability. All K3 devices
use mux mode 7 to switch to GPIO mux.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 4cd2df467d0b..b1a0415e6611 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -38,6 +38,8 @@
 #define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
 #define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
 
+#define PIN_GPIO_MUX_MODE	(7)
+
 #define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
-- 
2.43.0

Re: [PATCH 1/3] arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode

[Dhruva Gole]

Hi Nishanth,

On Jun 18, 2024 at 12:31:21 -0500, Nishanth Menon wrote:
> Introduce a GPIO mux mode macro for easier readability. All K3 devices
> use mux mode 7 to switch to GPIO mux.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> index 4cd2df467d0b..b1a0415e6611 100644
> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> @@ -38,6 +38,8 @@
>  #define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
>  #define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
>  
> +#define PIN_GPIO_MUX_MODE	(7)
> +

While I do agree that this is a standard thing, don't you think that
updating it everywhere else (k3 DTs) makes sense? Having the number 7 in some
places and others having PIN_GPIO_MUX_MODE will give rise to confusion I
feel.

-- 
Best regards,
Dhruva Gole <d-gole@ti.com>

Re: [PATCH 1/3] arm64: dts: ti: k3-pinctrl: Define a generic GPIO MUX Mode

[Nishanth Menon]

On 10:22-20240619, Dhruva Gole wrote:
> Hi Nishanth,
> 
> On Jun 18, 2024 at 12:31:21 -0500, Nishanth Menon wrote:
> > Introduce a GPIO mux mode macro for easier readability. All K3 devices
> > use mux mode 7 to switch to GPIO mux.
> > 
> > Signed-off-by: Nishanth Menon <nm@ti.com>
> > ---
> >  arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> > index 4cd2df467d0b..b1a0415e6611 100644
> > --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> > +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> > @@ -38,6 +38,8 @@
> >  #define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
> >  #define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
> >  
> > +#define PIN_GPIO_MUX_MODE	(7)
> > +
> 
> While I do agree that this is a standard thing, don't you think that
> updating it everywhere else (k3 DTs) makes sense? Having the number 7 in some
> places and others having PIN_GPIO_MUX_MODE will give rise to confusion I
> feel.
> 


Yes, thinking again, we will repeat using this for other SoCs as well for
gpio-ranges. I think it might be better if we did this instead:

/* Default mux configuration for gpio-ranges use with pinctrl */
#define PIN_GPIO_RANGE_IOPAD  (PIN_INPUT | 7)

* Clears up the understanding what the define is for.
* Consistent usage across K3 SoCs.
* Prevents mis-understanding where to use the macro.

Thoughts?
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

[PATCH 2/3] arm64: dts: ti: k3-am62p: Add gpio-ranges properties

[Nishanth Menon]

On the AM62P platform we have no single 1:1 relation regarding index
of GPIO and pin controller. The GPIOs and pin controller registers
have mapping and holes in the map. These have been extracted from the
AM62P data sheet.

Mux mode input is selected as it is bi-directional. In case a specific
pull type or a specific pin level drive setting is desired, the board
device tree files will have to explicitly mux those pins for the GPIO
with the desired setting.

Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p

Signed-off-by: Nishanth Menon <nm@ti.com>
---

Note: this generates a 'too large' warning for
pinctrl-single,gpio-ranges -
https://lore.kernel.org/r/20240618165102.2380159-1-nm@ti.com/ for more
details

 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 14 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi  | 10 ++++++++++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index eed06506f617..573c85486db1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -258,7 +258,17 @@ main_pmx0: pinctrl@f4000 {
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;
+		pinctrl-single,gpio-range =
+			<&main_pmx0_range 0 32 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&main_pmx0_range 33 92 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&main_pmx0_range 137 5 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&main_pmx0_range 143 3 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&main_pmx0_range 149 2 (PIN_INPUT | PIN_GPIO_MUX_MODE)>;
 		bootph-all;
+
+		main_pmx0_range: gpio-range {
+			#pinctrl-single,gpio-range-cells = <3>;
+		};
 	};
 
 	main_esm: esm@420000 {
@@ -543,6 +553,8 @@ main_gpio0: gpio@600000 {
 		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 77 0>;
 		clock-names = "gpio";
+		gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
+				<&main_pmx0 70 72 22>;
 	};
 
 	main_gpio1: gpio@601000 {
@@ -560,6 +572,8 @@ main_gpio1: gpio@601000 {
 		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 78 0>;
 		clock-names = "gpio";
+		gpio-ranges = <&main_pmx0 0 94 32>, <&main_pmx0 42 137 5>,
+				<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
 	};
 
 	sdhci0: mmc@fa10000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
index b973b550eb9d..a27dd12b44ac 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
@@ -11,7 +11,15 @@ mcu_pmx0: pinctrl@4084000 {
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
 		pinctrl-single,function-mask = <0xffffffff>;
+		pinctrl-single,gpio-range =
+			<&mcu_pmx_range 0 21 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&mcu_pmx_range 23 1 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+			<&mcu_pmx_range 32 2 (PIN_INPUT | PIN_GPIO_MUX_MODE)>;
 		bootph-all;
+
+		mcu_pmx_range: gpio-range {
+			#pinctrl-single,gpio-range-cells = <3>;
+		};
 	};
 
 	mcu_esm: esm@4100000 {
@@ -137,6 +145,8 @@ mcu_gpio0: gpio@4201000 {
 		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 79 0>;
 		clock-names = "gpio";
+		gpio-ranges = <&mcu_pmx0 0 0 21>, <&mcu_pmx0 21 23 1>,
+				<&mcu_pmx0 22 32 2>;
 	};
 
 	mcu_rti0: watchdog@4880000 {
-- 
2.43.0

Re: [PATCH 2/3] arm64: dts: ti: k3-am62p: Add gpio-ranges properties

[Dhruva Gole]

On Jun 18, 2024 at 12:31:22 -0500, Nishanth Menon wrote:
> On the AM62P platform we have no single 1:1 relation regarding index
> of GPIO and pin controller. The GPIOs and pin controller registers
> have mapping and holes in the map. These have been extracted from the
> AM62P data sheet.
> 
> Mux mode input is selected as it is bi-directional. In case a specific
> pull type or a specific pin level drive setting is desired, the board
> device tree files will have to explicitly mux those pins for the GPIO
> with the desired setting.
> 
> Ref: AM62P Data sheet https://www.ti.com/lit/gpn/am62p
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> 
> Note: this generates a 'too large' warning for
> pinctrl-single,gpio-ranges -
> https://lore.kernel.org/r/20240618165102.2380159-1-nm@ti.com/ for more
> details
> 
>  arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 14 ++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi  | 10 ++++++++++
>  2 files changed, 24 insertions(+)


Reviewed-by: Dhruva Gole <d-gole@ti.com>

-- 
Best regards,
Dhruva

[PATCH 3/3] arm64: dts: ti: k3-j722s: Add gpio-ranges properties

[Nishanth Menon]

From: Jared McArthur <j-mcarthur@ti.com>

The AM67A/J722S/TDA4AEN platform is a derivative of AM62P platform
and we have no single 1:1 relation regarding index of GPIO and pin
controller. The GPIOs and pin controller registers have mapping and
holes in the map. These have been extracted from the J722S data
sheet. The MCU mapping is carried forward as is with J722S, however the
main GPIO block has differences that needs to be accounted for.

Mux mode input is selected as it is bi-directional. In case a specific
pull type or a specific pin level drive setting is desired, the board
device tree files will have to explicitly mux those pins for the GPIO
with the desired setting.

Ref: J722S Data sheet https://www.ti.com/lit/gpn/tda4aen-q1

Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---

Note: this generates a 'too large' warning for
pinctrl-single,gpio-ranges -
https://lore.kernel.org/r/20240618165102.2380159-1-nm@ti.com/ for more
details

 arch/arm64/boot/dts/ti/k3-j722s.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index 9132b0232b0b..84441a8ed4f0 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -83,11 +83,28 @@ &inta_main_dmss {
 	ti,interrupt-ranges = <7 71 21>;
 };
 
+&main_pmx0 {
+	pinctrl-single,gpio-range =
+		<&main_pmx0_range 0 32 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 33 55 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 101 25 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 137 5 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 143 3 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 149 2 (PIN_INPUT | PIN_GPIO_MUX_MODE)>;
+};
+
 &main_gpio0 {
+	gpio-ranges = <&main_pmx0 0 0 32>,
+		      <&main_pmx0 32 33 38>,
+		      <&main_pmx0 70 72 17>;
 	ti,ngpio = <87>;
 };
 
 &main_gpio1 {
+	gpio-ranges = <&main_pmx0 7 101 25>,
+		      <&main_pmx0 42 137 5>,
+		      <&main_pmx0 47 143 3>,
+		      <&main_pmx0 50 149 2>;
 	ti,ngpio = <73>;
 };
 
-- 
2.43.0