Re: [PATCH 3/3] arm64: errata: Expand speculative SSBS workaround (again)

[Will Deacon <will@kernel.org>]

On Thu, Aug 01, 2024 at 11:18:03AM +0100, Mark Rutland wrote:
> A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS
> special-purpose register does not affect subsequent speculative
> instructions, permitting speculative store bypassing for a window of
> time.
> 
> We worked around this for a number of CPUs in commits:
> 
> * 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417")
> * 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround")
> 
> Since then, similar errata have been published for a number of other Arm
> Ltd CPUs, for which the same mitigation is sufficient. This is described
> in their respective Software Developer Errata Notice (SDEN) documents:
> 
> * Cortex-A76 (MP052) SDEN v31.0, erratum 3324349
>   https://developer.arm.com/documentation/SDEN-885749/3100/
> 
> * Cortex-A77 (MP074) SDEN v19.0, erratum 3324348
>   https://developer.arm.com/documentation/SDEN-1152370/1900/
> 
> * Cortex-A78 (MP102) SDEN v21.0, erratum 3324344
>   https://developer.arm.com/documentation/SDEN-1401784/2100/
> 
> * Cortex-A78C (MP138) SDEN v16.0, erratum 3324346
>   https://developer.arm.com/documentation/SDEN-1707916/1600/
> 
> * Cortex-A78C (MP154) SDEN v10.0, erratum 3324347
>   https://developer.arm.com/documentation/SDEN-2004089/1000/
> 
> * Cortex-A725 (MP190) SDEN v5.0, erratum 3456106
>   https://developer.arm.com/documentation/SDEN-2832921/0500/
> 
> * Cortex-X1 (MP077) SDEN v21.0, erratum 3324344
>   https://developer.arm.com/documentation/SDEN-1401782/2100/
> 
> * Cortex-X1C (MP136) SDEN v16.0, erratum 3324346
>   https://developer.arm.com/documentation/SDEN-1707914/1600/
> 
> * Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349
>   https://developer.arm.com/documentation/SDEN-885747/3200/
> 
> * Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341
>   https://developer.arm.com/documentation/SDEN-1401781/1900/
> 
> Note that due to the manner in which Arm develops IP and tracks errata,
> some CPUs share a common erratum number and some CPUs have multiple
> erratum numbers for the same HW issue.
> 
> On parts without SB, it is necessary to use ISB for the workaround. The
> spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB"
> sequence in this case, which is sufficient on all affected parts.
> 
> Enable the existing mitigation by adding the relevant MIDRs to
> erratum_spec_ssbs_list. The list is sorted alphanumerically (involving
> moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and
> potentially extend again in future. The Kconfig text is also updated to
> clarify the set of affected parts and the mitigation.
> 
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  Documentation/arch/arm64/silicon-errata.rst | 18 +++++++++++++++++
>  arch/arm64/Kconfig                          | 22 +++++++++++++++------
>  arch/arm64/kernel/cpu_errata.c              | 11 ++++++++++-
>  3 files changed, 44 insertions(+), 7 deletions(-)

Thanks. This looks correct as far as I can tell:

Acked-by: Will Deacon <will@kernel.org>

Will