From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, james.morse@arm.com, will@kernel.org
Subject: Re: [PATCH 1/3] arm64: cputype: Add Cortex-X1C definitions
Date: Thu, 1 Aug 2024 17:12:03 +0530 [thread overview]
Message-ID: <ed8d11e9-620a-44a0-bf72-23885175fc98@arm.com> (raw)
In-Reply-To: <20240801101803.1982459-2-mark.rutland@arm.com>
On 8/1/24 15:48, Mark Rutland wrote:
> Add cputype definitions for Cortex-X1C. These will be used for errata
> detection in subsequent patches.
>
> These values can be found in the Cortex-X1C TRM:
>
> https://developer.arm.com/documentation/101968/0002/
>
> ... in section B2.107 ("MIDR_EL1, Main ID Register, EL1").
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Will Deacon <will@kernel.org>
> ---
> arch/arm64/include/asm/cputype.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 1cb0704c6163f..5dc68ace305e5 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -86,6 +86,7 @@
> #define ARM_CPU_PART_CORTEX_X2 0xD48
> #define ARM_CPU_PART_NEOVERSE_N2 0xD49
> #define ARM_CPU_PART_CORTEX_A78C 0xD4B
> +#define ARM_CPU_PART_CORTEX_X1C 0xD4C
> #define ARM_CPU_PART_CORTEX_X3 0xD4E
> #define ARM_CPU_PART_NEOVERSE_V2 0xD4F
> #define ARM_CPU_PART_CORTEX_A720 0xD81
> @@ -165,6 +166,7 @@
> #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
> #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
> #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
> +#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
> #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
> #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
> #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
The CPU part number 0xD4C checks out in the mentioned document above.
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
next prev parent reply other threads:[~2024-08-01 11:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-01 10:18 [PATCH 0/3] arm64: errata: Expand speculative SSBS workaround (again) Mark Rutland
2024-08-01 10:18 ` [PATCH 1/3] arm64: cputype: Add Cortex-X1C definitions Mark Rutland
2024-08-01 11:42 ` Anshuman Khandual [this message]
2024-08-01 10:18 ` [PATCH 2/3] arm64: cputype: Add Cortex-A725 definitions Mark Rutland
2024-08-01 11:42 ` Anshuman Khandual
2024-08-01 10:18 ` [PATCH 3/3] arm64: errata: Expand speculative SSBS workaround (again) Mark Rutland
2024-08-01 12:06 ` Anshuman Khandual
2024-08-01 13:49 ` Will Deacon
2024-08-01 17:14 ` [PATCH 0/3] " Catalin Marinas
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