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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, james.morse@arm.com, will@kernel.org
Subject: Re: [PATCH 2/3] arm64: cputype: Add Cortex-A725 definitions
Date: Thu, 1 Aug 2024 17:12:58 +0530	[thread overview]
Message-ID: <29466ee2-c769-493a-85b0-8821bfd83e4f@arm.com> (raw)
In-Reply-To: <20240801101803.1982459-3-mark.rutland@arm.com>



On 8/1/24 15:48, Mark Rutland wrote:
> Add cputype definitions for Cortex-A725. These will be used for errata
> detection in subsequent patches.
> 
> These values can be found in the Cortex-A725 TRM:
> 
>   https://developer.arm.com/documentation/107652/0001/
> 
> ... in table A-247 ("MIDR_EL1 bit descriptions").
> 
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/include/asm/cputype.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 5dc68ace305e5..5fd7caea44193 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -93,6 +93,7 @@
>  #define ARM_CPU_PART_CORTEX_X4		0xD82
>  #define ARM_CPU_PART_NEOVERSE_V3	0xD84
>  #define ARM_CPU_PART_CORTEX_X925	0xD85
> +#define ARM_CPU_PART_CORTEX_A725	0xD87
>  
>  #define APM_CPU_PART_XGENE		0x000
>  #define APM_CPU_VAR_POTENZA		0x00
> @@ -173,6 +174,7 @@
>  #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
>  #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
>  #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
> +#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
>  #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
>  #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
>  #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

The CPU part number 0xD87 checks out in the mentioned document above.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>


  reply	other threads:[~2024-08-01 11:43 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-01 10:18 [PATCH 0/3] arm64: errata: Expand speculative SSBS workaround (again) Mark Rutland
2024-08-01 10:18 ` [PATCH 1/3] arm64: cputype: Add Cortex-X1C definitions Mark Rutland
2024-08-01 11:42   ` Anshuman Khandual
2024-08-01 10:18 ` [PATCH 2/3] arm64: cputype: Add Cortex-A725 definitions Mark Rutland
2024-08-01 11:42   ` Anshuman Khandual [this message]
2024-08-01 10:18 ` [PATCH 3/3] arm64: errata: Expand speculative SSBS workaround (again) Mark Rutland
2024-08-01 12:06   ` Anshuman Khandual
2024-08-01 13:49   ` Will Deacon
2024-08-01 17:14 ` [PATCH 0/3] " Catalin Marinas

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