[PATCH 1/4] dt-bindings: clock: imx95: add PCIE and USB PHY clk

[PATCH 1/4] dt-bindings: clock: imx95: add PCIE and USB PHY clk

[Xu Yang]

Add two clock definition in HSIOMIX.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 include/dt-bindings/clock/nxp,imx95-clock.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
index b7a713a9ac8c..a70a1473907d 100644
--- a/include/dt-bindings/clock/nxp,imx95-clock.h
+++ b/include/dt-bindings/clock/nxp,imx95-clock.h
@@ -28,4 +28,7 @@
 #define IMX95_CLK_NETCMIX_ENETC0_RMII		0
 #define IMX95_CLK_NETCMIX_ENETC1_RMII		1
 
+#define IMX95_CLK_HSIOMIX_PCIE_CLK_GATE		0
+#define IMX95_CLK_HSIOMIX_USB_PHY_CLK_SEL	1
+
 #endif	/* __DT_BINDINGS_CLOCK_IMX95_H */
-- 
2.34.1

[PATCH 2/4] clk: imx95-blk-ctl: fix hsio_blk_ctl_clk_dev_data reg offset

[Xu Yang]

The first item of hsio_blk_ctl_clk_dev_data is used to control PCIe
reference clock. The reg offset should be 0xc0 in HSIO block control
register map. Correct it so that other hsio block control items can
be added later. This will also rename the name to "hsio_pcie_clk_gate"
for better distinction.

Fixes: cf295252f0d8 ("clk: imx95-blk-ctl: Add one clock gate for HSIO block")
Cc: stable@vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 56bed4471995..3c2019f428c9 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -285,10 +285,10 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
 
 static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
 	[0] = {
-		.name = "hsio_blk_ctl_clk",
+		.name = "hsio_pcie_clk_gate",
 		.parent_names = (const char *[]){ "hsio_pll", },
 		.num_parents = 1,
-		.reg = 0,
+		.reg = 0xc0,
 		.bit_idx = 6,
 		.bit_width = 1,
 		.type = CLK_GATE,
-- 
2.34.1

[PATCH 3/4] clk: imx95-blk-ctl: Add one clock mux for HSIO block

[Xu Yang]

The GPR_REG0 register has an USB_PHY_REF_CLK_SEL (bit 6) to select USB 3.0
PHY reference clock.

USB_PHY_REF_CLK_SEL:
bit[6]   - 0b 24 MHz external oscillator
         - 1b 100 MHz high performance PLL

Add a clock multiplexer to support USB3.0 PHY clock selection.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 3c2019f428c9..ca06eee00e52 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -284,7 +284,7 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
 };
 
 static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
-	[0] = {
+	[IMX95_CLK_HSIOMIX_PCIE_CLK_GATE] = {
 		.name = "hsio_pcie_clk_gate",
 		.parent_names = (const char *[]){ "hsio_pll", },
 		.num_parents = 1,
@@ -293,11 +293,21 @@ static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
 		.bit_width = 1,
 		.type = CLK_GATE,
 		.flags = CLK_SET_RATE_PARENT,
-	}
+	},
+	[IMX95_CLK_HSIOMIX_USB_PHY_CLK_SEL] = {
+		.name = "usb_phy_ref_clk_sel",
+		.parent_names = (const char *[]){"osc24m", "hsiopll"},
+		.num_parents = 2,
+		.reg = 0,
+		.bit_idx = 6,
+		.bit_width = 1,
+		.type = CLK_MUX,
+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+	},
 };
 
 static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
-	.num_clks = 1,
+	.num_clks = ARRAY_SIZE(hsio_blk_ctl_clk_dev_data),
 	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
 	.clk_reg_offset = 0,
 };
-- 
2.34.1

[PATCH 4/4] arm64: dts: imx95: fix hsio_blk_ctl reg map

[Xu Yang]

The HSIO block control register map should be 0x4c010000~0x4c01FFFF.
Correct the start address and set length to 0x100 for available
registers.

Fixes: 3c8d7b5d2bed ("arm64: dts: imx95: add ref clock for pcie nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 1292677cbe4e..21c9df445be0 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1774,9 +1774,9 @@ usb3_dwc3: usb@4c100000 {
 			};
 		};
 
-		hsio_blk_ctl: syscon@4c0100c0 {
+		hsio_blk_ctl: syscon@4c010000 {
 			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
-			reg = <0x0 0x4c0100c0 0x0 0x1>;
+			reg = <0x0 0x4c010000 0x0 0x100>;
 			#clock-cells = <1>;
 			clocks = <&clk_sys100m>;
 			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
@@ -1844,7 +1844,7 @@ pcie0: pcie@4c300000 {
 				 <&scmi_clk IMX95_CLK_HSIOPLL>,
 				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
 				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
-				 <&hsio_blk_ctl 0>;
+				 <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;
 			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
 			assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
 					  <&scmi_clk IMX95_CLK_HSIOPLL>,
@@ -1919,7 +1919,7 @@ pcie1: pcie@4c380000 {
 				 <&scmi_clk IMX95_CLK_HSIOPLL>,
 				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
 				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
-				 <&hsio_blk_ctl 0>;
+				 <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;
 			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
 			assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
 					  <&scmi_clk IMX95_CLK_HSIOPLL>,
-- 
2.34.1

Re: [PATCH 2/4] clk: imx95-blk-ctl: fix hsio_blk_ctl_clk_dev_data reg offset

[Frank Li]

On Tue, Nov 18, 2025 at 03:40:53PM +0800, Xu Yang wrote:
> The first item of hsio_blk_ctl_clk_dev_data is used to control PCIe
> reference clock. The reg offset should be 0xc0 in HSIO block control
> register map. Correct it so that other hsio block control items can
> be added later. This will also rename the name to "hsio_pcie_clk_gate"
> for better distinction.
>
> Fixes: cf295252f0d8 ("clk: imx95-blk-ctl: Add one clock gate for HSIO block")
> Cc: stable@vger.kernel.org
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 56bed4471995..3c2019f428c9 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -285,10 +285,10 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
>
>  static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
>  	[0] = {
> -		.name = "hsio_blk_ctl_clk",
> +		.name = "hsio_pcie_clk_gate",
>  		.parent_names = (const char *[]){ "hsio_pll", },
>  		.num_parents = 1,
> -		.reg = 0,
> +		.reg = 0xc0,

This will break compatiblity. DTS is required related change at the same
time to match this change.

Is it possible to create new instance at dts

hsio_blk_ctl0: syscon@4c010000 {
	...
}

hsio_blk_ctl1: syscon@4c0100c0 {
        ...
}

You use <&hsio_blk_ctl1 IMX95_CLK_HSIOMIX_USB_PHY_CLK_SEL>

use IMX95_CLK_HSIOMIX_USB_PHY_CLK_SEL to distingiush which clocks.

Frank
>
>
>  		.bit_idx = 6,
>  		.bit_width = 1,
>  		.type = CLK_GATE,
> --
> 2.34.1
>

Re: [PATCH 4/4] arm64: dts: imx95: fix hsio_blk_ctl reg map

[Krzysztof Kozlowski]

On Tue, Nov 18, 2025 at 03:40:55PM +0800, Xu Yang wrote:
> The HSIO block control register map should be 0x4c010000~0x4c01FFFF.
> Correct the start address and set length to 0x100 for available
> registers.
> 
> Fixes: 3c8d7b5d2bed ("arm64: dts: imx95: add ref clock for pcie nodes")
> Cc: stable@vger.kernel.org
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 1292677cbe4e..21c9df445be0 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1774,9 +1774,9 @@ usb3_dwc3: usb@4c100000 {
>  			};
>  		};
>  
> -		hsio_blk_ctl: syscon@4c0100c0 {
> +		hsio_blk_ctl: syscon@4c010000 {
>  			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> -			reg = <0x0 0x4c0100c0 0x0 0x1>;
> +			reg = <0x0 0x4c010000 0x0 0x100>;
>  			#clock-cells = <1>;
>  			clocks = <&clk_sys100m>;
>  			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> @@ -1844,7 +1844,7 @@ pcie0: pcie@4c300000 {
>  				 <&scmi_clk IMX95_CLK_HSIOPLL>,
>  				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
>  				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> -				 <&hsio_blk_ctl 0>;
> +				 <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;

This is unrelated change, nothing explained in commit msg. Please do not
combine independent changes into one commit. Non-fixes with
fixes either

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: clock: imx95: add PCIE and USB PHY clk

[Krzysztof Kozlowski]

On Tue, Nov 18, 2025 at 03:40:52PM +0800, Xu Yang wrote:
> Add two clock definition in HSIOMIX.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  include/dt-bindings/clock/nxp,imx95-clock.h | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: clock: imx95: add PCIE and USB PHY clk

[Stephen Boyd]

Quoting Xu Yang (2025-11-17 23:40:52)
> Add two clock definition in HSIOMIX.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---

Please send a cover letter next time that all the other patches are a
reply to.

Re: [PATCH 4/4] arm64: dts: imx95: fix hsio_blk_ctl reg map

[Xu Yang]

On Wed, Nov 19, 2025 at 08:44:04AM +0100, Krzysztof Kozlowski wrote:
> On Tue, Nov 18, 2025 at 03:40:55PM +0800, Xu Yang wrote:
> > The HSIO block control register map should be 0x4c010000~0x4c01FFFF.
> > Correct the start address and set length to 0x100 for available
> > registers.
> > 
> > Fixes: 3c8d7b5d2bed ("arm64: dts: imx95: add ref clock for pcie nodes")
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > index 1292677cbe4e..21c9df445be0 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> > @@ -1774,9 +1774,9 @@ usb3_dwc3: usb@4c100000 {
> >  			};
> >  		};
> >  
> > -		hsio_blk_ctl: syscon@4c0100c0 {
> > +		hsio_blk_ctl: syscon@4c010000 {
> >  			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> > -			reg = <0x0 0x4c0100c0 0x0 0x1>;
> > +			reg = <0x0 0x4c010000 0x0 0x100>;
> >  			#clock-cells = <1>;
> >  			clocks = <&clk_sys100m>;
> >  			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> > @@ -1844,7 +1844,7 @@ pcie0: pcie@4c300000 {
> >  				 <&scmi_clk IMX95_CLK_HSIOPLL>,
> >  				 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> >  				 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
> > -				 <&hsio_blk_ctl 0>;
> > +				 <&hsio_blk_ctl IMX95_CLK_HSIOMIX_PCIE_CLK_GATE>;
> 
> This is unrelated change, nothing explained in commit msg. Please do not
> combine independent changes into one commit. Non-fixes with
> fixes either

OK. Will add complete description for each changes next time.

Thanks,
Xu Yang

Re: [PATCH 1/4] dt-bindings: clock: imx95: add PCIE and USB PHY clk

[Xu Yang]

On Wed, Nov 19, 2025 at 10:11:47AM -0800, Stephen Boyd wrote:
> Quoting Xu Yang (2025-11-17 23:40:52)
> > Add two clock definition in HSIOMIX.
> > 
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> 
> Please send a cover letter next time that all the other patches are a
> reply to.

Will do. 

Thanks,
Xu Yang