* [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B
@ 2025-10-20 2:37 Elaine Zhang
2025-10-20 2:37 ` [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() Elaine Zhang
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw)
To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh,
krzysztof.kozlowski+dt, conor+dt
Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip,
linux-kernel, huangtao
Add yaml and dt-bindings for the RV1126B.
Change in V3:
[PATCH v3 1/5]: No change
[PATCH v3 2/5]: Fix define error
[PATCH v3 3/5]: update driver,fix errir
[PATCH v3 4/5]: fix error
[PATCH v3 5/5]: No change
Change in V2:
[PATCH v2 1/5]: update commit message, rename v2 to multi_pll
[PATCH v2 2/5]: Modify DT binding headers license
[PATCH v2 3/5]: update driver
[PATCH v2 4/5]: fix error
[PATCH v2 5/5]: update commit message
Elaine Zhang (5):
clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
dt-bindings: clock, reset: Add support for rv1126b
clk: rockchip: Add clock controller for the RV1126B
dt-bindings: clock: Add support for rockchip pvtpll
clk: rockchip: add support for pvtpll clk
.../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++
.../bindings/clock/rockchip,rv1126b-cru.yaml | 52 +
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-cpu.c | 165 +++
drivers/clk/rockchip/clk-pvtpll.c | 925 ++++++++++++++
drivers/clk/rockchip/clk-rv1126b.c | 1105 +++++++++++++++++
drivers/clk/rockchip/clk.c | 24 +
drivers/clk/rockchip/clk.h | 83 ++
drivers/clk/rockchip/rst-rv1126b.c | 444 +++++++
.../dt-bindings/clock/rockchip,rv1126b-cru.h | 392 ++++++
.../dt-bindings/reset/rockchip,rv1126b-cru.h | 405 ++++++
12 files changed, 3703 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
create mode 100644 drivers/clk/rockchip/clk-pvtpll.c
create mode 100644 drivers/clk/rockchip/clk-rv1126b.c
create mode 100644 drivers/clk/rockchip/rst-rv1126b.c
create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h
create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h
base-commit: 9893549e592ad22d0a18de97acfb30204109290a
--
2.34.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang @ 2025-10-20 2:37 ` Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b Elaine Zhang ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw) To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao The current path will have an independent PLL(LPLL\BPLL) exclusively for the CPU to use. As follows: |-\ --lpll--| \ |mux|--[gate]--[div]--clk_core-- --gpll--| / |-/ The new chip does not have a dedicated PLL for the cpu; it is distributed nearby from the common PLL. If there are special frequency requirements that require the use of pvtpll, explanations will be submitted later. The clock path of new soc CPU simplified as follows: --gpll--|--\ | \ | \ | \ --v0pll--| mux |--[gate]--[div]--clk_core-- | / | / --v1pll--| / |--/ Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-cpu.c | 165 +++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 24 +++++ drivers/clk/rockchip/clk.h | 15 +++ 3 files changed, 204 insertions(+) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index dcc9dcb597ae..6e91a3041a03 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -396,3 +396,168 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, kfree(cpuclk); return ERR_PTR(ret); } + +static int rockchip_cpuclk_multi_pll_pre_rate_change(struct rockchip_cpuclk *cpuclk, + struct clk_notifier_data *ndata) +{ + unsigned long new_rate = roundup(ndata->new_rate, 1000); + const struct rockchip_cpuclk_rate_table *rate; + unsigned long flags; + + rate = rockchip_get_cpuclk_settings(cpuclk, new_rate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for cpuclk\n", + __func__, new_rate); + return -EINVAL; + } + + if (new_rate > ndata->old_rate) { + spin_lock_irqsave(cpuclk->lock, flags); + rockchip_cpuclk_set_dividers(cpuclk, rate); + spin_unlock_irqrestore(cpuclk->lock, flags); + } + + return 0; +} + +static int rockchip_cpuclk_multi_pll_post_rate_change(struct rockchip_cpuclk *cpuclk, + struct clk_notifier_data *ndata) +{ + unsigned long new_rate = roundup(ndata->new_rate, 1000); + const struct rockchip_cpuclk_rate_table *rate; + unsigned long flags; + + rate = rockchip_get_cpuclk_settings(cpuclk, new_rate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for cpuclk\n", + __func__, new_rate); + return -EINVAL; + } + + if (new_rate < ndata->old_rate) { + spin_lock_irqsave(cpuclk->lock, flags); + rockchip_cpuclk_set_dividers(cpuclk, rate); + spin_unlock_irqrestore(cpuclk->lock, flags); + } + + return 0; +} + +static int rockchip_cpuclk_multi_pll_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb); + int ret = 0; + + pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", + __func__, event, ndata->old_rate, ndata->new_rate); + if (event == PRE_RATE_CHANGE) + ret = rockchip_cpuclk_multi_pll_pre_rate_change(cpuclk, ndata); + else if (event == POST_RATE_CHANGE) + ret = rockchip_cpuclk_multi_pll_post_rate_change(cpuclk, ndata); + + return notifier_from_errno(ret); +} + +struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name, + const char *const *parent_names, + u8 num_parents, void __iomem *base, + int muxdiv_offset, u8 mux_shift, + u8 mux_width, u8 mux_flags, + int div_offset, u8 div_shift, + u8 div_width, u8 div_flags, + unsigned long flags, spinlock_t *lock, + const struct rockchip_cpuclk_rate_table *rates, + int nrates) +{ + struct rockchip_cpuclk *cpuclk; + struct clk_hw *hw; + struct clk_mux *mux = NULL; + struct clk_divider *div = NULL; + const struct clk_ops *mux_ops = NULL, *div_ops = NULL; + int ret; + + if (num_parents > 1) { + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + mux->reg = base + muxdiv_offset; + mux->shift = mux_shift; + mux->mask = BIT(mux_width) - 1; + mux->flags = mux_flags; + mux->lock = lock; + mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops + : &clk_mux_ops; + } + + if (div_width > 0) { + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + ret = -ENOMEM; + goto free_mux; + } + + div->flags = div_flags; + if (div_offset) + div->reg = base + div_offset; + else + div->reg = base + muxdiv_offset; + div->shift = div_shift; + div->width = div_width; + div->lock = lock; + div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) + ? &clk_divider_ro_ops + : &clk_divider_ops; + } + + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux ? &mux->hw : NULL, mux_ops, + div ? &div->hw : NULL, div_ops, + NULL, NULL, flags); + if (IS_ERR(hw)) { + ret = PTR_ERR(hw); + goto free_div; + } + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (!cpuclk) { + ret = -ENOMEM; + goto unregister_clk; + } + + cpuclk->reg_base = base; + cpuclk->lock = lock; + cpuclk->clk_nb.notifier_call = rockchip_cpuclk_multi_pll_notifier_cb; + ret = clk_notifier_register(hw->clk, &cpuclk->clk_nb); + if (ret) { + pr_err("%s: failed to register clock notifier for %s\n", + __func__, name); + goto free_cpuclk; + } + + if (nrates > 0) { + cpuclk->rate_count = nrates; + cpuclk->rate_table = kmemdup(rates, + sizeof(*rates) * nrates, + GFP_KERNEL); + if (!cpuclk->rate_table) { + ret = -ENOMEM; + goto free_cpuclk; + } + } + + return hw->clk; + +free_cpuclk: + kfree(cpuclk); +unregister_clk: + clk_hw_unregister_composite(hw); +free_div: + kfree(div); +free_mux: + kfree(mux); + + return ERR_PTR(ret); +} diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 19caf26c991b..2601df3b1066 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -722,6 +722,30 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, } EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); +void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + const struct rockchip_cpuclk_rate_table *rates, + int nrates) +{ + struct clk *clk; + + clk = rockchip_clk_register_cpuclk_multi_pll(list->name, list->parent_names, + list->num_parents, ctx->reg_base, + list->muxdiv_offset, list->mux_shift, + list->mux_width, list->mux_flags, + list->div_offset, list->div_shift, + list->div_width, list->div_flags, + list->flags, &ctx->lock, rates, nrates); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s: %ld\n", + __func__, list->name, PTR_ERR(clk)); + return; + } + + rockchip_clk_set_lookup(ctx, clk, list->id); +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk_multi_pll); + void rockchip_clk_protect_critical(const char *const clocks[], int nclocks) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 7c5e74c7a2e2..23653a942403 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -622,6 +622,17 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock); +struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name, + const char *const *parent_names, + u8 num_parents, void __iomem *base, + int muxdiv_offset, u8 mux_shift, + u8 mux_width, u8 mux_flags, + int div_offset, u8 div_shift, + u8 div_width, u8 div_flags, + unsigned long flags, spinlock_t *lock, + const struct rockchip_cpuclk_rate_table *rates, + int nrates); + struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *reg, @@ -1208,6 +1219,10 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates); +void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + const struct rockchip_cpuclk_rate_table *rates, + int nrates); void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, unsigned int reg, void (*cb)(void)); -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() Elaine Zhang @ 2025-10-20 2:37 ` Elaine Zhang 2025-10-20 17:27 ` Conor Dooley 2025-10-20 2:37 ` [PATCH v3 3/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw) To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao Add clock and reset ID defines for rv1126b. Also add documentation for the rv1126b CRU core. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../bindings/clock/rockchip,rv1126b-cru.yaml | 52 +++ .../dt-bindings/clock/rockchip,rv1126b-cru.h | 392 +++++++++++++++++ .../dt-bindings/reset/rockchip,rv1126b-cru.h | 405 ++++++++++++++++++ 3 files changed, 849 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml new file mode 100644 index 000000000000..61bfcde9b16a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126B Clock and Reset Unit + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The rv1126b clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126b-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rv1126b-cru"; + reg = <0x20000000 0xc0000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/rockchip,rv1126b-cru.h b/include/dt-bindings/clock/rockchip,rv1126b-cru.h new file mode 100644 index 000000000000..d6040058c21f --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rv1126b-cru.h @@ -0,0 +1,392 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H + +/* pll clocks */ +#define PLL_GPLL 1 +#define PLL_CPLL 2 +#define PLL_AUPLL 3 +#define ARMCLK 4 +#define SCLK_DDR 5 + +/* clk (clocks) */ +#define CLK_CPLL_DIV20 8 +#define CLK_CPLL_DIV10 9 +#define CLK_CPLL_DIV8 10 +#define CLK_GPLL_DIV8 11 +#define CLK_GPLL_DIV6 12 +#define CLK_GPLL_DIV4 13 +#define CLK_CPLL_DIV3 14 +#define CLK_GPLL_DIV3 15 +#define CLK_CPLL_DIV2 16 +#define CLK_GPLL_DIV2 17 +#define CLK_CM_FRAC0 18 +#define CLK_CM_FRAC1 19 +#define CLK_CM_FRAC2 20 +#define CLK_UART_FRAC0 21 +#define CLK_UART_FRAC1 22 +#define CLK_AUDIO_FRAC0 23 +#define CLK_AUDIO_FRAC1 24 +#define CLK_AUDIO_INT0 25 +#define CLK_AUDIO_INT1 26 +#define SCLK_UART0_SRC 27 +#define SCLK_UART1 28 +#define SCLK_UART2 29 +#define SCLK_UART3 30 +#define SCLK_UART4 31 +#define SCLK_UART5 32 +#define SCLK_UART6 33 +#define SCLK_UART7 34 +#define MCLK_SAI0 35 +#define MCLK_SAI1 36 +#define MCLK_SAI2 37 +#define MCLK_PDM 38 +#define CLKOUT_PDM 39 +#define MCLK_ASRC0 40 +#define MCLK_ASRC1 41 +#define MCLK_ASRC2 42 +#define MCLK_ASRC3 43 +#define CLK_ASRC0 44 +#define CLK_ASRC1 45 +#define CLK_CORE_PLL 46 +#define CLK_NPU_PLL 47 +#define CLK_VEPU_PLL 48 +#define CLK_ISP_PLL 49 +#define CLK_AISP_PLL 50 +#define CLK_SARADC0_SRC 51 +#define CLK_SARADC1_SRC 52 +#define CLK_SARADC2_SRC 53 +#define HCLK_NPU_ROOT 54 +#define PCLK_NPU_ROOT 55 +#define ACLK_VEPU_ROOT 56 +#define HCLK_VEPU_ROOT 57 +#define PCLK_VEPU_ROOT 58 +#define CLK_CORE_RGA_SRC 59 +#define ACLK_GMAC_ROOT 60 +#define ACLK_VI_ROOT 61 +#define HCLK_VI_ROOT 62 +#define PCLK_VI_ROOT 63 +#define DCLK_VICAP_ROOT 64 +#define CLK_SYS_DSMC_ROOT 65 +#define ACLK_VDO_ROOT 66 +#define ACLK_RKVDEC_ROOT 67 +#define HCLK_VDO_ROOT 68 +#define PCLK_VDO_ROOT 69 +#define DCLK_OOC_SRC 70 +#define DCLK_VOP 71 +#define DCLK_DECOM_SRC 72 +#define PCLK_DDR_ROOT 73 +#define ACLK_SYSMEM_SRC 74 +#define ACLK_TOP_ROOT 75 +#define ACLK_BUS_ROOT 76 +#define HCLK_BUS_ROOT 77 +#define PCLK_BUS_ROOT 78 +#define CCLK_SDMMC0 79 +#define CCLK_SDMMC1 80 +#define CCLK_EMMC 81 +#define SCLK_2X_FSPI0 82 +#define CLK_GMAC_PTP_REF_SRC 83 +#define CLK_GMAC_125M 84 +#define CLK_TIMER_ROOT 85 +#define TCLK_WDT_NS_SRC 86 +#define TCLK_WDT_S_SRC 87 +#define TCLK_WDT_HPMCU 88 +#define CLK_CAN0 89 +#define CLK_CAN1 90 +#define PCLK_PERI_ROOT 91 +#define ACLK_PERI_ROOT 92 +#define CLK_I2C_BUS_SRC 93 +#define CLK_SPI0 94 +#define CLK_SPI1 95 +#define BUSCLK_PMU_SRC 96 +#define CLK_PWM0 97 +#define CLK_PWM2 98 +#define CLK_PWM3 99 +#define CLK_PKA_RKCE_SRC 100 +#define ACLK_RKCE_SRC 101 +#define ACLK_VCP_ROOT 102 +#define HCLK_VCP_ROOT 103 +#define PCLK_VCP_ROOT 104 +#define CLK_CORE_FEC_SRC 105 +#define CLK_CORE_AVSP_SRC 106 +#define CLK_50M_GMAC_IOBUF_VI 107 +#define PCLK_TOP_ROOT 108 +#define CLK_MIPI0_OUT2IO 109 +#define CLK_MIPI1_OUT2IO 110 +#define CLK_MIPI2_OUT2IO 111 +#define CLK_MIPI3_OUT2IO 112 +#define CLK_CIF_OUT2IO 113 +#define CLK_MAC_OUT2IO 114 +#define MCLK_SAI0_OUT2IO 115 +#define MCLK_SAI1_OUT2IO 116 +#define MCLK_SAI2_OUT2IO 117 +#define CLK_CM_FRAC0_SRC 118 +#define CLK_CM_FRAC1_SRC 119 +#define CLK_CM_FRAC2_SRC 120 +#define CLK_UART_FRAC0_SRC 121 +#define CLK_UART_FRAC1_SRC 122 +#define CLK_AUDIO_FRAC0_SRC 123 +#define CLK_AUDIO_FRAC1_SRC 124 +#define ACLK_NPU_ROOT 125 +#define HCLK_RKNN 126 +#define ACLK_RKNN 127 +#define PCLK_GPIO3 128 +#define DBCLK_GPIO3 129 +#define PCLK_IOC_VCCIO3 130 +#define PCLK_SARADC0 131 +#define CLK_SARADC0 132 +#define HCLK_SDMMC1 133 +#define HCLK_VEPU 134 +#define ACLK_VEPU 135 +#define CLK_CORE_VEPU 136 +#define HCLK_FEC 137 +#define ACLK_FEC 138 +#define CLK_CORE_FEC 139 +#define HCLK_AVSP 140 +#define ACLK_AVSP 141 +#define BUSCLK_PMU1_ROOT 142 +#define HCLK_AISP 143 +#define ACLK_AISP 144 +#define CLK_CORE_AISP 145 +#define CLK_CORE_ISP_ROOT 146 +#define PCLK_DSMC 147 +#define ACLK_DSMC 148 +#define HCLK_CAN0 149 +#define HCLK_CAN1 150 +#define PCLK_GPIO2 151 +#define DBCLK_GPIO2 152 +#define PCLK_GPIO4 153 +#define DBCLK_GPIO4 154 +#define PCLK_GPIO5 155 +#define DBCLK_GPIO5 156 +#define PCLK_GPIO6 157 +#define DBCLK_GPIO6 158 +#define PCLK_GPIO7 159 +#define DBCLK_GPIO7 160 +#define PCLK_IOC_VCCIO2 161 +#define PCLK_IOC_VCCIO4 162 +#define PCLK_IOC_VCCIO5 163 +#define PCLK_IOC_VCCIO6 164 +#define PCLK_IOC_VCCIO7 165 +#define HCLK_ISP 166 +#define ACLK_ISP 167 +#define CLK_CORE_ISP 168 +#define HCLK_VICAP 169 +#define ACLK_VICAP 170 +#define DCLK_VICAP 171 +#define ISP0CLK_VICAP 172 +#define HCLK_VPSS 173 +#define ACLK_VPSS 174 +#define CLK_CORE_VPSS 175 +#define PCLK_CSI2HOST0 176 +#define DCLK_CSI2HOST0 177 +#define PCLK_CSI2HOST1 178 +#define DCLK_CSI2HOST1 179 +#define PCLK_CSI2HOST2 180 +#define DCLK_CSI2HOST2 181 +#define PCLK_CSI2HOST3 182 +#define DCLK_CSI2HOST3 183 +#define HCLK_SDMMC0 184 +#define ACLK_GMAC 185 +#define PCLK_GMAC 186 +#define CLK_GMAC_PTP_REF 187 +#define PCLK_CSIPHY0 188 +#define PCLK_CSIPHY1 189 +#define PCLK_MACPHY 190 +#define PCLK_SARADC1 191 +#define CLK_SARADC1 192 +#define PCLK_SARADC2 193 +#define CLK_SARADC2 194 +#define ACLK_RKVDEC 195 +#define HCLK_RKVDEC 196 +#define CLK_HEVC_CA_RKVDEC 197 +#define ACLK_VOP 198 +#define HCLK_VOP 199 +#define HCLK_RKJPEG 200 +#define ACLK_RKJPEG 201 +#define ACLK_RKMMU_DECOM 202 +#define HCLK_RKMMU_DECOM 203 +#define DCLK_DECOM 204 +#define ACLK_DECOM 205 +#define PCLK_DECOM 206 +#define PCLK_MIPI_DSI 207 +#define PCLK_DSIPHY 208 +#define ACLK_OOC 209 +#define ACLK_SYSMEM 210 +#define PCLK_DDRC 211 +#define PCLK_DDRMON 212 +#define CLK_TIMER_DDRMON 213 +#define PCLK_DFICTRL 214 +#define PCLK_DDRPHY 215 +#define PCLK_DMA2DDR 216 +#define CLK_RCOSC_SRC 217 +#define BUSCLK_PMU_MUX 218 +#define BUSCLK_PMU_ROOT 219 +#define PCLK_PMU 220 +#define CLK_XIN_RC_DIV 221 +#define CLK_32K 222 +#define PCLK_PMU_GPIO0 223 +#define DBCLK_PMU_GPIO0 224 +#define PCLK_PMU_HP_TIMER 225 +#define CLK_PMU_HP_TIMER 226 +#define CLK_PMU_32K_HP_TIMER 227 +#define PCLK_PWM1 228 +#define CLK_PWM1 229 +#define CLK_OSC_PWM1 230 +#define CLK_RC_PWM1 231 +#define CLK_FREQ_PWM1 232 +#define CLK_COUNTER_PWM1 233 +#define PCLK_I2C2 234 +#define CLK_I2C2 235 +#define PCLK_UART0 236 +#define SCLK_UART0 237 +#define PCLK_RCOSC_CTRL 238 +#define CLK_OSC_RCOSC_CTRL 239 +#define CLK_REF_RCOSC_CTRL 240 +#define PCLK_IOC_PMUIO0 241 +#define CLK_REFOUT 242 +#define CLK_PREROLL 243 +#define CLK_PREROLL_32K 244 +#define HCLK_PMU_SRAM 245 +#define PCLK_WDT_LPMCU 246 +#define TCLK_WDT_LPMCU 247 +#define CLK_LPMCU 248 +#define CLK_LPMCU_RTC 249 +#define PCLK_LPMCU_MAILBOX 250 +#define HCLK_OOC 251 +#define PCLK_SPI2AHB 252 +#define HCLK_SPI2AHB 253 +#define HCLK_FSPI1 254 +#define HCLK_XIP_FSPI1 255 +#define SCLK_1X_FSPI1 256 +#define PCLK_IOC_PMUIO1 257 +#define PCLK_AUDIO_ADC_PMU 258 +#define MCLK_AUDIO_ADC_PMU 259 +#define MCLK_AUDIO_ADC_DIV4_PMU 260 +#define MCLK_LPSAI 261 +#define ACLK_GIC400 262 +#define PCLK_WDT_NS 263 +#define TCLK_WDT_NS 264 +#define PCLK_WDT_HPMCU 265 +#define HCLK_CACHE 266 +#define PCLK_HPMCU_MAILBOX 267 +#define PCLK_HPMCU_INTMUX 268 +#define CLK_HPMCU 269 +#define CLK_HPMCU_RTC 270 +#define PCLK_RKDMA 271 +#define ACLK_RKDMA 272 +#define PCLK_DCF 273 +#define ACLK_DCF 274 +#define HCLK_RGA 275 +#define ACLK_RGA 276 +#define CLK_CORE_RGA 277 +#define PCLK_TIMER 278 +#define CLK_TIMER0 279 +#define CLK_TIMER1 280 +#define CLK_TIMER2 281 +#define CLK_TIMER3 282 +#define CLK_TIMER4 283 +#define CLK_TIMER5 284 +#define PCLK_I2C0 285 +#define CLK_I2C0 286 +#define PCLK_I2C1 287 +#define CLK_I2C1 288 +#define PCLK_I2C3 289 +#define CLK_I2C3 290 +#define PCLK_I2C4 291 +#define CLK_I2C4 292 +#define PCLK_I2C5 293 +#define CLK_I2C5 294 +#define PCLK_SPI0 295 +#define PCLK_SPI1 296 +#define PCLK_PWM0 297 +#define CLK_OSC_PWM0 298 +#define CLK_RC_PWM0 299 +#define PCLK_PWM2 300 +#define CLK_OSC_PWM2 301 +#define CLK_RC_PWM2 302 +#define PCLK_PWM3 303 +#define CLK_OSC_PWM3 304 +#define CLK_RC_PWM3 305 +#define PCLK_UART1 306 +#define PCLK_UART2 307 +#define PCLK_UART3 308 +#define PCLK_UART4 309 +#define PCLK_UART5 310 +#define PCLK_UART6 311 +#define PCLK_UART7 312 +#define PCLK_TSADC 313 +#define CLK_TSADC 314 +#define HCLK_SAI0 315 +#define HCLK_SAI1 316 +#define HCLK_SAI2 317 +#define HCLK_RKDSM 318 +#define MCLK_RKDSM 319 +#define HCLK_PDM 320 +#define HCLK_ASRC0 321 +#define HCLK_ASRC1 322 +#define PCLK_AUDIO_ADC_BUS 323 +#define MCLK_AUDIO_ADC_BUS 324 +#define MCLK_AUDIO_ADC_DIV4_BUS 325 +#define PCLK_RKCE 326 +#define HCLK_NS_RKCE 327 +#define PCLK_OTPC_NS 328 +#define CLK_SBPI_OTPC_NS 329 +#define CLK_USER_OTPC_NS 330 +#define CLK_OTPC_ARB 331 +#define PCLK_OTP_MASK 332 +#define CLK_TSADC_PHYCTRL 333 +#define LRCK_SRC_ASRC0 334 +#define LRCK_DST_ASRC0 335 +#define LRCK_SRC_ASRC1 336 +#define LRCK_DST_ASRC1 337 +#define PCLK_KEY_READER 338 +#define ACLK_NSRKCE 339 +#define CLK_PKA_NSRKCE 340 +#define PCLK_RTC_ROOT 341 +#define PCLK_GPIO1 342 +#define DBCLK_GPIO1 343 +#define PCLK_IOC_VCCIO1 344 +#define ACLK_USB3OTG 345 +#define CLK_REF_USB3OTG 346 +#define CLK_SUSPEND_USB3OTG 347 +#define HCLK_USB2HOST 348 +#define HCLK_ARB_USB2HOST 349 +#define PCLK_RTC_TEST 350 +#define HCLK_EMMC 351 +#define HCLK_FSPI0 352 +#define HCLK_XIP_FSPI0 353 +#define PCLK_PIPEPHY 354 +#define PCLK_USB2PHY 355 +#define CLK_REF_PIPEPHY_CPLL_SRC 356 +#define CLK_REF_PIPEPHY 357 +#define HCLK_VPSL 358 +#define ACLK_VPSL 359 +#define CLK_CORE_VPSL 360 +#define CLK_MACPHY 361 +#define HCLK_RKRNG_NS 362 +#define HCLK_RKRNG_S_NS 363 +#define CLK_AISP_PLL_SRC 364 + +/* secure clks */ +#define CLK_USER_OTPC_S 400 +#define CLK_SBPI_OTPC_S 401 +#define PCLK_OTPC_S 402 +#define PCLK_KEY_READER_S 403 +#define HCLK_KL_RKCE_S 404 +#define HCLK_RKCE_S 405 +#define PCLK_WDT_S 406 +#define TCLK_WDT_S 407 +#define CLK_STIMER0 408 +#define CLK_STIMER1 409 +#define PLK_STIMER 410 +#define HCLK_RKRNG_S 411 +#define CLK_PKA_RKCE_S 412 +#define ACLK_RKCE_S 413 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rv1126b-cru.h b/include/dt-bindings/reset/rockchip,rv1126b-cru.h new file mode 100644 index 000000000000..19d6de2c054f --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rv1126b-cru.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H + +/* ==========================list all of reset fields id=========================== */ +/* TOPCRU-->SOFTRST_CON00 */ + +/* TOPCRU-->SOFTRST_CON15 */ +#define SRST_PRESETN_CRU 0 +#define SRST_PRESETN_CRU_BIU 1 + +/* BUSCRU-->SOFTRST_CON00 */ +#define SRST_ARESETN_TOP_BIU 2 +#define SRST_ARESETN_RKCE_BIU 3 +#define SRST_ARESETN_BUS_BIU 4 +#define SRST_HRESETN_BUS_BIU 5 +#define SRST_PRESETN_BUS_BIU 6 +#define SRST_PRESETN_CRU_BUS 7 +#define SRST_PRESETN_SYS_GRF 8 +#define SRST_HRESETN_BOOTROM 9 +#define SRST_ARESETN_GIC400 10 +#define SRST_ARESETN_SPINLOCK 11 +#define SRST_PRESETN_WDT_NS 12 +#define SRST_TRESETN_WDT_NS 13 + +/* BUSCRU-->SOFTRST_CON01 */ +#define SRST_PRESETN_WDT_HPMCU 14 +#define SRST_TRESETN_WDT_HPMCU 15 +#define SRST_HRESETN_CACHE 16 +#define SRST_PRESETN_HPMCU_MAILBOX 17 +#define SRST_PRESETN_HPMCU_INTMUX 18 +#define SRST_RESETN_HPMCU_FULL_CLUSTER 19 +#define SRST_RESETN_HPMCU_PWUP 20 +#define SRST_RESETN_HPMCU_ONLY_CORE 21 +#define SRST_TRESETN_HPMCU_JTAG 22 +#define SRST_PRESETN_RKDMA 23 +#define SRST_ARESETN_RKDMA 24 + +/* BUSCRU-->SOFTRST_CON02 */ +#define SRST_PRESETN_DCF 25 +#define SRST_ARESETN_DCF 26 +#define SRST_HRESETN_RGA 27 +#define SRST_ARESETN_RGA 28 +#define SRST_RESETN_CORE_RGA 29 +#define SRST_PRESETN_TIMER 30 +#define SRST_RESETN_TIMER0 31 +#define SRST_RESETN_TIMER1 32 +#define SRST_RESETN_TIMER2 33 +#define SRST_RESETN_TIMER3 34 +#define SRST_RESETN_TIMER4 35 +#define SRST_RESETN_TIMER5 36 +#define SRST_ARESETN_RKCE 37 +#define SRST_RESETN_PKA_RKCE 38 +#define SRST_HRESETN_RKRNG_S 39 +#define SRST_HRESETN_RKRNG_NS 40 + +/* BUSCRU-->SOFTRST_CON03 */ +#define SRST_PRESETN_I2C0 41 +#define SRST_RESETN_I2C0 42 +#define SRST_PRESETN_I2C1 43 +#define SRST_RESETN_I2C1 44 +#define SRST_PRESETN_I2C3 45 +#define SRST_RESETN_I2C3 46 +#define SRST_PRESETN_I2C4 47 +#define SRST_RESETN_I2C4 48 +#define SRST_PRESETN_I2C5 49 +#define SRST_RESETN_I2C5 50 +#define SRST_PRESETN_SPI0 51 +#define SRST_RESETN_SPI0 52 +#define SRST_PRESETN_SPI1 53 +#define SRST_RESETN_SPI1 54 + +/* BUSCRU-->SOFTRST_CON04 */ +#define SRST_PRESETN_PWM0 55 +#define SRST_RESETN_PWM0 56 +#define SRST_PRESETN_PWM2 57 +#define SRST_RESETN_PWM2 58 +#define SRST_PRESETN_PWM3 59 +#define SRST_RESETN_PWM3 60 + +/* BUSCRU-->SOFTRST_CON05 */ +#define SRST_PRESETN_UART1 61 +#define SRST_SRESETN_UART1 62 +#define SRST_PRESETN_UART2 63 +#define SRST_SRESETN_UART2 64 +#define SRST_PRESETN_UART3 65 +#define SRST_SRESETN_UART3 66 +#define SRST_PRESETN_UART4 67 +#define SRST_SRESETN_UART4 68 +#define SRST_PRESETN_UART5 69 +#define SRST_SRESETN_UART5 70 +#define SRST_PRESETN_UART6 71 +#define SRST_SRESETN_UART6 72 +#define SRST_PRESETN_UART7 73 +#define SRST_SRESETN_UART7 74 + +/* BUSCRU-->SOFTRST_CON06 */ +#define SRST_PRESETN_TSADC 75 +#define SRST_RESETN_TSADC 76 +#define SRST_HRESETN_SAI0 77 +#define SRST_MRESETN_SAI0 78 +#define SRST_HRESETN_SAI1 79 +#define SRST_MRESETN_SAI1 80 +#define SRST_HRESETN_SAI2 81 +#define SRST_MRESETN_SAI2 82 +#define SRST_HRESETN_RKDSM 83 +#define SRST_MRESETN_RKDSM 84 +#define SRST_HRESETN_PDM 85 +#define SRST_MRESETN_PDM 86 +#define SRST_RESETN_PDM 87 + +/* BUSCRU-->SOFTRST_CON07 */ +#define SRST_HRESETN_ASRC0 88 +#define SRST_RESETN_ASRC0 89 +#define SRST_HRESETN_ASRC1 90 +#define SRST_RESETN_ASRC1 91 +#define SRST_PRESETN_AUDIO_ADC_BUS 92 +#define SRST_MRESETN_AUDIO_ADC_BUS 93 +#define SRST_PRESETN_RKCE 94 +#define SRST_HRESETN_NS_RKCE 95 +#define SRST_PRESETN_OTPC_NS 96 +#define SRST_RESETN_SBPI_OTPC_NS 97 +#define SRST_RESETN_USER_OTPC_NS 98 +#define SRST_RESETN_OTPC_ARB 99 +#define SRST_PRESETN_OTP_MASK 100 + +/* PERICRU-->SOFTRST_CON00 */ +#define SRST_ARESETN_PERI_BIU 101 +#define SRST_PRESETN_PERI_BIU 102 +#define SRST_PRESETN_RTC_BIU 103 +#define SRST_PRESETN_CRU_PERI 104 +#define SRST_PRESETN_PERI_GRF 105 +#define SRST_PRESETN_GPIO1 106 +#define SRST_DBRESETN_GPIO1 107 +#define SRST_PRESETN_IOC_VCCIO1 108 +#define SRST_ARESETN_USB3OTG 109 +#define SRST_HRESETN_USB2HOST 110 +#define SRST_HRESETN_ARB_USB2HOST 111 +#define SRST_PRESETN_RTC_TEST 112 + +/* PERICRU-->SOFTRST_CON01 */ +#define SRST_HRESETN_EMMC 113 +#define SRST_HRESETN_FSPI0 114 +#define SRST_HRESETN_XIP_FSPI0 115 +#define SRST_SRESETN_2X_FSPI0 116 +#define SRST_RESETN_UTMI_USB2HOST 117 +#define SRST_RESETN_REF_PIPEPHY 118 +#define SRST_PRESETN_PIPEPHY 119 +#define SRST_PRESETN_PIPEPHY_GRF 120 +#define SRST_PRESETN_USB2PHY 121 +#define SRST_RESETN_POR_USB2PHY 122 +#define SRST_RESETN_OTG_USB2PHY 123 +#define SRST_RESETN_HOST_USB2PHY 124 + +/* CORECRU-->SOFTRST_CON00 */ +#define SRST_RESETN_REF_PVTPLL_CORE 125 +#define SRST_NCOREPORESET0 126 +#define SRST_NCORESET0 127 +#define SRST_NCOREPORESET1 128 +#define SRST_NCORESET1 129 +#define SRST_NCOREPORESET2 130 +#define SRST_NCORESET2 131 +#define SRST_NCOREPORESET3 132 +#define SRST_NCORESET3 133 +#define SRST_NDBGRESET 134 +#define SRST_NL2RESET 135 + +/* CORECRU-->SOFTRST_CON01 */ +#define SRST_ARESETN_CORE_BIU 136 +#define SRST_PRESETN_CORE_BIU 137 +#define SRST_HRESETN_CORE_BIU 138 +#define SRST_PRESETN_DBG 139 +#define SRST_POTRESETN_DBG 140 +#define SRST_NTRESETN_DBG 141 +#define SRST_PRESETN_CORE_PVTPLL 142 +#define SRST_PRESETN_CRU_CORE 143 +#define SRST_PRESETN_CORE_GRF 144 +#define SRST_PRESETN_DFT2APB 145 + +/* PMUCRU-->SOFTRST_CON00 */ +#define SRST_HRESETN_PMU_BIU 146 +#define SRST_PRESETN_PMU_GPIO0 147 +#define SRST_DBRESETN_PMU_GPIO0 148 +#define SRST_PRESETN_PMU_HP_TIMER 149 +#define SRST_RESETN_PMU_HP_TIMER 150 +#define SRST_RESETN_PMU_32K_HP_TIMER 151 + +/* PMUCRU-->SOFTRST_CON01 */ +#define SRST_PRESETN_PWM1 152 +#define SRST_RESETN_PWM1 153 +#define SRST_PRESETN_I2C2 154 +#define SRST_RESETN_I2C2 155 +#define SRST_PRESETN_UART0 156 +#define SRST_SRESETN_UART0 157 + +/* PMUCRU-->SOFTRST_CON02 */ +#define SRST_PRESETN_RCOSC_CTRL 158 +#define SRST_RESETN_REF_RCOSC_CTRL 159 +#define SRST_PRESETN_IOC_PMUIO0 160 +#define SRST_PRESETN_CRU_PMU 161 +#define SRST_PRESETN_PMU_GRF 162 +#define SRST_RESETN_PREROLL 163 +#define SRST_RESETN_PREROLL_32K 164 +#define SRST_HRESETN_PMU_SRAM 165 + +/* PMUCRU-->SOFTRST_CON03 */ +#define SRST_PRESETN_WDT_LPMCU 166 +#define SRST_TRESETN_WDT_LPMCU 167 +#define SRST_RESETN_LPMCU_FULL_CLUSTER 168 +#define SRST_RESETN_LPMCU_PWUP 169 +#define SRST_RESETN_LPMCU_ONLY_CORE 170 +#define SRST_TRESETN_LPMCU_JTAG 171 +#define SRST_PRESETN_LPMCU_MAILBOX 172 + +/* PMU1CRU-->SOFTRST_CON00 */ +#define SRST_PRESETN_SPI2AHB 173 +#define SRST_HRESETN_SPI2AHB 174 +#define SRST_HRESETN_FSPI1 175 +#define SRST_HRESETN_XIP_FSPI1 176 +#define SRST_SRESETN_1X_FSPI1 177 +#define SRST_PRESETN_IOC_PMUIO1 178 +#define SRST_PRESETN_CRU_PMU1 179 +#define SRST_PRESETN_AUDIO_ADC_PMU 180 +#define SRST_MRESETN_AUDIO_ADC_PMU 181 +#define SRST_HRESETN_PMU1_BIU 182 + +/* PMU1CRU-->SOFTRST_CON01 */ +#define SRST_PRESETN_LPDMA 183 +#define SRST_ARESETN_LPDMA 184 +#define SRST_HRESETN_LPSAI 185 +#define SRST_MRESETN_LPSAI 186 +#define SRST_PRESETN_AOA_TDD 187 +#define SRST_PRESETN_AOA_FE 188 +#define SRST_PRESETN_AOA_AAD 189 +#define SRST_PRESETN_AOA_APB 190 +#define SRST_PRESETN_AOA_SRAM 191 + +/* DDRCRU-->SOFTRST_CON00 */ +#define SRST_PRESETN_DDR_BIU 192 +#define SRST_PRESETN_DDRC 193 +#define SRST_PRESETN_DDRMON 194 +#define SRST_RESETN_TIMER_DDRMON 195 +#define SRST_PRESETN_DFICTRL 196 +#define SRST_PRESETN_DDR_GRF 197 +#define SRST_PRESETN_CRU_DDR 198 +#define SRST_PRESETN_DDRPHY 199 +#define SRST_PRESETN_DMA2DDR 200 + +/* SUBDDRCRU-->SOFTRST_CON00 */ +#define SRST_ARESETN_SYSMEM_BIU 201 +#define SRST_ARESETN_SYSMEM 202 +#define SRST_ARESETN_DDR_BIU 203 +#define SRST_ARESETN_DDRSCH0_CPU 204 +#define SRST_ARESETN_DDRSCH1_NPU 205 +#define SRST_ARESETN_DDRSCH2_POE 206 +#define SRST_ARESETN_DDRSCH3_VI 207 +#define SRST_RESETN_CORE_DDRC 208 +#define SRST_RESETN_DDRMON 209 +#define SRST_RESETN_DFICTRL 210 +#define SRST_RESETN_RS 211 +#define SRST_ARESETN_DMA2DDR 212 +#define SRST_RESETN_DDRPHY 213 + +/* VICRU-->SOFTRST_CON00 */ +#define SRST_RESETN_REF_PVTPLL_ISP 214 +#define SRST_ARESETN_GMAC_BIU 215 +#define SRST_ARESETN_VI_BIU 216 +#define SRST_HRESETN_VI_BIU 217 +#define SRST_PRESETN_VI_BIU 218 +#define SRST_PRESETN_CRU_VI 219 +#define SRST_PRESETN_VI_GRF 220 +#define SRST_PRESETN_VI_PVTPLL 221 +#define SRST_PRESETN_DSMC 222 +#define SRST_ARESETN_DSMC 223 +#define SRST_HRESETN_CAN0 224 +#define SRST_RESETN_CAN0 225 +#define SRST_HRESETN_CAN1 226 +#define SRST_RESETN_CAN1 227 + +/* VICRU-->SOFTRST_CON01 */ +#define SRST_PRESETN_GPIO2 228 +#define SRST_DBRESETN_GPIO2 229 +#define SRST_PRESETN_GPIO4 230 +#define SRST_DBRESETN_GPIO4 231 +#define SRST_PRESETN_GPIO5 232 +#define SRST_DBRESETN_GPIO5 233 +#define SRST_PRESETN_GPIO6 234 +#define SRST_DBRESETN_GPIO6 235 +#define SRST_PRESETN_GPIO7 236 +#define SRST_DBRESETN_GPIO7 237 +#define SRST_PRESETN_IOC_VCCIO2 238 +#define SRST_PRESETN_IOC_VCCIO4 239 +#define SRST_PRESETN_IOC_VCCIO5 240 +#define SRST_PRESETN_IOC_VCCIO6 241 +#define SRST_PRESETN_IOC_VCCIO7 242 + +/* VICRU-->SOFTRST_CON02 */ +#define SRST_RESETN_CORE_ISP 243 +#define SRST_HRESETN_VICAP 244 +#define SRST_ARESETN_VICAP 245 +#define SRST_DRESETN_VICAP 246 +#define SRST_ISP0RESETN_VICAP 247 +#define SRST_RESETN_CORE_VPSS 248 +#define SRST_RESETN_CORE_VPSL 249 +#define SRST_PRESETN_CSI2HOST0 250 +#define SRST_PRESETN_CSI2HOST1 251 +#define SRST_PRESETN_CSI2HOST2 252 +#define SRST_PRESETN_CSI2HOST3 253 +#define SRST_HRESETN_SDMMC0 254 +#define SRST_ARESETN_GMAC 255 +#define SRST_PRESETN_CSIPHY0 256 +#define SRST_PRESETN_CSIPHY1 257 + +/* VICRU-->SOFTRST_CON03 */ +#define SRST_PRESETN_MACPHY 258 +#define SRST_RESETN_MACPHY 259 +#define SRST_PRESETN_SARADC1 260 +#define SRST_RESETN_SARADC1 261 +#define SRST_PRESETN_SARADC2 262 +#define SRST_RESETN_SARADC2 263 + +/* VEPUCRU-->SOFTRST_CON00 */ +#define SRST_RESETN_REF_PVTPLL_VEPU 264 +#define SRST_ARESETN_VEPU_BIU 265 +#define SRST_HRESETN_VEPU_BIU 266 +#define SRST_PRESETN_VEPU_BIU 267 +#define SRST_PRESETN_CRU_VEPU 268 +#define SRST_PRESETN_VEPU_GRF 269 +#define SRST_PRESETN_GPIO3 270 +#define SRST_DBRESETN_GPIO3 271 +#define SRST_PRESETN_IOC_VCCIO3 272 +#define SRST_PRESETN_SARADC0 273 +#define SRST_RESETN_SARADC0 274 +#define SRST_HRESETN_SDMMC1 275 + +/* VEPUCRU-->SOFTRST_CON01 */ +#define SRST_PRESETN_VEPU_PVTPLL 276 +#define SRST_HRESETN_VEPU 277 +#define SRST_ARESETN_VEPU 278 +#define SRST_RESETN_CORE_VEPU 279 + +/* NPUCRU-->SOFTRST_CON00 */ +#define SRST_RESETN_REF_PVTPLL_NPU 280 +#define SRST_ARESETN_NPU_BIU 281 +#define SRST_HRESETN_NPU_BIU 282 +#define SRST_PRESETN_NPU_BIU 283 +#define SRST_PRESETN_CRU_NPU 284 +#define SRST_PRESETN_NPU_GRF 285 +#define SRST_PRESETN_NPU_PVTPLL 286 +#define SRST_HRESETN_RKNN 287 +#define SRST_ARESETN_RKNN 288 + +/* VDOCRU-->SOFTRST_CON00 */ +#define SRST_ARESETN_RKVDEC_BIU 289 +#define SRST_ARESETN_VDO_BIU 290 +#define SRST_HRESETN_VDO_BIU 291 +#define SRST_PRESETN_VDO_BIU 292 +#define SRST_PRESETN_CRU_VDO 293 +#define SRST_PRESETN_VDO_GRF 294 +#define SRST_ARESETN_RKVDEC 295 +#define SRST_HRESETN_RKVDEC 296 +#define SRST_RESETN_HEVC_CA_RKVDEC 297 +#define SRST_ARESETN_VOP 298 +#define SRST_HRESETN_VOP 299 +#define SRST_DRESETN_VOP 300 +#define SRST_ARESETN_OOC 301 +#define SRST_HRESETN_OOC 302 +#define SRST_DRESETN_OOC 303 + +/* VDOCRU-->SOFTRST_CON01 */ +#define SRST_HRESETN_RKJPEG 304 +#define SRST_ARESETN_RKJPEG 305 +#define SRST_ARESETN_RKMMU_DECOM 306 +#define SRST_HRESETN_RKMMU_DECOM 307 +#define SRST_DRESETN_DECOM 308 +#define SRST_ARESETN_DECOM 309 +#define SRST_PRESETN_DECOM 310 +#define SRST_PRESETN_MIPI_DSI 311 +#define SRST_PRESETN_DSIPHY 312 + +/* VCPCRU-->SOFTRST_CON00 */ +#define SRST_RESETN_REF_PVTPLL_VCP 313 +#define SRST_ARESETN_VCP_BIU 314 +#define SRST_HRESETN_VCP_BIU 315 +#define SRST_PRESETN_VCP_BIU 316 +#define SRST_PRESETN_CRU_VCP 317 +#define SRST_PRESETN_VCP_GRF 318 +#define SRST_PRESETN_VCP_PVTPLL 319 +#define SRST_ARESETN_AISP_BIU 320 +#define SRST_HRESETN_AISP_BIU 321 +#define SRST_RESETN_CORE_AISP 322 + +/* VCPCRU-->SOFTRST_CON01 */ +#define SRST_HRESETN_FEC 323 +#define SRST_ARESETN_FEC 324 +#define SRST_RESETN_CORE_FEC 325 +#define SRST_HRESETN_AVSP 326 +#define SRST_ARESETN_AVSP 327 + +#endif -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b 2025-10-20 2:37 ` [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b Elaine Zhang @ 2025-10-20 17:27 ` Conor Dooley 0 siblings, 0 replies; 10+ messages in thread From: Conor Dooley @ 2025-10-20 17:27 UTC (permalink / raw) To: Elaine Zhang Cc: mturquette, sboyd, sugar.zhang, heiko, robh, krzysztof.kozlowski+dt, conor+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao [-- Attachment #1: Type: text/plain, Size: 2185 bytes --] On Mon, Oct 20, 2025 at 10:37:21AM +0800, Elaine Zhang wrote: > Add clock and reset ID defines for rv1126b. > Also add documentation for the rv1126b CRU core. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > .../bindings/clock/rockchip,rv1126b-cru.yaml | 52 +++ > .../dt-bindings/clock/rockchip,rv1126b-cru.h | 392 +++++++++++++++++ > .../dt-bindings/reset/rockchip,rv1126b-cru.h | 405 ++++++++++++++++++ > 3 files changed, 849 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml > create mode 100644 include/dt-bindings/clock/rockchip,rv1126b-cru.h > create mode 100644 include/dt-bindings/reset/rockchip,rv1126b-cru.h > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml > new file mode 100644 > index 000000000000..61bfcde9b16a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip RV1126B Clock and Reset Unit > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: > + The rv1126b clock controller generates the clock and also implements a > + reset controller for SoC peripherals. > + > +properties: > + compatible: > + enum: > + - rockchip,rv1126b-cru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: xin24m > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + cru: clock-controller@20000000 { Drop this label, and then Acked-by: Conor Dooley <conor.dooley@microchip.com> pw-bot: changes-requested Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/5] clk: rockchip: Add clock controller for the RV1126B 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b Elaine Zhang @ 2025-10-20 2:37 ` Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 5/5] clk: rockchip: add support for pvtpll clk Elaine Zhang 4 siblings, 0 replies; 10+ messages in thread From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw) To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao Add the clock and reset tree definitions for the new rv1126b SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rv1126b.c | 1105 ++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 68 ++ drivers/clk/rockchip/rst-rv1126b.c | 444 +++++++++++ 5 files changed, 1625 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rv1126b.c create mode 100644 drivers/clk/rockchip/rst-rv1126b.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index febb7944f34b..e1ea0a098ca9 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -30,6 +30,13 @@ config CLK_RV1126 help Build the driver for RV1126 Clock Driver. +config CLK_RV1126B + bool "Rockchip RV1126B clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RV1126B Clock Driver. + config CLK_RK3036 bool "Rockchip RK3036 clock controller support" depends on ARM || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index c281a9738d9f..82b4b29ad036 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -20,6 +20,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_CLK_PX30) += clk-px30.o obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o +obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o diff --git a/drivers/clk/rockchip/clk-rv1126b.c b/drivers/clk/rockchip/clk-rv1126b.c new file mode 100644 index 000000000000..dbf720d857c9 --- /dev/null +++ b/drivers/clk/rockchip/clk-rv1126b.c @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rockchip,rv1126b-cru.h> +#include "clk.h" + +#define RV1126B_GRF_SOC_STATUS0 0x10 + +#define RV1126B_FRAC_MAX_PRATE 1200000000 + +#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16)) + +enum rv1126b_plls { + gpll, cpll, aupll, dpll +}; + +static struct rockchip_pll_rate_table rv1126b_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355), + RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127), + RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185), + { /* sentinel */ }, +}; + +#define RV1126B_DIV_ACLK_CORE_MASK 0x1f +#define RV1126B_DIV_ACLK_CORE_SHIFT 0 +#define RV1126B_DIV_PCLK_CORE_MASK 0x1f +#define RV1126B_DIV_PCLK_CORE_SHIFT 8 +#define RV1126B_CORE_SEL_MASK 0x1 +#define RV1126B_CORE_SEL_SHIFT 1 + +#define RV1126B_CLKSEL0(_aclk_core) \ +{ \ + .reg = RV1126B_CORECLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \ + RV1126B_DIV_ACLK_CORE_SHIFT), \ +} + +#define RV1126B_CLKSEL1(_pclk_dbg) \ +{ \ + .reg = RV1126B_CORECLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \ + RV1126B_DIV_PCLK_CORE_SHIFT), \ +} + +#define RV1126B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ +{ \ + .prate = _prate, \ + .divs = { \ + RV1126B_CLKSEL0(_aclk_core), \ + RV1126B_CLKSEL1(_pclk_dbg), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rv1126b_cpuclk_rates[] __initdata = { + RV1126B_CPUCLK_RATE(1608000000, 4, 10), + RV1126B_CPUCLK_RATE(1512000000, 4, 10), + RV1126B_CPUCLK_RATE(1416000000, 4, 10), + RV1126B_CPUCLK_RATE(1296000000, 3, 10), + RV1126B_CPUCLK_RATE(1200000000, 3, 10), + RV1126B_CPUCLK_RATE(1188000000, 3, 8), + RV1126B_CPUCLK_RATE(1104000000, 2, 8), + RV1126B_CPUCLK_RATE(1008000000, 2, 8), + RV1126B_CPUCLK_RATE(816000000, 2, 6), + RV1126B_CPUCLK_RATE(600000000, 2, 4), + RV1126B_CPUCLK_RATE(594000000, 2, 4), + RV1126B_CPUCLK_RATE(408000000, 1, 3), + RV1126B_CPUCLK_RATE(396000000, 1, 3), +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" }; +PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" }; +PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" }; +PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" }; +PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" }; +PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" }; +PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", + "clk_uart_frac0", "clk_uart_frac1" }; +PNAME(mclk_sai0_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", + "clk_audio_frac0", "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io" }; +PNAME(mclk_sai1_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0", + "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai1_from_io" }; +PNAME(mclk_sai2_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0", + "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai2_from_io" }; +PNAME(mux_sai_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1", "clk_cm_frac2", "clk_audio_frac0", + "clk_audio_frac1", "clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io", + "mclk_sai1_from_io", "mclk_sai2_from_io"}; +PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; +PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" }; +PNAME(mux_500m_400m_200m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div6" }; +PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" }; +PNAME(mux_500m_400m_300m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4" }; +PNAME(mux_333m_200m_p) = { "clk_cpll_div3", "clk_gpll_div6" }; +PNAME(mux_600m_400m_200m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div6" }; +PNAME(mux_400m_300m_200m_p) = { "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" }; +PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_cpll_div10" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; +PNAME(mux_600m_24m_p) = { "clk_gpll_div2", "xin24m" }; +PNAME(mux_armclk_p) = { "clk_core_pll", "clk_core_pvtpll" }; +PNAME(aclk_npu_root_p) = { "clk_npu_pll", "clk_npu_pvtpll" }; +PNAME(clk_saradc0_p) = { "clk_saradc0_src", "clk_saradc0_rcosc_io" }; +PNAME(clk_core_vepu_p) = { "clk_vepu_pll", "clk_vepu_pvtpll" }; +PNAME(clk_core_fec_p) = { "clk_core_fec_src", "clk_vcp_pvtpll" }; +PNAME(clk_core_aisp_p) = { "clk_aisp_pll", "clk_vcp_pvtpll" }; +PNAME(clk_core_isp_root_p) = { "clk_isp_pll", "clk_isp_pvtpll" }; +PNAME(clk_gmac_ptp_ref_p) = { "clk_gmac_ptp_ref_src", "clk_gmac_ptp_from_io" }; +PNAME(clk_saradc1_p) = { "clk_saradc1_src", "clk_saradc1_rcosc_io" }; +PNAME(clk_saradc2_p) = { "clk_saradc2_src", "clk_saradc2_rcosc_io" }; +PNAME(clk_rcosc_src_p) = { "xin24m", "clk_rcosc", "clk_rcosc_div2", "clk_rcosc_div3", "clk_rcosc_div4" }; +PNAME(busclk_pmu_mux_p) = { "clk_cpll_div10", "clk_rcosc_src" }; +PNAME(clk_xin_rc_div_p) = { "xin24m", "clk_rcosc_src" }; +PNAME(clk_32k_p) = { "clk_xin_rc_div", "clk_32k_rtc", "clk_32k_io" }; +PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" }; +PNAME(mux_24m_rcosc_buspmu_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src" }; +PNAME(mux_24m_rcosc_buspmu_32k_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src", "clk_32k" }; +PNAME(sclk_uart0_p) = { "sclk_uart0_src", "xin24m", "clk_rcosc_src" }; +PNAME(clk_osc_rcosc_ctrl_p) = { "clk_rcosc_src", "clk_testout_out" }; +PNAME(lrck_src_asrc_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", + "fs_inter_from_sai0", "fs_inter_from_sai1", "fs_inter_from_sai2", "clkout_pdm"}; +PNAME(clk_ref_pipephy_p) = { "clk_ref_pipephy_cpll_src", "xin24m" }; +PNAME(clk_timer0_parents_p) = { "clk_timer_root", "mclk_sai0_from_io", "sclk_sai0_from_io" }; +PNAME(clk_timer1_parents_p) = { "clk_timer_root", "mclk_sai1_from_io", "sclk_sai1_from_io" }; +PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io", "sclk_sai2_from_io" }; +PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" }; +PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" }; +PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" }; +PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" }; + +static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = { + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + CLK_IS_CRITICAL, RV1126B_PLL_CON(8), + RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), + [aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p, + CLK_IS_CRITICAL, RV1126B_PLL_CON(0), + RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0), + RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates), + [dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p, + CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0), + RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rv1126b_rcdiv_pmu_fracmux __initdata = + MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RV1126B_PMUCLKSEL_CON(2), 1, 2, MFLAGS); + +static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = { + + FACTOR(0, "clk_rcosc_div2", "clk_rcosc", 0, 1, 2), + FACTOR(0, "clk_rcosc_div3", "clk_rcosc", 0, 1, 3), + FACTOR(0, "clk_rcosc_div4", "clk_rcosc", 0, 1, 4), + + /* Clock Definition */ + COMPOSITE_NODIV(CLK_AISP_PLL_SRC, "clk_aisp_pll_src", mux_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(62), 4, 2, MFLAGS, + RV1126B_CLKGATE_CON(5), 4, GFLAGS), + DIV(CLK_AISP_PLL, "clk_aisp_pll", "clk_aisp_pll_src", 0, + RV1126B_CLKSEL_CON(62), 0, 3, DFLAGS), + + COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", clk_cpll_div10_p, 0, + RV1126B_CLKSEL_CON(1), 15, 1, MFLAGS, 5, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_CPLL_DIV20, "clk_cpll_div20", "cpll", 0, + RV1126B_CLKSEL_CON(1), 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_CPLL_DIV8, "clk_cpll_div8", "cpll", 0, + RV1126B_CLKSEL_CON(1), 10, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV8, "clk_gpll_div8", "gpll", 0, + RV1126B_CLKSEL_CON(2), 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0, + RV1126B_CLKSEL_CON(2), 5, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0, + RV1126B_CLKSEL_CON(2), 10, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE_NOMUX(CLK_CPLL_DIV3, "clk_cpll_div3", "cpll", 0, + RV1126B_CLKSEL_CON(3), 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0, + RV1126B_CLKSEL_CON(3), 5, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_CPLL_DIV2, "clk_cpll_div2", "cpll", 0, + RV1126B_CLKSEL_CON(3), 10, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0, + RV1126B_CLKSEL_CON(4), 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(0), 9, GFLAGS), + MUX(CLK_CM_FRAC0_SRC, "clk_cm_frac0_src", mux_24m_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(10), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_CM_FRAC0, "clk_cm_frac0", "clk_cm_frac0_src", 0, + RV1126B_CLKSEL_CON(25), 0, + RV1126B_CLKGATE_CON(1), 0, GFLAGS), + MUX(CLK_CM_FRAC1_SRC, "clk_cm_frac1_src", mux_24m_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(10), 2, 2, MFLAGS), + COMPOSITE_FRAC(CLK_CM_FRAC1, "clk_cm_frac1", "clk_cm_frac1_src", 0, + RV1126B_CLKSEL_CON(26), 0, + RV1126B_CLKGATE_CON(1), 1, GFLAGS), + MUX(CLK_CM_FRAC2_SRC, "clk_cm_frac2_src", mux_24m_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(10), 4, 2, MFLAGS), + COMPOSITE_FRAC(CLK_CM_FRAC2, "clk_cm_frac2", "clk_cm_frac2_src", 0, + RV1126B_CLKSEL_CON(27), 0, + RV1126B_CLKGATE_CON(1), 2, GFLAGS), + MUX(CLK_UART_FRAC0_SRC, "clk_uart_frac0_src", mux_24m_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(10), 6, 2, MFLAGS), + COMPOSITE_FRAC(CLK_UART_FRAC0, "clk_uart_frac0", "clk_uart_frac0_src", 0, + RV1126B_CLKSEL_CON(28), 0, + RV1126B_CLKGATE_CON(1), 3, GFLAGS), + MUX(CLK_UART_FRAC1_SRC, "clk_uart_frac1_src", mux_24m_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(10), 8, 2, MFLAGS), + COMPOSITE_FRAC(CLK_UART_FRAC1, "clk_uart_frac1", "clk_uart_frac1_src", 0, + RV1126B_CLKSEL_CON(29), 0, + RV1126B_CLKGATE_CON(1), 4, GFLAGS), + MUX(CLK_AUDIO_FRAC0_SRC, "clk_audio_frac0_src", mux_24m_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(10), 10, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC0, "clk_audio_frac0", "clk_audio_frac0_src", 0, + RV1126B_CLKSEL_CON(30), 0, + RV1126B_CLKGATE_CON(1), 5, GFLAGS), + MUX(CLK_AUDIO_FRAC1_SRC, "clk_audio_frac1_src", mux_24m_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(10), 12, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC1, "clk_audio_frac1", "clk_audio_frac1_src", 0, + RV1126B_CLKSEL_CON(31), 0, + RV1126B_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE(CLK_AUDIO_INT0, "clk_audio_int0", mux_24m_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE(CLK_AUDIO_INT1, "clk_audio_int1", mux_24m_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE(SCLK_UART0_SRC, "sclk_uart0_src", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(12), 5, 3, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE(SCLK_UART1, "sclk_uart1", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(12), 13, 3, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE(SCLK_UART2, "sclk_uart2", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE(SCLK_UART3, "sclk_uart3", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(13), 13, 3, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(14), 5, 3, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(14), 13, 3, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(SCLK_UART6, "sclk_uart6", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(15), 5, 3, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE(SCLK_UART7, "sclk_uart7", mux_sclk_uart_src_p, 0, + RV1126B_CLKSEL_CON(15), 13, 3, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai0_src_p, 0, + RV1126B_CLKSEL_CON(16), 8, 4, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(2), 2, GFLAGS), + COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai1_src_p, 0, + RV1126B_CLKSEL_CON(17), 8, 4, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai2_src_p, 0, + RV1126B_CLKSEL_CON(18), 8, 4, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE(MCLK_PDM, "mclk_pdm", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(19), 6, 4, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE_NOGATE(0, "clkout_pdm_src", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(20), 8, 4, MFLAGS, 0, 8, DFLAGS), + GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0, + RV1126B_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(16), 12, 4, MFLAGS, + RV1126B_CLKGATE_CON(2), 7, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(17), 12, 4, MFLAGS, + RV1126B_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(18), 12, 4, MFLAGS, + RV1126B_CLKGATE_CON(2), 9, GFLAGS), + COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mux_sai_src_p, 0, + RV1126B_CLKSEL_CON(19), 12, 4, MFLAGS, + RV1126B_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE(CLK_ASRC0, "clk_asrc0", mux_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(21), 6, 1, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE(CLK_ASRC1, "clk_asrc1", mux_gpll_aupll_p, 0, + RV1126B_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(2), 12, GFLAGS), + COMPOSITE_NOMUX(CLK_CORE_PLL, "clk_core_pll", "gpll", CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(60), 0, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_NPU_PLL, "clk_npu_pll", "gpll", CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(60), 6, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 1, GFLAGS), + COMPOSITE(CLK_VEPU_PLL, "clk_vepu_pll", mux_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(61), 4, 2, MFLAGS, 0, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE(CLK_ISP_PLL, "clk_isp_pll", mux_gpll_aupll_cpll_p, 0, + RV1126B_CLKSEL_CON(61), 10, 2, MFLAGS, 6, 4, DFLAGS, + RV1126B_CLKGATE_CON(5), 3, GFLAGS), + COMPOSITE(CLK_SARADC0_SRC, "clk_saradc0_src", mux_200m_24m_p, 0, + RV1126B_CLKSEL_CON(63), 12, 1, MFLAGS, 0, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 6, GFLAGS), + COMPOSITE(CLK_SARADC1_SRC, "clk_saradc1_src", mux_200m_24m_p, 0, + RV1126B_CLKSEL_CON(63), 13, 1, MFLAGS, 4, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 7, GFLAGS), + COMPOSITE(CLK_SARADC2_SRC, "clk_saradc2_src", mux_200m_24m_p, 0, + RV1126B_CLKSEL_CON(63), 14, 1, MFLAGS, 8, 3, DFLAGS, + RV1126B_CLKGATE_CON(5), 8, GFLAGS), + GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(5), 10, GFLAGS), + GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(40), 0, 2, MFLAGS, + RV1126B_CLKGATE_CON(5), 12, GFLAGS), + GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(5), 13, GFLAGS), + GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0, + RV1126B_CLKGATE_CON(5), 14, GFLAGS), + COMPOSITE(CLK_CORE_RGA_SRC, "clk_core_rga_src", mux_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(40), 5, 1, MFLAGS, 2, 3, DFLAGS, + RV1126B_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_GMAC_ROOT, "aclk_gmac_root", mux_300m_200m_p, 0, + RV1126B_CLKSEL_CON(40), 6, 1, MFLAGS, + RV1126B_CLKGATE_CON(6), 1, GFLAGS), + COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_500m_400m_300m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(40), 7, 2, MFLAGS, + RV1126B_CLKGATE_CON(6), 2, GFLAGS), + GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(6), 3, GFLAGS), + GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(6), 4, GFLAGS), + COMPOSITE_NODIV(DCLK_VICAP_ROOT, "dclk_vicap_root", mux_333m_200m_p, 0, + RV1126B_CLKSEL_CON(42), 5, 1, MFLAGS, + RV1126B_CLKGATE_CON(6), 5, GFLAGS), + COMPOSITE(CLK_SYS_DSMC_ROOT, "clk_sys_dsmc_root", mux_24m_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(40), 14, 2, MFLAGS, 9, 5, DFLAGS, + RV1126B_CLKGATE_CON(6), 6, GFLAGS), + COMPOSITE(ACLK_VDO_ROOT, "aclk_vdo_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(42), 4, 1, MFLAGS, 0, 4, DFLAGS, + RV1126B_CLKGATE_CON(6), 7, GFLAGS), + COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", mux_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(42), 10, 1, MFLAGS, 6, 4, DFLAGS, + RV1126B_CLKGATE_CON(6), 8, GFLAGS), + GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(6), 9, GFLAGS), + GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(6), 10, GFLAGS), + COMPOSITE(DCLK_VOP, "dclk_vop", mux_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(43), 8, 1, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(6), 12, GFLAGS), + COMPOSITE(DCLK_OOC_SRC, "dclk_ooc_src", mux_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(62), 7, 1, MFLAGS, 8, 8, DFLAGS, + RV1126B_CLKGATE_CON(6), 13, GFLAGS), + GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0, + RV1126B_CLKGATE_CON(6), 14, GFLAGS), + GATE(PCLK_DDR_ROOT, "pclk_ddr_root", "clk_cpll_div10", 0, + RV1126B_CLKGATE_CON(7), 0, GFLAGS), + COMPOSITE(ACLK_SYSMEM, "aclk_sysmem", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(44), 3, 1, MFLAGS, 0, 3, DFLAGS, + RV1126B_CLKGATE_CON(7), 1, GFLAGS), + COMPOSITE_NODIV(ACLK_TOP_ROOT, "aclk_top_root", mux_600m_400m_200m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(44), 6, 2, MFLAGS, + RV1126B_CLKGATE_CON(7), 3, GFLAGS), + COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_400m_300m_200m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(44), 8, 2, MFLAGS, + RV1126B_CLKGATE_CON(7), 4, GFLAGS), + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(44), 10, 1, MFLAGS, + RV1126B_CLKGATE_CON(7), 5, GFLAGS), + GATE(PCLK_BUS_ROOT, "pclk_bus_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(7), 6, GFLAGS), + COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(45), 8, 2, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(7), 7, GFLAGS), + COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(47), 8, 2, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(7), 9, GFLAGS), + COMPOSITE(SCLK_2X_FSPI0, "sclk_2x_fspi0", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 8, DFLAGS, + RV1126B_CLKGATE_CON(7), 10, GFLAGS), + COMPOSITE(CLK_GMAC_PTP_REF_SRC, "clk_gmac_ptp_ref_src", mux_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(45), 10, 1, MFLAGS, 11, 5, DFLAGS, + RV1126B_CLKGATE_CON(7), 11, GFLAGS), + GATE(CLK_GMAC_125M, "clk_gmac_125m", "clk_cpll_div8", 0, + RV1126B_CLKGATE_CON(7), 12, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER_ROOT, "clk_timer_root", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(46), 11, 1, MFLAGS, + RV1126B_CLKGATE_CON(7), 13, GFLAGS), + COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(46), 14, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 2, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1126B_CLKGATE_CON(8), 5, GFLAGS), + COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_24m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(47), 12, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 6, GFLAGS), + COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_200m_24m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(47), 13, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE_NODIV(CLK_I2C_BUS_SRC, "clk_i2c_bus_src", mux_200m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 1, 1, MFLAGS, + RV1126B_CLKGATE_CON(8), 9, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 2, 2, MFLAGS, + RV1126B_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 4, 2, MFLAGS, + RV1126B_CLKGATE_CON(8), 11, GFLAGS), + GATE(BUSCLK_PMU_SRC, "busclk_pmu_src", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(8), 12, GFLAGS), + COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 8, 1, MFLAGS, + RV1126B_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 10, 1, MFLAGS, + RV1126B_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0, + RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS, + RV1126B_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS, + RV1126B_CLKGATE_CON(9), 4, GFLAGS), + COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS, + RV1126B_CLKGATE_CON(9), 5, GFLAGS), + COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL, + RV1126B_CLKSEL_CON(48), 12, 2, MFLAGS, + RV1126B_CLKGATE_CON(9), 6, GFLAGS), + GATE(HCLK_VCP_ROOT, "hclk_vcp_root", "clk_gpll_div8", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(9), 7, GFLAGS), + GATE(PCLK_VCP_ROOT, "pclk_vcp_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(9), 8, GFLAGS), + COMPOSITE(CLK_CORE_FEC_SRC, "clk_core_fec_src", mux_gpll_cpll_p, 0, + RV1126B_CLKSEL_CON(51), 3, 1, MFLAGS, 0, 3, DFLAGS, + RV1126B_CLKGATE_CON(9), 9, GFLAGS), + GATE(CLK_50M_GMAC_IOBUF_VI, "clk_50m_gmac_iobuf_vi", "clk_cpll_div20", 0, + RV1126B_CLKGATE_CON(9), 11, GFLAGS), + GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_cpll_div10", CLK_IS_CRITICAL, + RV1126B_CLKGATE_CON(15), 0, GFLAGS), + COMPOSITE(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", mux_600m_24m_p, 0, + RV1126B_CLKSEL_CON(67), 11, 1, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(15), 3, GFLAGS), + COMPOSITE(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", mux_600m_24m_p, 0, + RV1126B_CLKSEL_CON(67), 12, 1, MFLAGS, 6, 5, DFLAGS, + RV1126B_CLKGATE_CON(15), 4, GFLAGS), + COMPOSITE(CLK_MIPI2_OUT2IO, "clk_mipi2_out2io", mux_600m_24m_p, 0, + RV1126B_CLKSEL_CON(68), 11, 1, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(15), 5, GFLAGS), + COMPOSITE(CLK_MIPI3_OUT2IO, "clk_mipi3_out2io", mux_600m_24m_p, 0, + RV1126B_CLKSEL_CON(68), 12, 1, MFLAGS, 6, 5, DFLAGS, + RV1126B_CLKGATE_CON(15), 6, GFLAGS), + COMPOSITE(CLK_CIF_OUT2IO, "clk_cif_out2io", mux_600m_24m_p, 0, + RV1126B_CLKSEL_CON(69), 5, 1, MFLAGS, 0, 5, DFLAGS, + RV1126B_CLKGATE_CON(15), 7, GFLAGS), + COMPOSITE(CLK_MAC_OUT2IO, "clk_mac_out2io", mux_gpll_cpll_24m_p, 0, + RV1126B_CLKSEL_CON(69), 6, 2, MFLAGS, 8, 7, DFLAGS, + RV1126B_CLKGATE_CON(15), 8, GFLAGS), + COMPOSITE_NOMUX(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", "mclk_sai0", CLK_SET_RATE_PARENT, + RV1126B_CLKSEL_CON(70), 0, 4, DFLAGS, + RV1126B_CLKGATE_CON(15), 9, GFLAGS), + COMPOSITE_NOMUX(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", "mclk_sai1", CLK_SET_RATE_PARENT, + RV1126B_CLKSEL_CON(70), 5, 4, DFLAGS, + RV1126B_CLKGATE_CON(15), 10, GFLAGS), + COMPOSITE_NOMUX(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", "mclk_sai2", CLK_SET_RATE_PARENT, + RV1126B_CLKSEL_CON(70), 10, 4, DFLAGS, + RV1126B_CLKGATE_CON(15), 11, GFLAGS), + + /* pd _npu */ + MUX(ACLK_RKNN, "aclk_rknn", aclk_npu_root_p, CLK_SET_RATE_PARENT, + RV1126B_NPUCLKSEL_CON(0), 1, 1, MFLAGS), + + /* pd_vepu */ + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vepu_root", 0, + RV1126B_VEPUCLKGATE_CON(0), 7, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, + RV1126B_VEPUCLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_IOC_VCCIO3, "pclk_ioc_vccio3", "pclk_vepu_root", CLK_IS_CRITICAL, + RV1126B_VEPUCLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_SARADC0, "pclk_saradc0", "pclk_vepu_root", 0, + RV1126B_VEPUCLKGATE_CON(0), 10, GFLAGS), + MUX(CLK_SARADC0, "clk_saradc0", clk_saradc0_p, CLK_SET_RATE_PARENT, + RV1126B_VEPUCLKSEL_CON(0), 2, 1, MFLAGS), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_vepu_root", 0, + RV1126B_VEPUCLKGATE_CON(0), 12, GFLAGS), + GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0, + RV1126B_VEPUCLKGATE_CON(1), 1, GFLAGS), + GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0, + RV1126B_VEPUCLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, CLK_SET_RATE_PARENT, + RV1126B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS, + RV1126B_VEPUCLKGATE_CON(1), 3, GFLAGS), + + /* pd_vcp */ + GATE(HCLK_FEC, "hclk_fec", "hclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(1), 0, GFLAGS), + GATE(ACLK_FEC, "aclk_fec", "aclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_FEC, "clk_core_fec", clk_core_fec_p, CLK_SET_RATE_PARENT, + RV1126B_VCPCLKSEL_CON(0), 13, 1, MFLAGS, + RV1126B_VCPCLKGATE_CON(1), 2, GFLAGS), + GATE(HCLK_AVSP, "hclk_avsp", "hclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(1), 3, GFLAGS), + GATE(ACLK_AVSP, "aclk_avsp", "aclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(1), 4, GFLAGS), + GATE(HCLK_AISP, "hclk_aisp", "hclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(0), 11, GFLAGS), + GATE(ACLK_AISP, "aclk_aisp", "aclk_vcp_root", 0, + RV1126B_VCPCLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_AISP, "clk_core_aisp", clk_core_aisp_p, CLK_SET_RATE_PARENT, + RV1126B_VCPCLKSEL_CON(0), 15, 1, MFLAGS, + RV1126B_VCPCLKGATE_CON(0), 13, GFLAGS), + + /* pd_vi */ + MUX(CLK_CORE_ISP_ROOT, "clk_core_isp_root", clk_core_isp_root_p, CLK_SET_RATE_PARENT, + RV1126B_VICLKSEL_CON(0), 1, 1, MFLAGS), + GATE(PCLK_DSMC, "pclk_dsmc", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(0), 8, GFLAGS), + GATE(ACLK_DSMC, "aclk_dsmc", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(0), 9, GFLAGS), + GATE(HCLK_CAN0, "hclk_can0", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(0), 10, GFLAGS), + GATE(HCLK_CAN1, "hclk_can1", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(1), 0, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, + RV1126B_VICLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(1), 2, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, + RV1126B_VICLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(1), 4, GFLAGS), + GATE(DBCLK_GPIO5, "dbclk_gpio5", "xin24m", 0, + RV1126B_VICLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(1), 6, GFLAGS), + GATE(DBCLK_GPIO6, "dbclk_gpio6", "xin24m", 0, + RV1126B_VICLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(1), 8, GFLAGS), + GATE(DBCLK_GPIO7, "dbclk_gpio7", "xin24m", 0, + RV1126B_VICLKGATE_CON(1), 9, GFLAGS), + GATE(PCLK_IOC_VCCIO2, "pclk_ioc_vccio2", "pclk_vi_root", CLK_IS_CRITICAL, + RV1126B_VICLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_IOC_VCCIO4, "pclk_ioc_vccio4", "pclk_vi_root", CLK_IS_CRITICAL, + RV1126B_VICLKGATE_CON(1), 11, GFLAGS), + GATE(PCLK_IOC_VCCIO5, "pclk_ioc_vccio5", "pclk_vi_root", CLK_IS_CRITICAL, + RV1126B_VICLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_IOC_VCCIO6, "pclk_ioc_vccio6", "pclk_vi_root", CLK_IS_CRITICAL, + RV1126B_VICLKGATE_CON(1), 13, GFLAGS), + GATE(PCLK_IOC_VCCIO7, "pclk_ioc_vccio7", "pclk_vi_root", CLK_IS_CRITICAL, + RV1126B_VICLKGATE_CON(1), 14, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 0, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 1, GFLAGS), + GATE(CLK_CORE_ISP, "clk_core_isp", "clk_core_isp_root", 0, + RV1126B_VICLKGATE_CON(2), 2, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 3, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 4, GFLAGS), + GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap_root", 0, + RV1126B_VICLKGATE_CON(2), 5, GFLAGS), + GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp_root", 0, + RV1126B_VICLKGATE_CON(2), 6, GFLAGS), + GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 7, GFLAGS), + GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 8, GFLAGS), + GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_core_isp_root", 0, + RV1126B_VICLKGATE_CON(2), 9, GFLAGS), + GATE(HCLK_VPSL, "hclk_vpsl", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 10, GFLAGS), + GATE(ACLK_VPSL, "aclk_vpsl", "aclk_vi_root", 0, + RV1126B_VICLKGATE_CON(2), 11, GFLAGS), + GATE(CLK_CORE_VPSL, "clk_core_vpsl", "clk_core_isp_root", 0, + RV1126B_VICLKGATE_CON(2), 12, GFLAGS), + GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 0, GFLAGS), + GATE(DCLK_CSI2HOST0, "dclk_csi2host0", "dclk_vicap_root", 0, + RV1126B_VICLKGATE_CON(3), 1, GFLAGS), + GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 2, GFLAGS), + GATE(DCLK_CSI2HOST1, "dclk_csi2host1", "dclk_vicap_root", 0, + RV1126B_VICLKGATE_CON(3), 3, GFLAGS), + GATE(PCLK_CSI2HOST2, "pclk_csi2host2", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 4, GFLAGS), + GATE(DCLK_CSI2HOST2, "dclk_csi2host2", "dclk_vicap_root", 0, + RV1126B_VICLKGATE_CON(3), 5, GFLAGS), + GATE(PCLK_CSI2HOST3, "pclk_csi2host3", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 6, GFLAGS), + GATE(DCLK_CSI2HOST3, "dclk_csi2host3", "dclk_vicap_root", 0, + RV1126B_VICLKGATE_CON(3), 7, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 8, GFLAGS), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_root", 0, + RV1126B_VICLKGATE_CON(3), 9, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 10, GFLAGS), + MUX(CLK_GMAC_PTP_REF, "clk_gmac_ptp_ref", clk_gmac_ptp_ref_p, CLK_SET_RATE_PARENT, + RV1126B_VICLKSEL_CON(0), 14, 1, MFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 11, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 12, GFLAGS), + GATE(PCLK_MACPHY, "pclk_macphy", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(3), 13, GFLAGS), + GATE(PCLK_SARADC1, "pclk_saradc1", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(4), 0, GFLAGS), + MUX(CLK_SARADC1, "clk_saradc1", clk_saradc1_p, CLK_SET_RATE_PARENT, + RV1126B_VICLKSEL_CON(0), 2, 1, MFLAGS), + GATE(PCLK_SARADC2, "pclk_saradc2", "pclk_vi_root", 0, + RV1126B_VICLKGATE_CON(4), 2, GFLAGS), + MUX(CLK_SARADC2, "clk_saradc2", clk_saradc2_p, CLK_SET_RATE_PARENT, + RV1126B_VICLKSEL_CON(0), 3, 1, MFLAGS), + COMPOSITE_NODIV(CLK_MACPHY, "clk_macphy", clk_macphy_p, 0, + RV1126B_VICLKSEL_CON(1), 1, 1, MFLAGS, + RV1126B_VICLKGATE_CON(0), 12, GFLAGS), + + /* pd_vdo */ + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_root", 0, + RV1126B_VDOCLKGATE_CON(0), 7, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", "aclk_rkvdec_root", 0, + RV1126B_VDOCLKGATE_CON(0), 9, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(0), 10, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(0), 11, GFLAGS), + GATE(ACLK_OOC, "aclk_ooc", "aclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(0), 13, GFLAGS), + GATE(HCLK_OOC, "hclk_ooc", "hclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(0), 14, GFLAGS), + GATE(HCLK_RKJPEG, "hclk_rkjpeg", "hclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 3, GFLAGS), + GATE(ACLK_RKJPEG, "aclk_rkjpeg", "aclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 4, GFLAGS), + GATE(ACLK_RKMMU_DECOM, "aclk_rkmmu_decom", "aclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 5, GFLAGS), + GATE(HCLK_RKMMU_DECOM, "hclk_rkmmu_decom", "hclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 6, GFLAGS), + GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0, + RV1126B_VDOCLKGATE_CON(1), 8, GFLAGS), + GATE(ACLK_DECOM, "aclk_decom", "aclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 9, GFLAGS), + GATE(PCLK_DECOM, "pclk_decom", "pclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_vdo_root", 0, + RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS), + + /* pd_ddr */ + GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, + RV1126B_DDRCLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IS_CRITICAL, + RV1126B_DDRCLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0, + RV1126B_DDRCLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL, + RV1126B_DDRCLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, + RV1126B_DDRCLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_ddr_root", CLK_IS_CRITICAL, + RV1126B_DDRCLKGATE_CON(0), 9, GFLAGS), + + /* pd_pmu*/ + COMPOSITE_NODIV(CLK_RCOSC_SRC, "clk_rcosc_src", clk_rcosc_src_p, 0, + RV1126B_PMUCLKSEL_CON(1), 0, 3, MFLAGS, + RV1126B_PMUCLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NOGATE(BUSCLK_PMU_MUX, "busclk_pmu_mux", busclk_pmu_mux_p, 0, + RV1126B_PMUCLKSEL_CON(1), 3, 1, MFLAGS, 4, 2, DFLAGS), + GATE(BUSCLK_PMU_ROOT, "busclk_pmu_root", "busclk_pmu_mux", 0, + RV1126B_PMUCLKGATE_CON(0), 1, GFLAGS), + GATE(BUSCLK_PMU1_ROOT, "busclk_pmu1_root", "busclk_pmu_mux", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(3), 11, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(0), 6, GFLAGS), + MUX(0, "xin_rc_src", clk_xin_rc_div_p, 0, + RV1126B_PMUCLKSEL_CON(2), 0, 1, MFLAGS), + COMPOSITE_FRACMUX_NOGATE(CLK_XIN_RC_DIV, "clk_xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT, + RV1126B_PMUCLKSEL_CON(8), 0, + &rv1126b_rcdiv_pmu_fracmux), + GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0, + RV1126B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, + RV1126B_PMUCLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", mux_cpll_24m_p, CLK_IS_CRITICAL, + RV1126B_PMUCLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, + RV1126B_PMUCLKGATE_CON(0), 11, GFLAGS), + GATE(CLK_PMU_32K_HP_TIMER, "clk_pmu_32k_hp_timer", "clk_32k", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(0), 13, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(CLK_PWM1, "clk_pwm1", mux_24m_rcosc_buspmu_p, 0, + RV1126B_PMUCLKSEL_CON(2), 8, 2, MFLAGS, 6, 2, DFLAGS, + RV1126B_PMUCLKGATE_CON(1), 1, GFLAGS), + GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, + RV1126B_PMUCLKGATE_CON(1), 2, GFLAGS), + GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_32k", 0, + RV1126B_PMUCLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(1), 6, GFLAGS), + COMPOSITE(CLK_I2C2, "clk_i2c2", mux_24m_rcosc_buspmu_p, 0, + RV1126B_PMUCLKSEL_CON(2), 14, 2, MFLAGS, 12, 2, DFLAGS, + RV1126B_PMUCLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NODIV(SCLK_UART0, "sclk_uart0", sclk_uart0_p, CLK_SET_RATE_PARENT, + RV1126B_PMUCLKSEL_CON(3), 0, 2, MFLAGS, + RV1126B_PMUCLKGATE_CON(1), 11, GFLAGS), + GATE(PCLK_RCOSC_CTRL, "pclk_rcosc_ctrl", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(2), 0, GFLAGS), + COMPOSITE_NODIV(CLK_OSC_RCOSC_CTRL, "clk_osc_rcosc_ctrl", clk_osc_rcosc_ctrl_p, CLK_IS_CRITICAL, + RV1126B_PMUCLKSEL_CON(3), 2, 1, MFLAGS, + RV1126B_PMUCLKGATE_CON(2), 1, GFLAGS), + GATE(CLK_REF_RCOSC_CTRL, "clk_ref_rcosc_ctrl", "xin24m", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(2), 2, GFLAGS), + GATE(PCLK_IOC_PMUIO0, "pclk_ioc_pmuio0", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(2), 3, GFLAGS), + GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, + RV1126B_PMUCLKGATE_CON(2), 6, GFLAGS), + GATE(CLK_PREROLL, "clk_preroll", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(2), 7, GFLAGS), + GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0, + RV1126B_PMUCLKGATE_CON(2), 8, GFLAGS), + GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMUCLKGATE_CON(2), 9, GFLAGS), + GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(3), 0, GFLAGS), + COMPOSITE_NODIV(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", mux_24m_rcosc_buspmu_32k_p, 0, + RV1126B_PMUCLKSEL_CON(3), 6, 2, MFLAGS, + RV1126B_PMUCLKGATE_CON(3), 1, GFLAGS), + GATE(CLK_LPMCU, "clk_lpmcu", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(3), 2, GFLAGS), + GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0, + RV1126B_PMUCLKGATE_CON(3), 3, GFLAGS), + GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "busclk_pmu_root", 0, + RV1126B_PMUCLKGATE_CON(3), 4, GFLAGS), + + /* pd_pmu1 */ + GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "busclk_pmu_root", 0, + RV1126B_PMU1CLKGATE_CON(0), 0, GFLAGS), + GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "busclk_pmu_root", 0, + RV1126B_PMU1CLKGATE_CON(0), 1, GFLAGS), + GATE(HCLK_FSPI1, "hclk_fspi1", "busclk_pmu_root", 0, + RV1126B_PMU1CLKGATE_CON(0), 2, GFLAGS), + GATE(HCLK_XIP_FSPI1, "hclk_xip_fspi1", "busclk_pmu_root", 0, + RV1126B_PMU1CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(SCLK_1X_FSPI1, "sclk_1x_fspi1", mux_24m_rcosc_buspmu_p, 0, + RV1126B_PMU1CLKSEL_CON(0), 0, 2, MFLAGS, 2, 3, DFLAGS, + RV1126B_PMU1CLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_IOC_PMUIO1, "pclk_ioc_pmuio1", "busclk_pmu_root", CLK_IS_CRITICAL, + RV1126B_PMU1CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_AUDIO_ADC_PMU, "pclk_audio_adc_pmu", "busclk_pmu_root", 0, + RV1126B_PMU1CLKGATE_CON(0), 8, GFLAGS), + + COMPOSITE(MCLK_LPSAI, "mclk_lpsai", mux_24m_rcosc_buspmu_p, 0, + RV1126B_PMU1CLKSEL_CON(0), 6, 2, MFLAGS, 8, 5, DFLAGS, + RV1126B_PMU1CLKGATE_CON(1), 3, GFLAGS), + GATE(MCLK_AUDIO_ADC_PMU, "mclk_audio_adc_pmu", "mclk_lpsai", CLK_IS_CRITICAL, + RV1126B_PMU1CLKGATE_CON(0), 9, GFLAGS), + FACTOR(MCLK_AUDIO_ADC_DIV4_PMU, "mclk_audio_adc_div4_pmu", "mclk_audio_adc_pmu", 0, 1, 4), + + /* pd_bus */ + GATE(ACLK_GIC400, "aclk_gic400", "hclk_bus_root", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(0), 10, GFLAGS), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "tclk_wdt_ns_src", 0, + RV1126B_BUSCLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 0, GFLAGS), + GATE(HCLK_CACHE, "hclk_cache", "aclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 4, GFLAGS), + GATE(CLK_HPMCU, "clk_hpmcu", "aclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 5, GFLAGS), + GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_RKDMA, "pclk_rkdma", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 11, GFLAGS), + GATE(ACLK_RKDMA, "aclk_rkdma", "aclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 0, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 1, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 2, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 3, GFLAGS), + GATE(CLK_CORE_RGA, "clk_core_rga", "clk_core_rga_src", 0, + RV1126B_BUSCLKGATE_CON(2), 4, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 5, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0, "clk_timer0", clk_timer0_parents_p, 0, + RV1126B_BUSCLKSEL_CON(2), 0, 2, MFLAGS, + RV1126B_BUSCLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER1, "clk_timer1", clk_timer1_parents_p, 0, + RV1126B_BUSCLKSEL_CON(2), 2, 2, MFLAGS, + RV1126B_BUSCLKGATE_CON(2), 7, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER2, "clk_timer2", clk_timer2_parents_p, 0, + RV1126B_BUSCLKSEL_CON(2), 4, 2, MFLAGS, + RV1126B_BUSCLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER3, "clk_timer3", clk_timer3_parents_p, 0, + RV1126B_BUSCLKSEL_CON(2), 6, 2, MFLAGS, + RV1126B_BUSCLKGATE_CON(2), 9, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0, + RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS, + RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS), + GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS), + GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_rkrng_s_ns", 0, + RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 0, GFLAGS), + GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_bus_src", 0, + RV1126B_BUSCLKGATE_CON(3), 1, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 2, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_bus_src", 0, + RV1126B_BUSCLKGATE_CON(3), 3, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 4, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_bus_src", 0, + RV1126B_BUSCLKGATE_CON(3), 5, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 6, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_bus_src", 0, + RV1126B_BUSCLKGATE_CON(3), 7, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 8, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c_bus_src", 0, + RV1126B_BUSCLKGATE_CON(3), 9, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 10, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(3), 12, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 0, GFLAGS), + GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 1, GFLAGS), + GATE(CLK_RC_PWM0, "clk_rc_pwm0", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 2, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 3, GFLAGS), + GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 4, GFLAGS), + GATE(CLK_RC_PWM2, "clk_rc_pwm2", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 5, GFLAGS), + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 6, GFLAGS), + GATE(CLK_OSC_PWM3, "clk_osc_pwm3", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 7, GFLAGS), + GATE(CLK_RC_PWM3, "clk_rc_pwm3", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(4), 8, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 9, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 10, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 11, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 12, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 13, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 14, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(4), 15, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(5), 0, GFLAGS), + GATE(CLK_TSADC, "clk_tsadc", "xin24m", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(5), 1, GFLAGS), + GATE(HCLK_SAI0, "hclk_sai0", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 2, GFLAGS), + GATE(HCLK_SAI1, "hclk_sai1", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 4, GFLAGS), + GATE(HCLK_SAI2, "hclk_sai2", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 6, GFLAGS), + GATE(HCLK_RKDSM, "hclk_rkdsm", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 8, GFLAGS), + GATE(MCLK_RKDSM, "mclk_rkdsm", "mclk_sai2", 0, + RV1126B_BUSCLKGATE_CON(5), 9, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 10, GFLAGS), + GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 11, GFLAGS), + GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 12, GFLAGS), + GATE(PCLK_AUDIO_ADC_BUS, "pclk_audio_adc_bus", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(5), 13, GFLAGS), + GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0, + RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS), + FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4), + GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS), + GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(6), 2, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RV1126B_BUSCLKGATE_CON(6), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, + RV1126B_BUSCLKSEL_CON(2), 12, 3, DFLAGS, + RV1126B_BUSCLKGATE_CON(6), 4, GFLAGS), + GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_bus_root", 0, + RV1126B_BUSCLKGATE_CON(6), 6, GFLAGS), + GATE(CLK_TSADC_PHYCTRL, "clk_tsadc_phyctrl", "xin24m", CLK_IS_CRITICAL, + RV1126B_BUSCLKGATE_CON(6), 8, GFLAGS), + MUX(LRCK_SRC_ASRC0, "lrck_src_asrc0", lrck_src_asrc_p, 0, + RV1126B_BUSCLKSEL_CON(3), 0, 3, MFLAGS), + MUX(LRCK_DST_ASRC0, "lrck_dst_asrc0", lrck_src_asrc_p, 0, + RV1126B_BUSCLKSEL_CON(3), 4, 3, MFLAGS), + MUX(LRCK_SRC_ASRC1, "lrck_src_asrc1", lrck_src_asrc_p, 0, + RV1126B_BUSCLKSEL_CON(3), 8, 3, MFLAGS), + MUX(LRCK_DST_ASRC1, "lrck_dst_asrc1", lrck_src_asrc_p, 0, + RV1126B_BUSCLKSEL_CON(3), 12, 3, MFLAGS), + GATE(ACLK_NSRKCE, "aclk_nsrkce", "aclk_rkce_src", 0, + RV1126B_BUSCLKGATE_CON(2), 12, GFLAGS), + GATE(CLK_PKA_NSRKCE, "clk_pka_nsrkce", "clk_pka_rkce_src", 0, + RV1126B_BUSCLKGATE_CON(2), 13, GFLAGS), + + /* pd_peri */ + DIV(PCLK_RTC_ROOT, "pclk_rtc_root", "pclk_peri_root", 0, + RV1126B_PERICLKSEL_CON(0), 0, 2, DFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(0), 5, GFLAGS), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, + RV1126B_PERICLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_IOC_VCCIO1, "pclk_ioc_vccio1", "pclk_peri_root", CLK_IS_CRITICAL, + RV1126B_PERICLKGATE_CON(0), 7, GFLAGS), + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, + RV1126B_PERICLKGATE_CON(0), 9, GFLAGS), + GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, + RV1126B_PERICLKGATE_CON(0), 10, GFLAGS), + GATE(HCLK_USB2HOST, "hclk_usb2host", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(0), 11, GFLAGS), + GATE(HCLK_ARB_USB2HOST, "hclk_arb_usb2host", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(0), 12, GFLAGS), + GATE(PCLK_RTC_TEST, "pclk_rtc_test", "pclk_rtc_root", 0, + RV1126B_PERICLKGATE_CON(0), 13, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(1), 0, GFLAGS), + GATE(HCLK_FSPI0, "hclk_fspi0", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(1), 1, GFLAGS), + GATE(HCLK_XIP_FSPI0, "hclk_xip_fspi0", "aclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(1), 8, GFLAGS), + GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri_root", 0, + RV1126B_PERICLKGATE_CON(1), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_PIPEPHY_CPLL_SRC, "clk_ref_pipephy_cpll_src", "cpll", 0, + RV1126B_PERICLKSEL_CON(1), 0, 6, DFLAGS, + RV1126B_PERICLKGATE_CON(1), 14, GFLAGS), + MUX(CLK_REF_PIPEPHY, "clk_ref_pipephy", clk_ref_pipephy_p, 0, + RV1126B_PERICLKSEL_CON(1), 12, 1, MFLAGS), +}; + +static struct rockchip_clk_branch rv1126b_armclk __initdata = + MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + RV1126B_CORECLKSEL_CON(0), 1, 1, MFLAGS); + +static void __init rv1126b_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + void __iomem *reg_base; + unsigned long clk_nr_clks; + + clk_nr_clks = rockchip_clk_find_max_clk_id(rv1126b_clk_branches, + ARRAY_SIZE(rv1126b_clk_branches)) + 1; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rv1126b_pll_clks, + ARRAY_SIZE(rv1126b_pll_clks), + RV1126B_GRF_SOC_STATUS0); + + rockchip_clk_register_branches(ctx, rv1126b_clk_branches, + ARRAY_SIZE(rv1126b_clk_branches)); + + rockchip_clk_register_armclk_multi_pll(ctx, &rv1126b_armclk, + rv1126b_cpuclk_rates, + ARRAY_SIZE(rv1126b_cpuclk_rates)); + + rv1126b_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RV1126B_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); + + /* pvtpll src init */ + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0)); + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0)); + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0)); + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0)); + writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0)); +} + +CLK_OF_DECLARE(rv1126b_cru, "rockchip,rv1126b-cru", rv1126b_clk_init); + +struct clk_rv1126b_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rv1126b_inits clk_rv1126b_init = { + .inits = rv1126b_clk_init, +}; + +static const struct of_device_id clk_rv1126b_match_table[] = { + { + .compatible = "rockchip,rv1126b-cru", + .data = &clk_rv1126b_init, + }, + { } +}; + +static int clk_rv1126b_probe(struct platform_device *pdev) +{ + const struct clk_rv1126b_inits *init_data; + struct device *dev = &pdev->dev; + + init_data = device_get_match_data(dev); + if (!init_data) + return -EINVAL; + + if (init_data->inits) + init_data->inits(dev->of_node); + + return 0; +} + +static struct platform_driver clk_rv1126b_driver = { + .probe = clk_rv1126b_probe, + .driver = { + .name = "clk-rv1126b", + .of_match_table = clk_rv1126b_match_table, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_rv1126b_driver, clk_rv1126b_probe); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 23653a942403..87f09320b942 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -99,6 +99,73 @@ struct clk; #define RV1126_EMMC_CON0 0x450 #define RV1126_EMMC_CON1 0x454 +#define RV1126B_TOPCRU_BASE 0x0 +#define RV1126B_BUSCRU_BASE 0x10000 +#define RV1126B_PERICRU_BASE 0x20000 +#define RV1126B_CORECRU_BASE 0x30000 +#define RV1126B_PMUCRU_BASE 0x40000 +#define RV1126B_PMU1CRU_BASE 0x50000 +#define RV1126B_DDRCRU_BASE 0x60000 +#define RV1126B_SUBDDRCRU_BASE 0x68000 +#define RV1126B_VICRU_BASE 0x70000 +#define RV1126B_VEPUCRU_BASE 0x80000 +#define RV1126B_NPUCRU_BASE 0x90000 +#define RV1126B_VDOCRU_BASE 0xA0000 +#define RV1126B_VCPCRU_BASE 0xB0000 + +#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE) +#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE) +#define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE) +#define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE) +#define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE) +#define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE) +#define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE) +#define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE) +#define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE) +#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE) +#define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE) +#define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE) +#define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE) +#define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE) +#define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE) +#define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE) +#define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE) +#define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE) +#define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE) +#define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE) +#define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE) +#define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE) +#define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE) +#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE) +#define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE) +#define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE) +#define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE) +#define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE) +#define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE) +#define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE) +#define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE) +#define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE) +#define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE) +#define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE) +#define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE) +#define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE) +#define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE) +#define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE) +#define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE) + #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) @@ -1261,6 +1328,7 @@ static inline void rockchip_register_softrst(struct device_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } +void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base); void rk3528_rst_init(struct device_node *np, void __iomem *reg_base); void rk3562_rst_init(struct device_node *np, void __iomem *reg_base); void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); diff --git a/drivers/clk/rockchip/rst-rv1126b.c b/drivers/clk/rockchip/rst-rv1126b.c new file mode 100644 index 000000000000..251b1875bd0b --- /dev/null +++ b/drivers/clk/rockchip/rst-rv1126b.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <dt-bindings/reset/rockchip,rv1126b-cru.h> +#include "clk.h" + +/* 0x20000000 + 0x0A00 */ +#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit) +/* 0x20010000 + 0x0A00 */ +#define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit) +/* 0x20020000 + 0x0A00 */ +#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit) +/* 0x20030000 + 0x0A00 */ +#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit) +/* 0x20040000 + 0x0A00 */ +#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit) +/* 0x20050000 + 0x0A00 */ +#define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit) +/* 0x20060000 + 0x0A00 */ +#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit) +/* 0x20068000 + 0x0A00 */ +#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit) +/* 0x20070000 + 0x0A00 */ +#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit) +/* 0x20080000 + 0x0A00 */ +#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit) +/* 0x20090000 + 0x0A00 */ +#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x90000 * 4 + reg * 16 + bit) +/* 0x200A0000 + 0x0A00 */ +#define VDOCRU_RESET_OFFSET(id, reg, bit) [id] = (0xA0000 * 4 + reg * 16 + bit) +/* 0x200B0000 + 0x0A00 */ +#define VCPCRU_RESET_OFFSET(id, reg, bit) [id] = (0xB0000 * 4 + reg * 16 + bit) + +/* =================mapping table for reset ID to register offset================== */ +static const int rv1126b_register_offset[] = { + /* TOPCRU-->SOFTRST_CON00 */ + + /* TOPCRU-->SOFTRST_CON15 */ + TOPCRU_RESET_OFFSET(SRST_PRESETN_CRU, 15, 1), + TOPCRU_RESET_OFFSET(SRST_PRESETN_CRU_BIU, 15, 2), + + /* BUSCRU-->SOFTRST_CON00 */ + BUSCRU_RESET_OFFSET(SRST_ARESETN_TOP_BIU, 0, 0), + BUSCRU_RESET_OFFSET(SRST_ARESETN_RKCE_BIU, 0, 1), + BUSCRU_RESET_OFFSET(SRST_ARESETN_BUS_BIU, 0, 2), + BUSCRU_RESET_OFFSET(SRST_HRESETN_BUS_BIU, 0, 3), + BUSCRU_RESET_OFFSET(SRST_PRESETN_BUS_BIU, 0, 4), + BUSCRU_RESET_OFFSET(SRST_PRESETN_CRU_BUS, 0, 5), + BUSCRU_RESET_OFFSET(SRST_PRESETN_SYS_GRF, 0, 6), + BUSCRU_RESET_OFFSET(SRST_HRESETN_BOOTROM, 0, 7), + BUSCRU_RESET_OFFSET(SRST_ARESETN_GIC400, 0, 8), + BUSCRU_RESET_OFFSET(SRST_ARESETN_SPINLOCK, 0, 9), + BUSCRU_RESET_OFFSET(SRST_PRESETN_WDT_NS, 0, 10), + BUSCRU_RESET_OFFSET(SRST_TRESETN_WDT_NS, 0, 11), + + /* BUSCRU-->SOFTRST_CON01 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_WDT_HPMCU, 1, 0), + BUSCRU_RESET_OFFSET(SRST_TRESETN_WDT_HPMCU, 1, 1), + BUSCRU_RESET_OFFSET(SRST_HRESETN_CACHE, 1, 2), + BUSCRU_RESET_OFFSET(SRST_PRESETN_HPMCU_MAILBOX, 1, 3), + BUSCRU_RESET_OFFSET(SRST_PRESETN_HPMCU_INTMUX, 1, 4), + BUSCRU_RESET_OFFSET(SRST_RESETN_HPMCU_FULL_CLUSTER, 1, 5), + BUSCRU_RESET_OFFSET(SRST_RESETN_HPMCU_PWUP, 1, 6), + BUSCRU_RESET_OFFSET(SRST_RESETN_HPMCU_ONLY_CORE, 1, 7), + BUSCRU_RESET_OFFSET(SRST_TRESETN_HPMCU_JTAG, 1, 8), + BUSCRU_RESET_OFFSET(SRST_PRESETN_RKDMA, 1, 11), + BUSCRU_RESET_OFFSET(SRST_ARESETN_RKDMA, 1, 12), + + /* BUSCRU-->SOFTRST_CON02 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_DCF, 2, 0), + BUSCRU_RESET_OFFSET(SRST_ARESETN_DCF, 2, 1), + BUSCRU_RESET_OFFSET(SRST_HRESETN_RGA, 2, 2), + BUSCRU_RESET_OFFSET(SRST_ARESETN_RGA, 2, 3), + BUSCRU_RESET_OFFSET(SRST_RESETN_CORE_RGA, 2, 4), + BUSCRU_RESET_OFFSET(SRST_PRESETN_TIMER, 2, 5), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER0, 2, 6), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER1, 2, 7), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER2, 2, 8), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER3, 2, 9), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER4, 2, 10), + BUSCRU_RESET_OFFSET(SRST_RESETN_TIMER5, 2, 11), + BUSCRU_RESET_OFFSET(SRST_ARESETN_RKCE, 2, 12), + BUSCRU_RESET_OFFSET(SRST_RESETN_PKA_RKCE, 2, 13), + BUSCRU_RESET_OFFSET(SRST_HRESETN_RKRNG_S, 2, 14), + BUSCRU_RESET_OFFSET(SRST_HRESETN_RKRNG_NS, 2, 15), + + /* BUSCRU-->SOFTRST_CON03 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_I2C0, 3, 0), + BUSCRU_RESET_OFFSET(SRST_RESETN_I2C0, 3, 1), + BUSCRU_RESET_OFFSET(SRST_PRESETN_I2C1, 3, 2), + BUSCRU_RESET_OFFSET(SRST_RESETN_I2C1, 3, 3), + BUSCRU_RESET_OFFSET(SRST_PRESETN_I2C3, 3, 4), + BUSCRU_RESET_OFFSET(SRST_RESETN_I2C3, 3, 5), + BUSCRU_RESET_OFFSET(SRST_PRESETN_I2C4, 3, 6), + BUSCRU_RESET_OFFSET(SRST_RESETN_I2C4, 3, 7), + BUSCRU_RESET_OFFSET(SRST_PRESETN_I2C5, 3, 8), + BUSCRU_RESET_OFFSET(SRST_RESETN_I2C5, 3, 9), + BUSCRU_RESET_OFFSET(SRST_PRESETN_SPI0, 3, 10), + BUSCRU_RESET_OFFSET(SRST_RESETN_SPI0, 3, 11), + BUSCRU_RESET_OFFSET(SRST_PRESETN_SPI1, 3, 12), + BUSCRU_RESET_OFFSET(SRST_RESETN_SPI1, 3, 13), + + /* BUSCRU-->SOFTRST_CON04 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_PWM0, 4, 0), + BUSCRU_RESET_OFFSET(SRST_RESETN_PWM0, 4, 1), + BUSCRU_RESET_OFFSET(SRST_PRESETN_PWM2, 4, 4), + BUSCRU_RESET_OFFSET(SRST_RESETN_PWM2, 4, 5), + BUSCRU_RESET_OFFSET(SRST_PRESETN_PWM3, 4, 8), + BUSCRU_RESET_OFFSET(SRST_RESETN_PWM3, 4, 9), + + /* BUSCRU-->SOFTRST_CON05 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART1, 5, 0), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART1, 5, 1), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART2, 5, 2), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART2, 5, 3), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART3, 5, 4), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART3, 5, 5), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART4, 5, 6), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART4, 5, 7), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART5, 5, 8), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART5, 5, 9), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART6, 5, 10), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART6, 5, 11), + BUSCRU_RESET_OFFSET(SRST_PRESETN_UART7, 5, 12), + BUSCRU_RESET_OFFSET(SRST_SRESETN_UART7, 5, 13), + + /* BUSCRU-->SOFTRST_CON06 */ + BUSCRU_RESET_OFFSET(SRST_PRESETN_TSADC, 6, 0), + BUSCRU_RESET_OFFSET(SRST_RESETN_TSADC, 6, 1), + BUSCRU_RESET_OFFSET(SRST_HRESETN_SAI0, 6, 2), + BUSCRU_RESET_OFFSET(SRST_MRESETN_SAI0, 6, 3), + BUSCRU_RESET_OFFSET(SRST_HRESETN_SAI1, 6, 4), + BUSCRU_RESET_OFFSET(SRST_MRESETN_SAI1, 6, 5), + BUSCRU_RESET_OFFSET(SRST_HRESETN_SAI2, 6, 6), + BUSCRU_RESET_OFFSET(SRST_MRESETN_SAI2, 6, 7), + BUSCRU_RESET_OFFSET(SRST_HRESETN_RKDSM, 6, 8), + BUSCRU_RESET_OFFSET(SRST_MRESETN_RKDSM, 6, 9), + BUSCRU_RESET_OFFSET(SRST_HRESETN_PDM, 6, 10), + BUSCRU_RESET_OFFSET(SRST_MRESETN_PDM, 6, 11), + BUSCRU_RESET_OFFSET(SRST_RESETN_PDM, 6, 12), + + /* BUSCRU-->SOFTRST_CON07 */ + BUSCRU_RESET_OFFSET(SRST_HRESETN_ASRC0, 7, 0), + BUSCRU_RESET_OFFSET(SRST_RESETN_ASRC0, 7, 1), + BUSCRU_RESET_OFFSET(SRST_HRESETN_ASRC1, 7, 2), + BUSCRU_RESET_OFFSET(SRST_RESETN_ASRC1, 7, 3), + BUSCRU_RESET_OFFSET(SRST_PRESETN_AUDIO_ADC_BUS, 7, 4), + BUSCRU_RESET_OFFSET(SRST_MRESETN_AUDIO_ADC_BUS, 7, 5), + BUSCRU_RESET_OFFSET(SRST_PRESETN_RKCE, 7, 6), + BUSCRU_RESET_OFFSET(SRST_HRESETN_NS_RKCE, 7, 7), + BUSCRU_RESET_OFFSET(SRST_PRESETN_OTPC_NS, 7, 8), + BUSCRU_RESET_OFFSET(SRST_RESETN_SBPI_OTPC_NS, 7, 9), + BUSCRU_RESET_OFFSET(SRST_RESETN_USER_OTPC_NS, 7, 10), + BUSCRU_RESET_OFFSET(SRST_RESETN_OTPC_ARB, 7, 11), + BUSCRU_RESET_OFFSET(SRST_PRESETN_OTP_MASK, 7, 12), + + /* PERICRU-->SOFTRST_CON00 */ + PERICRU_RESET_OFFSET(SRST_ARESETN_PERI_BIU, 0, 0), + PERICRU_RESET_OFFSET(SRST_PRESETN_PERI_BIU, 0, 1), + PERICRU_RESET_OFFSET(SRST_PRESETN_RTC_BIU, 0, 2), + PERICRU_RESET_OFFSET(SRST_PRESETN_CRU_PERI, 0, 3), + PERICRU_RESET_OFFSET(SRST_PRESETN_PERI_GRF, 0, 4), + PERICRU_RESET_OFFSET(SRST_PRESETN_GPIO1, 0, 5), + PERICRU_RESET_OFFSET(SRST_DBRESETN_GPIO1, 0, 6), + PERICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO1, 0, 7), + PERICRU_RESET_OFFSET(SRST_ARESETN_USB3OTG, 0, 8), + PERICRU_RESET_OFFSET(SRST_HRESETN_USB2HOST, 0, 11), + PERICRU_RESET_OFFSET(SRST_HRESETN_ARB_USB2HOST, 0, 12), + PERICRU_RESET_OFFSET(SRST_PRESETN_RTC_TEST, 0, 13), + + /* PERICRU-->SOFTRST_CON01 */ + PERICRU_RESET_OFFSET(SRST_HRESETN_EMMC, 1, 0), + PERICRU_RESET_OFFSET(SRST_HRESETN_FSPI0, 1, 1), + PERICRU_RESET_OFFSET(SRST_HRESETN_XIP_FSPI0, 1, 2), + PERICRU_RESET_OFFSET(SRST_SRESETN_2X_FSPI0, 1, 3), + PERICRU_RESET_OFFSET(SRST_RESETN_UTMI_USB2HOST, 1, 5), + PERICRU_RESET_OFFSET(SRST_RESETN_REF_PIPEPHY, 1, 7), + PERICRU_RESET_OFFSET(SRST_PRESETN_PIPEPHY, 1, 8), + PERICRU_RESET_OFFSET(SRST_PRESETN_PIPEPHY_GRF, 1, 9), + PERICRU_RESET_OFFSET(SRST_PRESETN_USB2PHY, 1, 10), + PERICRU_RESET_OFFSET(SRST_RESETN_POR_USB2PHY, 1, 11), + PERICRU_RESET_OFFSET(SRST_RESETN_OTG_USB2PHY, 1, 12), + PERICRU_RESET_OFFSET(SRST_RESETN_HOST_USB2PHY, 1, 13), + + /* CORECRU-->SOFTRST_CON00 */ + CORECRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_CORE, 0, 0), + CORECRU_RESET_OFFSET(SRST_NCOREPORESET0, 0, 1), + CORECRU_RESET_OFFSET(SRST_NCORESET0, 0, 2), + CORECRU_RESET_OFFSET(SRST_NCOREPORESET1, 0, 3), + CORECRU_RESET_OFFSET(SRST_NCORESET1, 0, 4), + CORECRU_RESET_OFFSET(SRST_NCOREPORESET2, 0, 5), + CORECRU_RESET_OFFSET(SRST_NCORESET2, 0, 6), + CORECRU_RESET_OFFSET(SRST_NCOREPORESET3, 0, 7), + CORECRU_RESET_OFFSET(SRST_NCORESET3, 0, 8), + CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 9), + CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 10), + + /* CORECRU-->SOFTRST_CON01 */ + CORECRU_RESET_OFFSET(SRST_ARESETN_CORE_BIU, 1, 0), + CORECRU_RESET_OFFSET(SRST_PRESETN_CORE_BIU, 1, 1), + CORECRU_RESET_OFFSET(SRST_HRESETN_CORE_BIU, 1, 2), + CORECRU_RESET_OFFSET(SRST_PRESETN_DBG, 1, 3), + CORECRU_RESET_OFFSET(SRST_POTRESETN_DBG, 1, 4), + CORECRU_RESET_OFFSET(SRST_NTRESETN_DBG, 1, 5), + CORECRU_RESET_OFFSET(SRST_PRESETN_CORE_PVTPLL, 1, 6), + CORECRU_RESET_OFFSET(SRST_PRESETN_CRU_CORE, 1, 7), + CORECRU_RESET_OFFSET(SRST_PRESETN_CORE_GRF, 1, 8), + CORECRU_RESET_OFFSET(SRST_PRESETN_DFT2APB, 1, 10), + + /* PMUCRU-->SOFTRST_CON00 */ + PMUCRU_RESET_OFFSET(SRST_HRESETN_PMU_BIU, 0, 0), + PMUCRU_RESET_OFFSET(SRST_PRESETN_PMU_GPIO0, 0, 7), + PMUCRU_RESET_OFFSET(SRST_DBRESETN_PMU_GPIO0, 0, 8), + PMUCRU_RESET_OFFSET(SRST_PRESETN_PMU_HP_TIMER, 0, 10), + PMUCRU_RESET_OFFSET(SRST_RESETN_PMU_HP_TIMER, 0, 11), + PMUCRU_RESET_OFFSET(SRST_RESETN_PMU_32K_HP_TIMER, 0, 12), + + /* PMUCRU-->SOFTRST_CON01 */ + PMUCRU_RESET_OFFSET(SRST_PRESETN_PWM1, 1, 0), + PMUCRU_RESET_OFFSET(SRST_RESETN_PWM1, 1, 1), + PMUCRU_RESET_OFFSET(SRST_PRESETN_I2C2, 1, 2), + PMUCRU_RESET_OFFSET(SRST_RESETN_I2C2, 1, 3), + PMUCRU_RESET_OFFSET(SRST_PRESETN_UART0, 1, 4), + PMUCRU_RESET_OFFSET(SRST_SRESETN_UART0, 1, 5), + + /* PMUCRU-->SOFTRST_CON02 */ + PMUCRU_RESET_OFFSET(SRST_PRESETN_RCOSC_CTRL, 2, 0), + PMUCRU_RESET_OFFSET(SRST_RESETN_REF_RCOSC_CTRL, 2, 2), + PMUCRU_RESET_OFFSET(SRST_PRESETN_IOC_PMUIO0, 2, 3), + PMUCRU_RESET_OFFSET(SRST_PRESETN_CRU_PMU, 2, 4), + PMUCRU_RESET_OFFSET(SRST_PRESETN_PMU_GRF, 2, 5), + PMUCRU_RESET_OFFSET(SRST_RESETN_PREROLL, 2, 7), + PMUCRU_RESET_OFFSET(SRST_RESETN_PREROLL_32K, 2, 8), + PMUCRU_RESET_OFFSET(SRST_HRESETN_PMU_SRAM, 2, 9), + + /* PMUCRU-->SOFTRST_CON03 */ + PMUCRU_RESET_OFFSET(SRST_PRESETN_WDT_LPMCU, 3, 0), + PMUCRU_RESET_OFFSET(SRST_TRESETN_WDT_LPMCU, 3, 1), + PMUCRU_RESET_OFFSET(SRST_RESETN_LPMCU_FULL_CLUSTER, 3, 2), + PMUCRU_RESET_OFFSET(SRST_RESETN_LPMCU_PWUP, 3, 3), + PMUCRU_RESET_OFFSET(SRST_RESETN_LPMCU_ONLY_CORE, 3, 4), + PMUCRU_RESET_OFFSET(SRST_TRESETN_LPMCU_JTAG, 3, 5), + PMUCRU_RESET_OFFSET(SRST_PRESETN_LPMCU_MAILBOX, 3, 6), + + /* PMU1CRU-->SOFTRST_CON00 */ + PMU1CRU_RESET_OFFSET(SRST_PRESETN_SPI2AHB, 0, 0), + PMU1CRU_RESET_OFFSET(SRST_HRESETN_SPI2AHB, 0, 1), + PMU1CRU_RESET_OFFSET(SRST_HRESETN_FSPI1, 0, 2), + PMU1CRU_RESET_OFFSET(SRST_HRESETN_XIP_FSPI1, 0, 3), + PMU1CRU_RESET_OFFSET(SRST_SRESETN_1X_FSPI1, 0, 4), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_IOC_PMUIO1, 0, 5), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_CRU_PMU1, 0, 6), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AUDIO_ADC_PMU, 0, 7), + PMU1CRU_RESET_OFFSET(SRST_MRESETN_AUDIO_ADC_PMU, 0, 8), + PMU1CRU_RESET_OFFSET(SRST_HRESETN_PMU1_BIU, 0, 9), + + /* PMU1CRU-->SOFTRST_CON01 */ + PMU1CRU_RESET_OFFSET(SRST_PRESETN_LPDMA, 1, 0), + PMU1CRU_RESET_OFFSET(SRST_ARESETN_LPDMA, 1, 1), + PMU1CRU_RESET_OFFSET(SRST_HRESETN_LPSAI, 1, 2), + PMU1CRU_RESET_OFFSET(SRST_MRESETN_LPSAI, 1, 3), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AOA_TDD, 1, 4), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AOA_FE, 1, 5), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AOA_AAD, 1, 6), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AOA_APB, 1, 7), + PMU1CRU_RESET_OFFSET(SRST_PRESETN_AOA_SRAM, 1, 8), + + /* DDRCRU-->SOFTRST_CON00 */ + DDRCRU_RESET_OFFSET(SRST_PRESETN_DDR_BIU, 0, 1), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DDRC, 0, 2), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DDRMON, 0, 3), + DDRCRU_RESET_OFFSET(SRST_RESETN_TIMER_DDRMON, 0, 4), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DFICTRL, 0, 5), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DDR_GRF, 0, 6), + DDRCRU_RESET_OFFSET(SRST_PRESETN_CRU_DDR, 0, 7), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DDRPHY, 0, 8), + DDRCRU_RESET_OFFSET(SRST_PRESETN_DMA2DDR, 0, 9), + + /* SUBDDRCRU-->SOFTRST_CON00 */ + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_SYSMEM_BIU, 0, 0), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_SYSMEM, 0, 1), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DDR_BIU, 0, 2), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DDRSCH0_CPU, 0, 3), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DDRSCH1_NPU, 0, 4), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DDRSCH2_POE, 0, 5), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DDRSCH3_VI, 0, 6), + SUBDDRCRU_RESET_OFFSET(SRST_RESETN_CORE_DDRC, 0, 7), + SUBDDRCRU_RESET_OFFSET(SRST_RESETN_DDRMON, 0, 8), + SUBDDRCRU_RESET_OFFSET(SRST_RESETN_DFICTRL, 0, 9), + SUBDDRCRU_RESET_OFFSET(SRST_RESETN_RS, 0, 11), + SUBDDRCRU_RESET_OFFSET(SRST_ARESETN_DMA2DDR, 0, 12), + SUBDDRCRU_RESET_OFFSET(SRST_RESETN_DDRPHY, 0, 13), + + /* VICRU-->SOFTRST_CON00 */ + VICRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_ISP, 0, 0), + VICRU_RESET_OFFSET(SRST_ARESETN_GMAC_BIU, 0, 1), + VICRU_RESET_OFFSET(SRST_ARESETN_VI_BIU, 0, 2), + VICRU_RESET_OFFSET(SRST_HRESETN_VI_BIU, 0, 3), + VICRU_RESET_OFFSET(SRST_PRESETN_VI_BIU, 0, 4), + VICRU_RESET_OFFSET(SRST_PRESETN_CRU_VI, 0, 5), + VICRU_RESET_OFFSET(SRST_PRESETN_VI_GRF, 0, 6), + VICRU_RESET_OFFSET(SRST_PRESETN_VI_PVTPLL, 0, 7), + VICRU_RESET_OFFSET(SRST_PRESETN_DSMC, 0, 8), + VICRU_RESET_OFFSET(SRST_ARESETN_DSMC, 0, 9), + VICRU_RESET_OFFSET(SRST_HRESETN_CAN0, 0, 10), + VICRU_RESET_OFFSET(SRST_RESETN_CAN0, 0, 11), + VICRU_RESET_OFFSET(SRST_HRESETN_CAN1, 0, 12), + VICRU_RESET_OFFSET(SRST_RESETN_CAN1, 0, 13), + + /* VICRU-->SOFTRST_CON01 */ + VICRU_RESET_OFFSET(SRST_PRESETN_GPIO2, 1, 0), + VICRU_RESET_OFFSET(SRST_DBRESETN_GPIO2, 1, 1), + VICRU_RESET_OFFSET(SRST_PRESETN_GPIO4, 1, 2), + VICRU_RESET_OFFSET(SRST_DBRESETN_GPIO4, 1, 3), + VICRU_RESET_OFFSET(SRST_PRESETN_GPIO5, 1, 4), + VICRU_RESET_OFFSET(SRST_DBRESETN_GPIO5, 1, 5), + VICRU_RESET_OFFSET(SRST_PRESETN_GPIO6, 1, 6), + VICRU_RESET_OFFSET(SRST_DBRESETN_GPIO6, 1, 7), + VICRU_RESET_OFFSET(SRST_PRESETN_GPIO7, 1, 8), + VICRU_RESET_OFFSET(SRST_DBRESETN_GPIO7, 1, 9), + VICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO2, 1, 10), + VICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO4, 1, 11), + VICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO5, 1, 12), + VICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO6, 1, 13), + VICRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO7, 1, 14), + + /* VICRU-->SOFTRST_CON02 */ + VICRU_RESET_OFFSET(SRST_RESETN_CORE_ISP, 2, 0), + VICRU_RESET_OFFSET(SRST_HRESETN_VICAP, 2, 1), + VICRU_RESET_OFFSET(SRST_ARESETN_VICAP, 2, 2), + VICRU_RESET_OFFSET(SRST_DRESETN_VICAP, 2, 3), + VICRU_RESET_OFFSET(SRST_ISP0RESETN_VICAP, 2, 4), + VICRU_RESET_OFFSET(SRST_RESETN_CORE_VPSS, 2, 5), + VICRU_RESET_OFFSET(SRST_RESETN_CORE_VPSL, 2, 6), + VICRU_RESET_OFFSET(SRST_PRESETN_CSI2HOST0, 2, 7), + VICRU_RESET_OFFSET(SRST_PRESETN_CSI2HOST1, 2, 8), + VICRU_RESET_OFFSET(SRST_PRESETN_CSI2HOST2, 2, 9), + VICRU_RESET_OFFSET(SRST_PRESETN_CSI2HOST3, 2, 10), + VICRU_RESET_OFFSET(SRST_HRESETN_SDMMC0, 2, 11), + VICRU_RESET_OFFSET(SRST_ARESETN_GMAC, 2, 12), + VICRU_RESET_OFFSET(SRST_PRESETN_CSIPHY0, 2, 13), + VICRU_RESET_OFFSET(SRST_PRESETN_CSIPHY1, 2, 14), + + /* VICRU-->SOFTRST_CON03 */ + VICRU_RESET_OFFSET(SRST_PRESETN_MACPHY, 3, 0), + VICRU_RESET_OFFSET(SRST_RESETN_MACPHY, 3, 1), + VICRU_RESET_OFFSET(SRST_PRESETN_SARADC1, 3, 2), + VICRU_RESET_OFFSET(SRST_RESETN_SARADC1, 3, 3), + VICRU_RESET_OFFSET(SRST_PRESETN_SARADC2, 3, 5), + VICRU_RESET_OFFSET(SRST_RESETN_SARADC2, 3, 6), + + /* VEPUCRU-->SOFTRST_CON00 */ + VEPUCRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_VEPU, 0, 0), + VEPUCRU_RESET_OFFSET(SRST_ARESETN_VEPU_BIU, 0, 1), + VEPUCRU_RESET_OFFSET(SRST_HRESETN_VEPU_BIU, 0, 2), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_VEPU_BIU, 0, 3), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_CRU_VEPU, 0, 4), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_VEPU_GRF, 0, 5), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_GPIO3, 0, 7), + VEPUCRU_RESET_OFFSET(SRST_DBRESETN_GPIO3, 0, 8), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_IOC_VCCIO3, 0, 9), + VEPUCRU_RESET_OFFSET(SRST_PRESETN_SARADC0, 0, 10), + VEPUCRU_RESET_OFFSET(SRST_RESETN_SARADC0, 0, 11), + VEPUCRU_RESET_OFFSET(SRST_HRESETN_SDMMC1, 0, 13), + + /* VEPUCRU-->SOFTRST_CON01 */ + VEPUCRU_RESET_OFFSET(SRST_PRESETN_VEPU_PVTPLL, 1, 0), + VEPUCRU_RESET_OFFSET(SRST_HRESETN_VEPU, 1, 1), + VEPUCRU_RESET_OFFSET(SRST_ARESETN_VEPU, 1, 2), + VEPUCRU_RESET_OFFSET(SRST_RESETN_CORE_VEPU, 1, 3), + + /* NPUCRU-->SOFTRST_CON00 */ + NPUCRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_NPU, 0, 0), + NPUCRU_RESET_OFFSET(SRST_ARESETN_NPU_BIU, 0, 2), + NPUCRU_RESET_OFFSET(SRST_HRESETN_NPU_BIU, 0, 3), + NPUCRU_RESET_OFFSET(SRST_PRESETN_NPU_BIU, 0, 4), + NPUCRU_RESET_OFFSET(SRST_PRESETN_CRU_NPU, 0, 5), + NPUCRU_RESET_OFFSET(SRST_PRESETN_NPU_GRF, 0, 6), + NPUCRU_RESET_OFFSET(SRST_PRESETN_NPU_PVTPLL, 0, 8), + NPUCRU_RESET_OFFSET(SRST_HRESETN_RKNN, 0, 9), + NPUCRU_RESET_OFFSET(SRST_ARESETN_RKNN, 0, 10), + + /* VDOCRU-->SOFTRST_CON00 */ + VDOCRU_RESET_OFFSET(SRST_ARESETN_RKVDEC_BIU, 0, 0), + VDOCRU_RESET_OFFSET(SRST_ARESETN_VDO_BIU, 0, 1), + VDOCRU_RESET_OFFSET(SRST_HRESETN_VDO_BIU, 0, 3), + VDOCRU_RESET_OFFSET(SRST_PRESETN_VDO_BIU, 0, 4), + VDOCRU_RESET_OFFSET(SRST_PRESETN_CRU_VDO, 0, 5), + VDOCRU_RESET_OFFSET(SRST_PRESETN_VDO_GRF, 0, 6), + VDOCRU_RESET_OFFSET(SRST_ARESETN_RKVDEC, 0, 7), + VDOCRU_RESET_OFFSET(SRST_HRESETN_RKVDEC, 0, 8), + VDOCRU_RESET_OFFSET(SRST_RESETN_HEVC_CA_RKVDEC, 0, 9), + VDOCRU_RESET_OFFSET(SRST_ARESETN_VOP, 0, 10), + VDOCRU_RESET_OFFSET(SRST_HRESETN_VOP, 0, 11), + VDOCRU_RESET_OFFSET(SRST_DRESETN_VOP, 0, 12), + VDOCRU_RESET_OFFSET(SRST_ARESETN_OOC, 0, 13), + VDOCRU_RESET_OFFSET(SRST_HRESETN_OOC, 0, 14), + VDOCRU_RESET_OFFSET(SRST_DRESETN_OOC, 0, 15), + + /* VDOCRU-->SOFTRST_CON01 */ + VDOCRU_RESET_OFFSET(SRST_HRESETN_RKJPEG, 1, 3), + VDOCRU_RESET_OFFSET(SRST_ARESETN_RKJPEG, 1, 4), + VDOCRU_RESET_OFFSET(SRST_ARESETN_RKMMU_DECOM, 1, 5), + VDOCRU_RESET_OFFSET(SRST_HRESETN_RKMMU_DECOM, 1, 6), + VDOCRU_RESET_OFFSET(SRST_DRESETN_DECOM, 1, 8), + VDOCRU_RESET_OFFSET(SRST_ARESETN_DECOM, 1, 9), + VDOCRU_RESET_OFFSET(SRST_PRESETN_DECOM, 1, 10), + VDOCRU_RESET_OFFSET(SRST_PRESETN_MIPI_DSI, 1, 12), + VDOCRU_RESET_OFFSET(SRST_PRESETN_DSIPHY, 1, 13), + + /* VCPCRU-->SOFTRST_CON00 */ + VCPCRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_VCP, 0, 0), + VCPCRU_RESET_OFFSET(SRST_ARESETN_VCP_BIU, 0, 1), + VCPCRU_RESET_OFFSET(SRST_HRESETN_VCP_BIU, 0, 2), + VCPCRU_RESET_OFFSET(SRST_PRESETN_VCP_BIU, 0, 3), + VCPCRU_RESET_OFFSET(SRST_PRESETN_CRU_VCP, 0, 4), + VCPCRU_RESET_OFFSET(SRST_PRESETN_VCP_GRF, 0, 5), + VCPCRU_RESET_OFFSET(SRST_PRESETN_VCP_PVTPLL, 0, 7), + VCPCRU_RESET_OFFSET(SRST_ARESETN_AISP_BIU, 0, 8), + VCPCRU_RESET_OFFSET(SRST_HRESETN_AISP_BIU, 0, 9), + VCPCRU_RESET_OFFSET(SRST_RESETN_CORE_AISP, 0, 13), + + /* VCPCRU-->SOFTRST_CON01 */ + VCPCRU_RESET_OFFSET(SRST_HRESETN_FEC, 1, 0), + VCPCRU_RESET_OFFSET(SRST_ARESETN_FEC, 1, 1), + VCPCRU_RESET_OFFSET(SRST_RESETN_CORE_FEC, 1, 2), + VCPCRU_RESET_OFFSET(SRST_HRESETN_AVSP, 1, 3), + VCPCRU_RESET_OFFSET(SRST_ARESETN_AVSP, 1, 4), +}; + +void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rv1126b_register_offset, + ARRAY_SIZE(rv1126b_register_offset), + reg_base + RV1126B_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} + -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang ` (2 preceding siblings ...) 2025-10-20 2:37 ` [PATCH v3 3/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang @ 2025-10-20 2:37 ` Elaine Zhang 2025-10-20 9:38 ` Diederik de Haas 2025-10-20 17:26 ` Conor Dooley 2025-10-20 2:37 ` [PATCH v3 5/5] clk: rockchip: add support for pvtpll clk Elaine Zhang 4 siblings, 2 replies; 10+ messages in thread From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw) To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao Add pvtpll documentation for rockchip. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml new file mode 100644 index 000000000000..8be34bcde7b0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pvtpll + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +properties: + compatible: + items: + - enum: + - rockchip,rv1103b-core-pvtpll + - rockchip,rv1103b-enc-pvtpll + - rockchip,rv1103b-isp-pvtpll + - rockchip,rv1103b-npu-pvtpll + - rockchip,rv1126b-core-pvtpll + - rockchip,rv1126b-isp-pvtpll + - rockchip,rv1126b-enc-pvtpll + - rockchip,rv1126b-aisp-pvtpll + - rockchip,rv1126b-npu-pvtpll + - rockchip,rk3506-core-pvtpll + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + rockchip,cru: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the main Clock and Reset Unit (CRU) controller. + Required for PVTPLLs that need to interact with the main CRU + for clock management operations. + +required: + - "#clock-cells" + - compatible + - reg + - clock-output-names + +additionalProperties: false + +examples: + - | + pvtpll_core: pvtpll-core@20480000 { + compatible = "rockchip,rv1126b-core-pvtpll", "syscon"; + reg = <0x20480000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_core_pvtpll"; + }; + + - | + pvtpll_isp: pvtpll-isp@21c60000 { + compatible = "rockchip,rv1126b-isp-pvtpll", "syscon"; + reg = <0x21c60000 0x100>; + rockchip,cru = <&cru>; + #clock-cells = <0>; + clock-output-names = "clk_isp_pvtpll"; + }; + + - | + pvtpll_enc: pvtpll-enc@21f00000 { + compatible = "rockchip,rv1126b-enc-pvtpll", "syscon"; + reg = <0x21f00000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_vepu_pvtpll"; + }; + + - | + pvtpll_aisp: pvtpll-aisp@21fc0000 { + compatible = "rockchip,rv1126b-aisp-pvtpll", "syscon"; + reg = <0x21fc0000 0x100>; + rockchip,cru = <&cru>; + #clock-cells = <0>; + clock-output-names = "clk_vcp_pvtpll"; + }; + + - | + pvtpll_npu: pvtpll-npu@22080000 { + compatible = "rockchip,rv1126b-npu-pvtpll", "syscon"; + reg = <0x22080000 0x100>; + rockchip,cru = <&cru>; + #clock-cells = <0>; + clock-output-names = "clk_npu_pvtpll"; + }; + +... -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll 2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang @ 2025-10-20 9:38 ` Diederik de Haas 2025-10-20 17:25 ` Conor Dooley 2025-10-20 17:26 ` Conor Dooley 1 sibling, 1 reply; 10+ messages in thread From: Diederik de Haas @ 2025-10-20 9:38 UTC (permalink / raw) To: Elaine Zhang, mturquette, sboyd, sugar.zhang, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao On Mon Oct 20, 2025 at 4:37 AM CEST, Elaine Zhang wrote: > Add pvtpll documentation for rockchip. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++ > 1 file changed, 100 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > new file mode 100644 Should this file have the 'clk-' part in its name? In a way this is different from the other DT binding files, but none of the others have the 'clk-' part in their file name: me@pc:~/linux/Documentation/devicetree/bindings/clock$ ls -lh rockchip,* -rw-rw-r-- 1 me me 2,9K okt 20 11:32 rockchip,px30-cru.yaml -rw-rw-r-- 1 me me 1,9K okt 20 11:32 rockchip,rk3036-cru.yaml -rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3128-cru.yaml -rw-rw-r-- 1 me me 2,3K okt 20 11:32 rockchip,rk3188-cru.yaml -rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3228-cru.yaml -rw-rw-r-- 1 me me 2,6K okt 20 11:32 rockchip,rk3288-cru.yaml -rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rk3308-cru.yaml -rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3328-cru.yaml -rw-rw-r-- 1 me me 2,4K okt 20 11:32 rockchip,rk3368-cru.yaml -rw-rw-r-- 1 me me 2,5K okt 20 11:32 rockchip,rk3399-cru.yaml -rw-rw-r-- 1 me me 1,5K okt 20 11:32 rockchip,rk3528-cru.yaml -rw-rw-r-- 1 me me 1,1K okt 20 11:32 rockchip,rk3562-cru.yaml -rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3568-cru.yaml -rw-rw-r-- 1 me me 1,2K okt 20 11:32 rockchip,rk3576-cru.yaml -rw-rw-r-- 1 me me 1,6K okt 20 11:32 rockchip,rk3588-cru.yaml -rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rv1108-cru.yaml -rw-rw-r-- 1 me me 1,3K okt 20 11:32 rockchip,rv1126-cru.yaml > index 000000000000..8be34bcde7b0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > @@ -0,0 +1,100 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Pvtpll > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + items: > + - enum: > + - rockchip,rv1103b-core-pvtpll > + - rockchip,rv1103b-enc-pvtpll > + - rockchip,rv1103b-isp-pvtpll > + - rockchip,rv1103b-npu-pvtpll > + - rockchip,rv1126b-core-pvtpll > + - rockchip,rv1126b-isp-pvtpll > + - rockchip,rv1126b-enc-pvtpll > + - rockchip,rv1126b-aisp-pvtpll > + - rockchip,rv1126b-npu-pvtpll > + - rockchip,rk3506-core-pvtpll > + - const: syscon > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 0 > + > + clocks: > + maxItems: 1 > + > + clock-output-names: > + maxItems: 1 > + > + rockchip,cru: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: | > + Phandle to the main Clock and Reset Unit (CRU) controller. > + Required for PVTPLLs that need to interact with the main CRU > + for clock management operations. > + > +required: > + - "#clock-cells" > + - compatible > + - reg > + - clock-output-names > + > +additionalProperties: false > + > +examples: > + - | > + pvtpll_core: pvtpll-core@20480000 { > + compatible = "rockchip,rv1126b-core-pvtpll", "syscon"; > + reg = <0x20480000 0x100>; > + #clock-cells = <0>; > + clock-output-names = "clk_core_pvtpll"; > + }; > + > + - | > + pvtpll_isp: pvtpll-isp@21c60000 { > + compatible = "rockchip,rv1126b-isp-pvtpll", "syscon"; > + reg = <0x21c60000 0x100>; > + rockchip,cru = <&cru>; > + #clock-cells = <0>; > + clock-output-names = "clk_isp_pvtpll"; > + }; > + > + - | > + pvtpll_enc: pvtpll-enc@21f00000 { > + compatible = "rockchip,rv1126b-enc-pvtpll", "syscon"; > + reg = <0x21f00000 0x100>; > + #clock-cells = <0>; > + clock-output-names = "clk_vepu_pvtpll"; > + }; > + > + - | > + pvtpll_aisp: pvtpll-aisp@21fc0000 { > + compatible = "rockchip,rv1126b-aisp-pvtpll", "syscon"; > + reg = <0x21fc0000 0x100>; > + rockchip,cru = <&cru>; > + #clock-cells = <0>; > + clock-output-names = "clk_vcp_pvtpll"; > + }; > + > + - | > + pvtpll_npu: pvtpll-npu@22080000 { > + compatible = "rockchip,rv1126b-npu-pvtpll", "syscon"; > + reg = <0x22080000 0x100>; > + rockchip,cru = <&cru>; > + #clock-cells = <0>; > + clock-output-names = "clk_npu_pvtpll"; rockchip,cru line as the last line? Cheers, Diederik > + }; > + > +... ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll 2025-10-20 9:38 ` Diederik de Haas @ 2025-10-20 17:25 ` Conor Dooley 0 siblings, 0 replies; 10+ messages in thread From: Conor Dooley @ 2025-10-20 17:25 UTC (permalink / raw) To: Diederik de Haas Cc: Elaine Zhang, mturquette, sboyd, sugar.zhang, heiko, robh, krzysztof.kozlowski+dt, conor+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao [-- Attachment #1: Type: text/plain, Size: 5578 bytes --] On Mon, Oct 20, 2025 at 11:38:02AM +0200, Diederik de Haas wrote: > On Mon Oct 20, 2025 at 4:37 AM CEST, Elaine Zhang wrote: > > Add pvtpll documentation for rockchip. > > > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > > --- > > .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++ > > 1 file changed, 100 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > > new file mode 100644 > > Should this file have the 'clk-' part in its name? > In a way this is different from the other DT binding files, but none of > the others have the 'clk-' part in their file name: Normally we would ask for a filename matching the compatible, which IIRC is what these -cru ones are doing. > > me@pc:~/linux/Documentation/devicetree/bindings/clock$ ls -lh rockchip,* > -rw-rw-r-- 1 me me 2,9K okt 20 11:32 rockchip,px30-cru.yaml > -rw-rw-r-- 1 me me 1,9K okt 20 11:32 rockchip,rk3036-cru.yaml > -rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3128-cru.yaml > -rw-rw-r-- 1 me me 2,3K okt 20 11:32 rockchip,rk3188-cru.yaml > -rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3228-cru.yaml > -rw-rw-r-- 1 me me 2,6K okt 20 11:32 rockchip,rk3288-cru.yaml > -rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rk3308-cru.yaml > -rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3328-cru.yaml > -rw-rw-r-- 1 me me 2,4K okt 20 11:32 rockchip,rk3368-cru.yaml > -rw-rw-r-- 1 me me 2,5K okt 20 11:32 rockchip,rk3399-cru.yaml > -rw-rw-r-- 1 me me 1,5K okt 20 11:32 rockchip,rk3528-cru.yaml > -rw-rw-r-- 1 me me 1,1K okt 20 11:32 rockchip,rk3562-cru.yaml > -rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3568-cru.yaml > -rw-rw-r-- 1 me me 1,2K okt 20 11:32 rockchip,rk3576-cru.yaml > -rw-rw-r-- 1 me me 1,6K okt 20 11:32 rockchip,rk3588-cru.yaml > -rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rv1108-cru.yaml > -rw-rw-r-- 1 me me 1,3K okt 20 11:32 rockchip,rv1126-cru.yaml > > > index 000000000000..8be34bcde7b0 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > > @@ -0,0 +1,100 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip Pvtpll > > + > > +maintainers: > > + - Elaine Zhang <zhangqing@rock-chips.com> > > + - Heiko Stuebner <heiko@sntech.de> > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - rockchip,rv1103b-core-pvtpll > > + - rockchip,rv1103b-enc-pvtpll > > + - rockchip,rv1103b-isp-pvtpll > > + - rockchip,rv1103b-npu-pvtpll > > + - rockchip,rv1126b-core-pvtpll > > + - rockchip,rv1126b-isp-pvtpll > > + - rockchip,rv1126b-enc-pvtpll > > + - rockchip,rv1126b-aisp-pvtpll > > + - rockchip,rv1126b-npu-pvtpll > > + - rockchip,rk3506-core-pvtpll > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + "#clock-cells": > > + const: 0 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-output-names: > > + maxItems: 1 > > + > > + rockchip,cru: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: | > > + Phandle to the main Clock and Reset Unit (CRU) controller. > > + Required for PVTPLLs that need to interact with the main CRU > > + for clock management operations. > > + > > +required: > > + - "#clock-cells" > > + - compatible > > + - reg > > + - clock-output-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + pvtpll_core: pvtpll-core@20480000 { Additionally, none of the labels are being used and should be removed. "pvtpll-anything" is also not a generic node name, so those should get changed too. > > + compatible = "rockchip,rv1126b-core-pvtpll", "syscon"; > > + reg = <0x20480000 0x100>; > > + #clock-cells = <0>; > > + clock-output-names = "clk_core_pvtpll"; > > + }; > > + > > + - | > > + pvtpll_isp: pvtpll-isp@21c60000 { > > + compatible = "rockchip,rv1126b-isp-pvtpll", "syscon"; > > + reg = <0x21c60000 0x100>; > > + rockchip,cru = <&cru>; > > + #clock-cells = <0>; > > + clock-output-names = "clk_isp_pvtpll"; > > + }; > > + > > + - | > > + pvtpll_enc: pvtpll-enc@21f00000 { > > + compatible = "rockchip,rv1126b-enc-pvtpll", "syscon"; > > + reg = <0x21f00000 0x100>; > > + #clock-cells = <0>; > > + clock-output-names = "clk_vepu_pvtpll"; > > + }; > > + > > + - | > > + pvtpll_aisp: pvtpll-aisp@21fc0000 { > > + compatible = "rockchip,rv1126b-aisp-pvtpll", "syscon"; > > + reg = <0x21fc0000 0x100>; > > + rockchip,cru = <&cru>; > > + #clock-cells = <0>; > > + clock-output-names = "clk_vcp_pvtpll"; > > + }; > > + > > + - | > > + pvtpll_npu: pvtpll-npu@22080000 { > > + compatible = "rockchip,rv1126b-npu-pvtpll", "syscon"; > > + reg = <0x22080000 0x100>; > > + rockchip,cru = <&cru>; > > + #clock-cells = <0>; > > + clock-output-names = "clk_npu_pvtpll"; > > rockchip,cru line as the last line? > > Cheers, > Diederik > > > + }; > > + > > +... > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll 2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang 2025-10-20 9:38 ` Diederik de Haas @ 2025-10-20 17:26 ` Conor Dooley 1 sibling, 0 replies; 10+ messages in thread From: Conor Dooley @ 2025-10-20 17:26 UTC (permalink / raw) To: Elaine Zhang Cc: mturquette, sboyd, sugar.zhang, heiko, robh, krzysztof.kozlowski+dt, conor+dt, devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao [-- Attachment #1: Type: text/plain, Size: 2233 bytes --] On Mon, Oct 20, 2025 at 10:37:23AM +0800, Elaine Zhang wrote: > Add pvtpll documentation for rockchip. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > .../bindings/clock/rockchip,clk-pvtpll.yaml | 100 ++++++++++++++++++ > 1 file changed, 100 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > new file mode 100644 > index 000000000000..8be34bcde7b0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml > @@ -0,0 +1,100 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip Pvtpll > + > +maintainers: > + - Elaine Zhang <zhangqing@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + items: > + - enum: > + - rockchip,rv1103b-core-pvtpll > + - rockchip,rv1103b-enc-pvtpll > + - rockchip,rv1103b-isp-pvtpll > + - rockchip,rv1103b-npu-pvtpll > + - rockchip,rv1126b-core-pvtpll > + - rockchip,rv1126b-isp-pvtpll > + - rockchip,rv1126b-enc-pvtpll > + - rockchip,rv1126b-aisp-pvtpll > + - rockchip,rv1126b-npu-pvtpll > + - rockchip,rk3506-core-pvtpll > + - const: syscon > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 0 > + > + clocks: > + maxItems: 1 > + > + clock-output-names: > + maxItems: 1 > + > + rockchip,cru: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: | > + Phandle to the main Clock and Reset Unit (CRU) controller. > + Required for PVTPLLs that need to interact with the main CRU > + for clock management operations. > + > +required: > + - "#clock-cells" > + - compatible > + - reg > + - clock-output-names Please follow the property definition order here. pw-bot: changes-requested [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 5/5] clk: rockchip: add support for pvtpll clk 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang ` (3 preceding siblings ...) 2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang @ 2025-10-20 2:37 ` Elaine Zhang 4 siblings, 0 replies; 10+ messages in thread From: Elaine Zhang @ 2025-10-20 2:37 UTC (permalink / raw) To: mturquette, sboyd, sugar.zhang, zhangqing, heiko, robh, krzysztof.kozlowski+dt, conor+dt Cc: devicetree, linux-arm-kernel, linux-clk, linux-rockchip, linux-kernel, huangtao Support to adjust pvtpll by volt-sel and otp. Support calibrate pvtpll init frequency. PVTPLL is used to monitor the chip performance variance caused by chip process, voltage and temperature, and generate a set of reference signals for adjusting the voltage of the chip. PVTPLL supports the following features: 1. A clock oscillation ring is integrated and used to generate a clock like signal (osc_clk),the frequency of this clock is determined by the cell delay value of clock oscillation ring circuit 2. A frequency counter(osc_cnt) is used to measure the frequency of osc_clk. 3. A externally input clock (ref_clk) is used as a reference clock for detecting the frequency of osc_clk. 4. A calculation counter uses ref_clk to generate a configurable periodic timing window. 5. Two clock counters are used to measure the frequency of the clock generated by OSC_WRAPPER? 6. Support for dividing the ref_clk and osc_clk 7. Support for configuring the effective polarity of the voltage regulator signal 'OUT' The clock path of cpu used pvtpll: --gpll--|--\ | \ | \ | \ | \ | \ | \ --v0pll--| mux |--[gate]--[div]--clk_core_src--|mux |--clk_core | / | / | / --ref_clk--[div]-cpu_pvtpll--| / --v1pll--| / | / |--/ Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-pvtpll.c | 925 ++++++++++++++++++++++++++++++ 1 file changed, 925 insertions(+) create mode 100644 drivers/clk/rockchip/clk-pvtpll.c diff --git a/drivers/clk/rockchip/clk-pvtpll.c b/drivers/clk/rockchip/clk-pvtpll.c new file mode 100644 index 000000000000..8a5c9a84646e --- /dev/null +++ b/drivers/clk/rockchip/clk-pvtpll.c @@ -0,0 +1,925 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/clk-provider.h> +#include <linux/regulator/consumer.h> +#include "clk.h" + +#define MHz 1000000 + +#define RV1103B_PVTPLL_GCK_CFG 0x20 +#define RV1103B_PVTPLL_GCK_LEN 0x24 +#define RV1103B_GCK_START BIT(0) +#define RV1103B_GCK_EN BIT(1) +#define RV1103B_GCK_MODE BIT(5) +#define RV1103B_GCK_RING_LEN_SEL_OFFSET 0 +#define RV1103B_GCK_RING_LEN_SEL_MASK 0x1ff +#define RV1103B_GCK_RING_SEL_OFFSET 10 +#define RV1103B_GCK_RING_SEL_MASK 0x07 +#define RV1103B_PVTPLL_MAX_LENGTH 0x1ff +#define RV1103B_PVTPLL_GCK_CNT_AVG 0x54 + +#define RV1126B_PVTPLL_NORMAL_MODE 0x1 +#define RV1126B_PVTPLL_SLOW_MODE 0 +#define RV1126B_PVTPLL_MODE_SHIFT 0 +#define RV1126B_PVTPLL_MODE_MASK 0x1 + +#define RK3506_GRF_CORE_PVTPLL_CON0_L 0x00 +#define RK3506_GRF_CORE_PVTPLL_CON0_H 0x04 +#define RK3506_OSC_RING_SEL_OFFSET 8 +#define RK3506_OSC_RING_SEL_MASK 0x03 +#define RK3506_OSC_EN BIT(1) +#define RK3506_START BIT(0) +#define RK3506_RING_LENGTH_SEL_OFFSET 0 +#define RK3506_RING_LENGTH_SEL_MASK 0x7f +#define RK3506_PVTPLL_MAX_LENGTH 0x7f + +struct rockchip_clock_pvtpll; + +struct pvtpll_table { + unsigned int rate; + u32 length; + u32 length_frac; + u32 ring_sel; + u32 volt_sel_thr; +}; + +struct rockchip_clock_pvtpll_info { + const struct clk_ops *clk_ops; + unsigned int table_size; + struct pvtpll_table *table; + unsigned int jm_table_size; + struct pvtpll_table *jm_table; + unsigned int pvtpll_adjust_factor; + unsigned int calibrate_length_step; + unsigned int calibrate_freq_per_step; + unsigned int mode_offset; + bool is_always_on; + int (*config)(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table); + int (*pvtpll_calibrate)(struct rockchip_clock_pvtpll *pvtpll); + int (*pvtpll_volt_sel_adjust)(struct rockchip_clock_pvtpll *pvtpll, + u32 clock_id, + u32 volt_sel); +}; + +struct rockchip_clock_pvtpll { + struct device *dev; + struct list_head list_head; + struct rockchip_clock_pvtpll_info *info; + struct regmap *regmap; + struct regmap *regmap_cru; + struct clk_hw hw; + struct clk *main_clk; + struct clk *sclk; + struct clk *pvtpll_clk; + struct clk *pvtpll_out; + struct notifier_block pvtpll_nb; + struct delayed_work pvtpll_calibrate_work; + unsigned long cur_rate; + u32 pvtpll_clk_id; +}; + +static LIST_HEAD(rockchip_clock_pvtpll_list); +static DEFINE_MUTEX(pvtpll_list_mutex); + +struct otp_opp_info { + u16 min_freq; + u16 max_freq; + u8 volt; + u8 length; +} __packed; + +#define ROCKCHIP_PVTPLL(_rate, _sel, _len) \ +{ \ + .rate = _rate##U, \ + .ring_sel = _sel, \ + .length = _len, \ +} + +#define ROCKCHIP_PVTPLL_VOLT_SEL(_rate, _sel, _len, _volt_sel_thr) \ +{ \ + .rate = _rate##U, \ + .ring_sel = _sel, \ + .length = _len, \ + .volt_sel_thr = _volt_sel_thr, \ +} + +static struct pvtpll_table rv1103b_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length */ + ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 1, 6, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1512000000, 1, 6, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(1416000000, 1, 6, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(1296000000, 1, 6, 5), + ROCKCHIP_PVTPLL_VOLT_SEL(1200000000, 1, 6, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1008000000, 1, 26, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(816000000, 1, 50, 3), +}; + +static struct pvtpll_table rv1103b_enc_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(500000000, 1, 80), +}; + +static struct pvtpll_table rv1103b_isp_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(400000000, 1, 160), +}; + +static struct pvtpll_table rv1103b_npu_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL_VOLT_SEL(1000000000, 1, 12, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(900000000, 1, 12, 6), + ROCKCHIP_PVTPLL_VOLT_SEL(800000000, 1, 12, 4), + ROCKCHIP_PVTPLL_VOLT_SEL(700000000, 1, 32, 4), +}; + +static struct pvtpll_table rv1126b_aisp_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(835000000, 0, 8), + ROCKCHIP_PVTPLL(805000000, 0, 8), + ROCKCHIP_PVTPLL(775000000, 0, 8), +}; + +static struct pvtpll_table rv1126b_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length */ + ROCKCHIP_PVTPLL_VOLT_SEL(1900000000, 0, 30, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(1800000000, 0, 30, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(1700000000, 0, 30, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 0, 30, 5), + ROCKCHIP_PVTPLL_VOLT_SEL(1512000000, 0, 30, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1416000000, 0, 34, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1296000000, 0, 38, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1200000000, 0, 38, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1008000000, 0, 52, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(816000000, 0, 84, 3), +}; + +static struct pvtpll_table rv1126b_enc_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(550000000, 0, 80), + ROCKCHIP_PVTPLL(520000000, 0, 88), + ROCKCHIP_PVTPLL(500000000, 0, 88), + ROCKCHIP_PVTPLL(480000000, 0, 88), +}; + +static struct pvtpll_table rv1126b_isp_pvtpll_table[] = { + /* rate_hz, ring_se, length */ + ROCKCHIP_PVTPLL(530000000, 0, 100), + ROCKCHIP_PVTPLL(510000000, 0, 100), + ROCKCHIP_PVTPLL(490000000, 0, 100), +}; + +static struct pvtpll_table rv1126b_npu_pvtpll_table[] = { + /* rate_hz, ring_se, length, volt_sel_thr */ + ROCKCHIP_PVTPLL_VOLT_SEL(1100000000, 0, 12, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(1050000000, 0, 12, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(1000000000, 0, 12, 0), + ROCKCHIP_PVTPLL_VOLT_SEL(950000000, 0, 12, 2), + ROCKCHIP_PVTPLL_VOLT_SEL(900000000, 0, 14, 1), + ROCKCHIP_PVTPLL_VOLT_SEL(800000000, 0, 18, 1), + ROCKCHIP_PVTPLL_VOLT_SEL(700000000, 0, 36, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(600000000, 0, 60, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(510000000, 0, 108, 3), +}; + +static struct pvtpll_table rk3506_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length, volt_sel_thr */ + ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 0, 6, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1512000000, 0, 6, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1416000000, 0, 6, 5), + ROCKCHIP_PVTPLL_VOLT_SEL(1296000000, 0, 6, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1200000000, 0, 6, 2), + ROCKCHIP_PVTPLL_VOLT_SEL(1008000000, 0, 10, 4), + ROCKCHIP_PVTPLL_VOLT_SEL(800000000, 0, 18, 4), +}; + +static struct pvtpll_table rk3506j_core_pvtpll_table[] = { + /* rate_hz, ring_sel, length, volt_sel_thr */ + ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 0, 6, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1512000000, 0, 7, 7), + ROCKCHIP_PVTPLL_VOLT_SEL(1416000000, 0, 7, 5), + ROCKCHIP_PVTPLL_VOLT_SEL(1296000000, 0, 7, 3), + ROCKCHIP_PVTPLL_VOLT_SEL(1200000000, 0, 7, 2), + ROCKCHIP_PVTPLL_VOLT_SEL(1008000000, 0, 11, 2), + ROCKCHIP_PVTPLL_VOLT_SEL(800000000, 0, 19, 2), +}; + +static struct pvtpll_table +*rockchip_get_pvtpll_settings(struct rockchip_clock_pvtpll *pvtpll, + unsigned long rate) +{ + const struct rockchip_clock_pvtpll_info *info = pvtpll->info; + int i; + + for (i = 0; i < info->table_size; i++) { + if (rate == info->table[i].rate) + return &info->table[i]; + } + return NULL; +} + +static int rv1103b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table) +{ + u32 val; + int ret = 0; + + val = HIWORD_UPDATE(table->ring_sel, RV1103B_GCK_RING_SEL_MASK, + RV1103B_GCK_RING_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + + val = HIWORD_UPDATE(table->length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, + RV1103B_GCK_EN | (RV1103B_GCK_EN << 16) | + RV1103B_GCK_MODE | (RV1103B_GCK_MODE << 16)); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, + RV1103B_GCK_START | (RV1103B_GCK_START << 16)); + if (ret) + return ret; + + return ret; +} + +static int rv1126b_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table) +{ + u32 val; + int ret = 0; + + ret = rv1103b_pvtpll_configs(pvtpll, table); + if (ret) + return ret; + + if (!pvtpll->regmap_cru) + return 0; + + val = HIWORD_UPDATE(RV1126B_PVTPLL_NORMAL_MODE, RV1126B_PVTPLL_MODE_MASK, + RV1126B_PVTPLL_MODE_SHIFT); + return regmap_write(pvtpll->regmap_cru, pvtpll->info->mode_offset, val); +} + +static int rk3506_pvtpll_configs(struct rockchip_clock_pvtpll *pvtpll, + struct pvtpll_table *table) +{ + u32 val; + int ret = 0; + + val = HIWORD_UPDATE(table->ring_sel, RK3506_OSC_RING_SEL_MASK, + RK3506_OSC_RING_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_L, val); + if (ret) + return ret; + + val = HIWORD_UPDATE(table->length, RK3506_RING_LENGTH_SEL_MASK, + RK3506_RING_LENGTH_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_H, val); + if (ret) + return ret; + + ret = regmap_write(pvtpll->regmap, RK3506_GRF_CORE_PVTPLL_CON0_L, + RK3506_START | (RK3506_START << 16) | + RK3506_OSC_EN | (RK3506_OSC_EN << 16)); + if (ret) + return ret; + + return ret; +} + +static int rockchip_clock_pvtpll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rockchip_clock_pvtpll *pvtpll; + struct pvtpll_table *table; + int ret = 0; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + /* + * The calibration is only for the init frequency of pvtpll on the platform + * which regulator is fixed, if the frequency will be change, we assume that + * dvfs is working, so just cancel the calibration work and use the pvtpll + * configuration from pvtpll_table, it will match the opp-table. + */ + if (pvtpll->info->pvtpll_calibrate) + cancel_delayed_work_sync(&pvtpll->pvtpll_calibrate_work); + + table = rockchip_get_pvtpll_settings(pvtpll, rate); + if (!table) + return 0; + + ret = pvtpll->info->config(pvtpll, table); + + pvtpll->cur_rate = rate; + return ret; +} + +static unsigned long +rockchip_clock_pvtpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rockchip_clock_pvtpll *pvtpll; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + return pvtpll->cur_rate; +} + +static long rockchip_clock_pvtpll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct rockchip_clock_pvtpll *pvtpll; + struct pvtpll_table *table; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + + if (!pvtpll) + return 0; + + table = rockchip_get_pvtpll_settings(pvtpll, rate); + if (!table) + return 0; + + return rate; +} + +static int rv1126b_pvtpll_enable(struct clk_hw *hw) +{ + struct rockchip_clock_pvtpll *pvtpll; + struct pvtpll_table *table; + u32 val = 0; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + table = rockchip_get_pvtpll_settings(pvtpll, pvtpll->cur_rate); + if (!table) + return 0; + + regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, &val); + if (!(val & RV1103B_GCK_EN)) + return pvtpll->info->config(pvtpll, table); + + return 0; +} + +static void rv1126b_pvtpll_disable(struct clk_hw *hw) +{ + struct rockchip_clock_pvtpll *pvtpll; + u32 val; + int ret; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + if (!pvtpll->regmap_cru) + return; + + val = HIWORD_UPDATE(RV1126B_PVTPLL_SLOW_MODE, RV1126B_PVTPLL_MODE_MASK, + RV1126B_PVTPLL_MODE_SHIFT); + ret = regmap_write(pvtpll->regmap_cru, pvtpll->info->mode_offset, val); + if (ret) + return; + regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, RV1103B_GCK_EN << 16); +} + +static int rv1126b_pvtpll_is_enabled(struct clk_hw *hw) +{ + struct rockchip_clock_pvtpll *pvtpll; + u32 val = 0; + + pvtpll = container_of(hw, struct rockchip_clock_pvtpll, hw); + regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CFG, &val); + + return (val & RV1103B_GCK_EN); +} + +static const struct clk_ops clock_pvtpll_ops = { + .recalc_rate = rockchip_clock_pvtpll_recalc_rate, + .round_rate = rockchip_clock_pvtpll_round_rate, + .set_rate = rockchip_clock_pvtpll_set_rate, +}; + +static const struct clk_ops rv1126b_pvtpll_ops = { + .recalc_rate = rockchip_clock_pvtpll_recalc_rate, + .round_rate = rockchip_clock_pvtpll_round_rate, + .set_rate = rockchip_clock_pvtpll_set_rate, + .enable = rv1126b_pvtpll_enable, + .disable = rv1126b_pvtpll_disable, + .is_enabled = rv1126b_pvtpll_is_enabled, +}; + +/* Remove is_enabled for fixing clk_summary issue */ +static const struct clk_ops rv1126b_npu_pvtpll_ops = { + .recalc_rate = rockchip_clock_pvtpll_recalc_rate, + .round_rate = rockchip_clock_pvtpll_round_rate, + .set_rate = rockchip_clock_pvtpll_set_rate, + .enable = rv1126b_pvtpll_enable, + .disable = rv1126b_pvtpll_disable, +}; + +static int clock_pvtpll_regitstor(struct device *dev, + struct rockchip_clock_pvtpll *pvtpll) +{ + struct clk_init_data init = {}; + + init.parent_names = NULL; + init.num_parents = 0; + init.flags = CLK_GET_RATE_NOCACHE; + init.name = "pvtpll"; + if (pvtpll->info->clk_ops) + init.ops = pvtpll->info->clk_ops; + else + init.ops = &clock_pvtpll_ops; + + pvtpll->hw.init = &init; + + /* optional override of the clockname */ + of_property_read_string_index(dev->of_node, "clock-output-names", + 0, &init.name); + pvtpll->pvtpll_out = devm_clk_register(dev, &pvtpll->hw); + if (IS_ERR(pvtpll->pvtpll_out)) + return PTR_ERR(pvtpll->pvtpll_out); + + return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, + pvtpll->pvtpll_out); +} + +static int pvtpll_volt_sel_adjust_linear(struct rockchip_clock_pvtpll *pvtpll, + u32 clock_id, + u32 volt_sel) +{ + struct pvtpll_table *table = pvtpll->info->table; + unsigned int size = pvtpll->info->table_size; + unsigned int factor = pvtpll->info->pvtpll_adjust_factor; + u32 delta_len = 0; + int i; + + for (i = 0; i < size; i++) { + if (!table[i].volt_sel_thr) + continue; + if (volt_sel >= table[i].volt_sel_thr) { + delta_len = (volt_sel - table[i].volt_sel_thr + 1) * factor; + table[i].length += delta_len; + if (table[i].length > RK3506_PVTPLL_MAX_LENGTH) + table[i].length = RK3506_PVTPLL_MAX_LENGTH; + + /* update new pvtpll config for current rate */ + if (table[i].rate == pvtpll->cur_rate) + pvtpll->info->config(pvtpll, table + i); + } + } + + return 0; +} + +int rockchip_pvtpll_volt_sel_adjust(u32 clock_id, u32 volt_sel) +{ + struct rockchip_clock_pvtpll *pvtpll; + int ret = -ENODEV; + + mutex_lock(&pvtpll_list_mutex); + list_for_each_entry(pvtpll, &rockchip_clock_pvtpll_list, list_head) { + if ((pvtpll->pvtpll_clk_id == clock_id) && pvtpll->info->pvtpll_volt_sel_adjust) { + ret = pvtpll->info->pvtpll_volt_sel_adjust(pvtpll, clock_id, volt_sel); + break; + } + } + mutex_unlock(&pvtpll_list_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(rockchip_pvtpll_volt_sel_adjust); + +static int rockchip_pvtpll_get_otp_info(struct device *dev, + struct otp_opp_info *opp_info) +{ + struct nvmem_cell *cell; + void *buf; + size_t len = 0; + + cell = nvmem_cell_get(dev, "opp-info"); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + if (IS_ERR(buf)) { + nvmem_cell_put(cell); + return PTR_ERR(buf); + } + if (len != sizeof(*opp_info)) { + kfree(buf); + nvmem_cell_put(cell); + return -EINVAL; + } + + memcpy(opp_info, buf, sizeof(*opp_info)); + kfree(buf); + nvmem_cell_put(cell); + + return 0; +} + +static void rockchip_switch_pvtpll_table(struct device *dev, + struct rockchip_clock_pvtpll *pvtpll) +{ + u8 spec = 0; + + if (!pvtpll->info->jm_table) + return; + + if (!nvmem_cell_read_u8(dev, "specification_serial_number", &spec)) { + /* M = 0xd, J = 0xa */ + if ((spec == 0xd) || (spec == 0xa)) { + pvtpll->info->table = pvtpll->info->jm_table; + pvtpll->info->table_size = pvtpll->info->jm_table_size; + } + } +} + +static void rockchip_adjust_pvtpll_by_otp(struct device *dev, + struct rockchip_clock_pvtpll *pvtpll) +{ + struct otp_opp_info opp_info = { 0 }; + struct pvtpll_table *table = pvtpll->info->table; + unsigned int size = pvtpll->info->table_size; + u32 min_freq, max_freq; + int i; + + if (rockchip_pvtpll_get_otp_info(dev, &opp_info)) + return; + + if (!opp_info.length) + return; + + dev_info(dev, "adjust opp-table by otp: min=%uM, max=%uM, length=%u\n", + opp_info.min_freq, opp_info.max_freq, opp_info.length); + + min_freq = opp_info.min_freq * MHz; + max_freq = opp_info.max_freq * MHz; + + for (i = 0; i < size; i++) { + if (table[i].rate < min_freq) + continue; + if (table[i].rate > max_freq) + continue; + + table[i].length += opp_info.length; + if (table[i].length > RK3506_PVTPLL_MAX_LENGTH) + table[i].length = RK3506_PVTPLL_MAX_LENGTH; + } +} + +static int rv1103b_pvtpll_calibrate(struct rockchip_clock_pvtpll *pvtpll) +{ + unsigned int rate, delta, length, length_ori, val, i = 0; + unsigned int length_step = pvtpll->info->calibrate_length_step; + unsigned int freq_per_step = pvtpll->info->calibrate_freq_per_step; + unsigned long target_rate = pvtpll->cur_rate / MHz; + int ret; + + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + + if (rate < target_rate) + return 0; + + /* delta < (6.25% * target_rate) */ + if ((rate - target_rate) < (target_rate >> 4)) + return 0; + + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, &val); + if (ret) + return ret; + length_ori = (val >> RV1103B_GCK_RING_LEN_SEL_OFFSET) & RV1103B_GCK_RING_LEN_SEL_MASK; + length = length_ori; + delta = rate - target_rate; + length += (delta / freq_per_step) * length_step; + val = HIWORD_UPDATE(length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + usleep_range(2000, 2100); + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + + while ((rate < target_rate) || ((rate - target_rate) > (target_rate >> 4))) { + if (i++ > 20) + break; + + if (rate > target_rate) + length += length_step; + else + length -= length_step; + if (length < length_ori) + break; + + val = HIWORD_UPDATE(length, RV1103B_GCK_RING_LEN_SEL_MASK, + RV1103B_GCK_RING_LEN_SEL_OFFSET); + ret = regmap_write(pvtpll->regmap, RV1103B_PVTPLL_GCK_LEN, val); + if (ret) + return ret; + usleep_range(2000, 2100); + ret = regmap_read(pvtpll->regmap, RV1103B_PVTPLL_GCK_CNT_AVG, &rate); + if (ret) + return ret; + } + + /* update pvtpll table */ + if (length > length_ori) { + delta = length - length_ori; + for (i = 0; i < pvtpll->info->table_size; i++) + pvtpll->info->table[i].length += delta; + } + + return 0; +} + +static void rockchip_pvtpll_calibrate(struct work_struct *work) +{ + struct rockchip_clock_pvtpll *pvtpll; + int ret; + + pvtpll = container_of(work, struct rockchip_clock_pvtpll, pvtpll_calibrate_work.work); + + if (pvtpll->info->pvtpll_calibrate) { + ret = pvtpll->info->pvtpll_calibrate(pvtpll); + if (ret) + dev_warn(pvtpll->dev, "%s: calibrate error, ret %d\n", __func__, ret); + } +} + +static const struct rockchip_clock_pvtpll_info rv1103b_core_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_core_pvtpll_table), + .table = rv1103b_core_pvtpll_table, + .pvtpll_adjust_factor = 4, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .calibrate_length_step = 2, + .calibrate_freq_per_step = 30, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, +}; + +static const struct rockchip_clock_pvtpll_info rv1103b_enc_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_enc_pvtpll_table), + .table = rv1103b_enc_pvtpll_table, + .calibrate_length_step = 8, + .calibrate_freq_per_step = 25, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, +}; + +static const struct rockchip_clock_pvtpll_info rv1103b_isp_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_isp_pvtpll_table), + .table = rv1103b_isp_pvtpll_table, +}; + +static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = { + .config = rv1103b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1103b_npu_pvtpll_table), + .table = rv1103b_npu_pvtpll_table, + .pvtpll_adjust_factor = 6, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .calibrate_length_step = 4, + .calibrate_freq_per_step = 25, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, +}; + +static const struct rockchip_clock_pvtpll_info rv1126b_aisp_pvtpll_data = { + .clk_ops = &rv1126b_pvtpll_ops, + .config = rv1126b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1126b_aisp_pvtpll_table), + .table = rv1126b_aisp_pvtpll_table, + .calibrate_length_step = 4, + .calibrate_freq_per_step = 20, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, + .mode_offset = 0xb0300, +}; + +static const struct rockchip_clock_pvtpll_info rv1126b_core_pvtpll_data = { + .config = rv1126b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1126b_core_pvtpll_table), + .table = rv1126b_core_pvtpll_table, + .pvtpll_adjust_factor = 4, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .mode_offset = 0x30300, + .is_always_on = true, +}; + +static const struct rockchip_clock_pvtpll_info rv1126b_enc_pvtpll_data = { + .config = rv1126b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1126b_enc_pvtpll_table), + .table = rv1126b_enc_pvtpll_table, + .calibrate_length_step = 8, + .calibrate_freq_per_step = 20, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, + .mode_offset = 0x80300, + .is_always_on = true, +}; + +static const struct rockchip_clock_pvtpll_info rv1126b_isp_pvtpll_data = { + .clk_ops = &rv1126b_pvtpll_ops, + .config = rv1126b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1126b_isp_pvtpll_table), + .table = rv1126b_isp_pvtpll_table, + .calibrate_length_step = 8, + .calibrate_freq_per_step = 20, + .pvtpll_calibrate = rv1103b_pvtpll_calibrate, + .mode_offset = 0x70300, +}; + +static const struct rockchip_clock_pvtpll_info rv1126b_npu_pvtpll_data = { + .clk_ops = &rv1126b_npu_pvtpll_ops, + .config = rv1126b_pvtpll_configs, + .table_size = ARRAY_SIZE(rv1126b_npu_pvtpll_table), + .table = rv1126b_npu_pvtpll_table, + .pvtpll_adjust_factor = 6, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, + .mode_offset = 0x90300, +}; + +static const struct rockchip_clock_pvtpll_info rk3506_core_pvtpll_data = { + .config = rk3506_pvtpll_configs, + .table_size = ARRAY_SIZE(rk3506_core_pvtpll_table), + .table = rk3506_core_pvtpll_table, + .jm_table_size = ARRAY_SIZE(rk3506j_core_pvtpll_table), + .jm_table = rk3506j_core_pvtpll_table, + .pvtpll_adjust_factor = 1, + .pvtpll_volt_sel_adjust = pvtpll_volt_sel_adjust_linear, +}; + +static const struct of_device_id rockchip_clock_pvtpll_match[] = { + { + .compatible = "rockchip,rv1103b-core-pvtpll", + .data = (void *)&rv1103b_core_pvtpll_data, + }, + { + .compatible = "rockchip,rv1103b-enc-pvtpll", + .data = (void *)&rv1103b_enc_pvtpll_data, + }, + { + .compatible = "rockchip,rv1103b-isp-pvtpll", + .data = (void *)&rv1103b_isp_pvtpll_data, + }, + { + .compatible = "rockchip,rv1103b-npu-pvtpll", + .data = (void *)&rv1103b_npu_pvtpll_data, + }, + { + .compatible = "rockchip,rv1126b-aisp-pvtpll", + .data = (void *)&rv1126b_aisp_pvtpll_data, + }, + { + .compatible = "rockchip,rv1126b-core-pvtpll", + .data = (void *)&rv1126b_core_pvtpll_data, + }, + { + .compatible = "rockchip,rv1126b-enc-pvtpll", + .data = (void *)&rv1126b_enc_pvtpll_data, + }, + { + .compatible = "rockchip,rv1126b-isp-pvtpll", + .data = (void *)&rv1126b_isp_pvtpll_data, + }, + { + .compatible = "rockchip,rv1126b-npu-pvtpll", + .data = (void *)&rv1126b_npu_pvtpll_data, + }, + { + .compatible = "rockchip,rk3506-core-pvtpll", + .data = (void *)&rk3506_core_pvtpll_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, rockchip_clock_pvtpll_match); + +static int rockchip_clock_pvtpll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + struct rockchip_clock_pvtpll *pvtpll; + struct of_phandle_args clkspec = { 0 }; + int error = 0; + + pvtpll = devm_kzalloc(dev, sizeof(*pvtpll), GFP_KERNEL); + if (!pvtpll) + return -ENOMEM; + + pvtpll->info = (struct rockchip_clock_pvtpll_info *)device_get_match_data(&pdev->dev); + if (!pvtpll->info) + return -EINVAL; + + pvtpll->regmap = device_node_to_regmap(np); + if (IS_ERR(pvtpll->regmap)) + return PTR_ERR(pvtpll->regmap); + + pvtpll->regmap_cru = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,cru"); + + pvtpll->dev = dev; + pvtpll->pvtpll_clk_id = UINT_MAX; + INIT_DELAYED_WORK(&pvtpll->pvtpll_calibrate_work, rockchip_pvtpll_calibrate); + + error = of_parse_phandle_with_args(np, "clocks", "#clock-cells", + 0, &clkspec); + if (!error) { + pvtpll->pvtpll_clk_id = clkspec.args[0]; + of_node_put(clkspec.np); + } + + rockchip_switch_pvtpll_table(dev, pvtpll); + + rockchip_adjust_pvtpll_by_otp(dev, pvtpll); + + platform_set_drvdata(pdev, pvtpll); + + error = clock_pvtpll_regitstor(&pdev->dev, pvtpll); + if (error) { + dev_err(&pdev->dev, "failed to register clock: %d\n", error); + return error; + } + + if (pvtpll->info->pvtpll_calibrate) + queue_delayed_work(system_freezable_wq, + &pvtpll->pvtpll_calibrate_work, + 0); + + mutex_lock(&pvtpll_list_mutex); + list_add(&pvtpll->list_head, &rockchip_clock_pvtpll_list); + mutex_unlock(&pvtpll_list_mutex); + + return 0; +} + +static int rockchip_clock_pvtpll_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + of_clk_del_provider(np); + + return 0; +} + +static int rockchip_clock_pvtpll_resume(struct device *dev) +{ + struct rockchip_clock_pvtpll *pvtpll = dev_get_drvdata(dev); + struct pvtpll_table *table; + + if (!pvtpll->info->is_always_on) + return 0; + + table = rockchip_get_pvtpll_settings(pvtpll, pvtpll->cur_rate); + if (!table) + return 0; + + return pvtpll->info->config(pvtpll, table); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_clock_pvtpll_pm_ops, NULL, + rockchip_clock_pvtpll_resume); + +static struct platform_driver rockchip_clock_pvtpll_driver = { + .driver = { + .name = "rockchip-clcok-pvtpll", + .pm = pm_sleep_ptr(&rockchip_clock_pvtpll_pm_ops), + .of_match_table = rockchip_clock_pvtpll_match, + }, + .probe = rockchip_clock_pvtpll_probe, + .remove = rockchip_clock_pvtpll_remove, +}; + +module_platform_driver(rockchip_clock_pvtpll_driver); + +MODULE_DESCRIPTION("Rockchip Clock Pvtpll Driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-10-20 17:28 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-20 2:37 [PATCH v3 0/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 1/5] clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 2/5] dt-bindings: clock, reset: Add support for rv1126b Elaine Zhang 2025-10-20 17:27 ` Conor Dooley 2025-10-20 2:37 ` [PATCH v3 3/5] clk: rockchip: Add clock controller for the RV1126B Elaine Zhang 2025-10-20 2:37 ` [PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll Elaine Zhang 2025-10-20 9:38 ` Diederik de Haas 2025-10-20 17:25 ` Conor Dooley 2025-10-20 17:26 ` Conor Dooley 2025-10-20 2:37 ` [PATCH v3 5/5] clk: rockchip: add support for pvtpll clk Elaine Zhang
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