* [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
@ 2024-08-01 5:44 Anshuman Khandual
2024-08-01 5:44 ` [PATCH 1/1] " Anshuman Khandual
2024-08-03 11:07 ` [PATCH 0/1] " Mark Rutland
0 siblings, 2 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-08-01 5:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
utilizes recently added macro GENMASK_U128() while also adding some helpers
such as define_field_128() and parse_bitdef_128().
This patch applies after the following series which adds GENMASK_U128()
https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/
A. Example for SysregFields128
------------------------------
SysregFields128 TTBRx_D128_EL1
Res0 127:88
Field 87:80 BADDR_HIGH
Res0 79:64
Field 63:48 ASID
Field 47:5 BADDR_LOW
Res0 4:3
Field 2:1 SKL
Field 0 CnP
EndSysregFields128
------------------------------
The above input generates the following macros
#define TTBRx_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
#define TTBRx_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
#define TTBRx_D128_EL1_BADDR_HIGH_SHIFT 80
#define TTBRx_D128_EL1_BADDR_HIGH_WIDTH 8
#define TTBRx_D128_EL1_ASID GENMASK_U128(63, 48)
#define TTBRx_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
#define TTBRx_D128_EL1_ASID_SHIFT 48
#define TTBRx_D128_EL1_ASID_WIDTH 16
#define TTBRx_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
#define TTBRx_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
#define TTBRx_D128_EL1_BADDR_LOW_SHIFT 5
#define TTBRx_D128_EL1_BADDR_LOW_WIDTH 43
#define TTBRx_D128_EL1_SKL GENMASK_U128(2, 1)
#define TTBRx_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
#define TTBRx_D128_EL1_SKL_SHIFT 1
#define TTBRx_D128_EL1_SKL_WIDTH 2
#define TTBRx_D128_EL1_CnP GENMASK_U128(0, 0)
#define TTBRx_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
#define TTBRx_D128_EL1_CnP_SHIFT 0
#define TTBRx_D128_EL1_CnP_WIDTH 1
#define TTBRx_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
#define TTBRx_D128_EL1_RES1 (UL(0))
#define TTBRx_D128_EL1_UNKN (UL(0))
B. Example Sysreg128
------------------------------
Sysreg128 TTBR1_D128_EL1 3 0 2 0 1
Res0 127:88
Field 87:80 BADDR_HIGH
Res0 79:64
Field 63:48 ASID
Field 47:5 BADDR_LOW
Res0 4:3
Field 2:1 SKL
Field 0 CnP
EndSysreg128
------------------------------
The above input generates the following macros
#define REG_TTBR1_D128_EL1 S3_0_C2_C0_1
#define SYS_TTBR1_D128_EL1 sys_reg(3, 0, 2, 0, 1)
#define SYS_TTBR1_D128_EL1_Op0 3
#define SYS_TTBR1_D128_EL1_Op1 0
#define SYS_TTBR1_D128_EL1_CRn 2
#define SYS_TTBR1_D128_EL1_CRm 0
#define SYS_TTBR1_D128_EL1_Op2 1
#define TTBR1_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
#define TTBR1_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
#define TTBR1_D128_EL1_BADDR_HIGH_SHIFT 80
#define TTBR1_D128_EL1_BADDR_HIGH_WIDTH 8
#define TTBR1_D128_EL1_ASID GENMASK_U128(63, 48)
#define TTBR1_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
#define TTBR1_D128_EL1_ASID_SHIFT 48
#define TTBR1_D128_EL1_ASID_WIDTH 16
#define TTBR1_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
#define TTBR1_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
#define TTBR1_D128_EL1_BADDR_LOW_SHIFT 5
#define TTBR1_D128_EL1_BADDR_LOW_WIDTH 43
#define TTBR1_D128_EL1_SKL GENMASK_U128(2, 1)
#define TTBR1_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
#define TTBR1_D128_EL1_SKL_SHIFT 1
#define TTBR1_D128_EL1_SKL_WIDTH 2
#define TTBR1_D128_EL1_CnP GENMASK_U128(0, 0)
#define TTBR1_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
#define TTBR1_D128_EL1_CnP_SHIFT 0
#define TTBR1_D128_EL1_CnP_WIDTH 1
#define TTBR1_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
#define TTBR1_D128_EL1_RES1 (UL(0))
#define TTBR1_D128_EL1_UNKN (UL(0))
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Anshuman Khandual (1):
arm64/tools/sysreg: Add Sysreg128/SysregFields128
arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
--
2.30.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-01 5:44 [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Anshuman Khandual
@ 2024-08-01 5:44 ` Anshuman Khandual
2024-08-03 11:12 ` Mark Rutland
2024-08-03 11:07 ` [PATCH 0/1] " Mark Rutland
1 sibling, 1 reply; 7+ messages in thread
From: Anshuman Khandual @ 2024-08-01 5:44 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
utilizes recently added macro GENMASK_U128() while also adding some helpers
such as define_field_128() and parse_bitdef_128().
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
1 file changed, 231 insertions(+)
diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index d1254a056114..a1571881d1c3 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -56,6 +56,13 @@ function define_field(reg, field, msb, lsb) {
define(reg "_" field "_WIDTH", msb - lsb + 1)
}
+function define_field_128(reg, field, msb, lsb) {
+ define(reg "_" field, "GENMASK_U128(" msb ", " lsb ")")
+ define(reg "_" field "_MASK", "GENMASK_U128(" msb ", " lsb ")")
+ define(reg "_" field "_SHIFT", lsb)
+ define(reg "_" field "_WIDTH", msb - lsb + 1)
+}
+
# Print a field _SIGNED definition for a field
function define_field_sign(reg, field, sign) {
define(reg "_" field "_SIGNED", sign)
@@ -89,6 +96,33 @@ function parse_bitdef(reg, field, bitdef, _bits)
next_bit = lsb - 1
}
+function parse_bitdef_128(reg, field, bitdef, _bits)
+{
+ if (bitdef ~ /^[0-9]+$/) {
+ msb = bitdef
+ lsb = bitdef
+ } else if (split(bitdef, _bits, ":") == 2) {
+ msb = _bits[1]
+ lsb = _bits[2]
+ } else {
+ fatal("invalid bit-range definition '" bitdef "'")
+ }
+
+
+ if (msb != next_bit)
+ fatal(reg "." field " starts at " msb " not " next_bit)
+ if (127 < msb || msb < 0)
+ fatal(reg "." field " invalid high bit in '" bitdef "'")
+ if (127 < lsb || lsb < 0)
+ fatal(reg "." field " invalid low bit in '" bitdef "'")
+ if (msb < lsb)
+ fatal(reg "." field " invalid bit-range '" bitdef "'")
+ if (low > high)
+ fatal(reg "." field " has invalid range " high "-" low)
+
+ next_bit = lsb - 1
+}
+
BEGIN {
print "#ifndef __ASM_SYSREG_DEFS_H"
print "#define __ASM_SYSREG_DEFS_H"
@@ -111,6 +145,99 @@ END {
/^$/ { next }
/^[\t ]*#/ { next }
+/^SysregFields128/ && block_current() == "Root" {
+ block_push("SysregFields128")
+
+ expect_fields(2)
+
+ reg = $2
+
+ res0 = "UL(0)"
+ res1 = "UL(0)"
+ unkn = "UL(0)"
+
+ next_bit = 127
+
+ next
+}
+
+/^EndSysregFields128/ && block_current() == "SysregFields128" {
+ if (next_bit > 0)
+ fatal("Unspecified bits in " reg)
+
+ define(reg "_RES0", "(" res0 ")")
+ define(reg "_RES1", "(" res1 ")")
+ define(reg "_UNKN", "(" unkn ")")
+ print ""
+
+ reg = null
+ res0 = null
+ res1 = null
+ unkn = null
+
+ block_pop()
+ next
+}
+
+/^Sysreg128/ && block_current() == "Root" {
+ block_push("Sysreg128")
+
+ expect_fields(7)
+
+ reg = $2
+ op0 = $3
+ op1 = $4
+ crn = $5
+ crm = $6
+ op2 = $7
+
+ res0 = "UL(0)"
+ res1 = "UL(0)"
+ unkn = "UL(0)"
+
+ define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
+ define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
+
+ define("SYS_" reg "_Op0", op0)
+ define("SYS_" reg "_Op1", op1)
+ define("SYS_" reg "_CRn", crn)
+ define("SYS_" reg "_CRm", crm)
+ define("SYS_" reg "_Op2", op2)
+
+ print ""
+
+ next_bit = 127
+
+ next
+}
+
+/^EndSysreg128/ && block_current() == "Sysreg128" {
+ if (next_bit > 0)
+ fatal("Unspecified bits in " reg)
+
+ if (res0 != null)
+ define(reg "_RES0", "(" res0 ")")
+ if (res1 != null)
+ define(reg "_RES1", "(" res1 ")")
+ if (unkn != null)
+ define(reg "_UNKN", "(" unkn ")")
+ if (res0 != null || res1 != null || unkn != null)
+ print ""
+
+ reg = null
+ op0 = null
+ op1 = null
+ crn = null
+ crm = null
+ op2 = null
+ res0 = null
+ res1 = null
+ unkn = null
+
+ block_pop()
+ next
+}
+
/^SysregFields/ && block_current() == "Root" {
block_push("SysregFields")
@@ -223,6 +350,22 @@ END {
next
}
+/^Fields/ && block_current() == "Sysreg128" {
+ expect_fields(2)
+
+ if (next_bit != 127)
+ fatal("Some fields already defined for " reg)
+
+ print "/* For " reg " fields see " $2 " */"
+ print ""
+
+ next_bit = 0
+ res0 = null
+ res1 = null
+ unkn = null
+
+ next
+}
/^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
expect_fields(2)
@@ -234,6 +377,16 @@ END {
next
}
+/^Res0/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ expect_fields(2)
+ parse_bitdef_128(reg, "RES0", $2)
+ field = "RES0_" msb "_" lsb
+
+ res0 = res0 " | GENMASK_U128(" msb ", " lsb ")"
+
+ next
+}
+
/^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
expect_fields(2)
parse_bitdef(reg, "RES1", $2)
@@ -244,6 +397,16 @@ END {
next
}
+/^Res1/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ expect_fields(2)
+ parse_bitdef_128(reg, "RES1", $2)
+ field = "RES1_" msb "_" lsb
+
+ res1 = res1 " | GENMASK_U128(" msb ", " lsb ")"
+
+ next
+}
+
/^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
expect_fields(2)
parse_bitdef(reg, "UNKN", $2)
@@ -254,6 +417,16 @@ END {
next
}
+/^Unkn/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ expect_fields(2)
+ parse_bitdef_128(reg, "UNKN", $2)
+ field = "UNKN_" msb "_" lsb
+
+ unkn = unkn " | GENMASK_U128(" msb ", " lsb ")"
+
+ next
+}
+
/^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
expect_fields(3)
field = $3
@@ -265,6 +438,17 @@ END {
next
}
+/^Field/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ expect_fields(3)
+ field = $3
+ parse_bitdef_128(reg, field, $2)
+
+ define_field_128(reg, field, msb, lsb)
+ print ""
+
+ next
+}
+
/^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
expect_fields(2)
parse_bitdef(reg, field, $2)
@@ -272,6 +456,14 @@ END {
next
}
+/^Raz/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ expect_fields(2)
+ parse_bitdef_128(reg, field, $2)
+
+ next
+}
+
+
/^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
block_push("Enum")
@@ -285,6 +477,19 @@ END {
next
}
+/^SignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef_128(reg, field, $2)
+
+ define_field_128(reg, field, msb, lsb)
+ define_field_sign(reg, field, "true")
+
+ next
+}
+
/^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
block_push("Enum")
@@ -298,6 +503,20 @@ END {
next
}
+/^UnsignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef_128(reg, field, $2)
+
+ define_field_128(reg, field, msb, lsb)
+ define_field_sign(reg, field, "false")
+
+ next
+}
+
+
/^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
block_push("Enum")
@@ -310,6 +529,18 @@ END {
next
}
+/^Enum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef_128(reg, field, $2)
+
+ define_field_128(reg, field, msb, lsb)
+
+ next
+}
+
/^EndEnum/ && block_current() == "Enum" {
field = null
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-01 5:44 [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Anshuman Khandual
2024-08-01 5:44 ` [PATCH 1/1] " Anshuman Khandual
@ 2024-08-03 11:07 ` Mark Rutland
2024-08-05 3:00 ` Anshuman Khandual
1 sibling, 1 reply; 7+ messages in thread
From: Mark Rutland @ 2024-08-03 11:07 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
On Thu, Aug 01, 2024 at 11:14:35AM +0530, Anshuman Khandual wrote:
> FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
> defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
> new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
> utilizes recently added macro GENMASK_U128() while also adding some helpers
> such as define_field_128() and parse_bitdef_128().
>
> This patch applies after the following series which adds GENMASK_U128()
>
> https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/
Is that patch merged or not? It wouod make a lot more sense to send them
together as one series.
>
> A. Example for SysregFields128
>
> ------------------------------
> SysregFields128 TTBRx_D128_EL1
> Res0 127:88
> Field 87:80 BADDR_HIGH
> Res0 79:64
> Field 63:48 ASID
> Field 47:5 BADDR_LOW
> Res0 4:3
> Field 2:1 SKL
> Field 0 CnP
> EndSysregFields128
> ------------------------------
Ok, so we get the definitions, but do we have all the other helpers we'd
need to make that useable, i.e.
* read_sysreg() and write_sysreg() variants that can use MRRS/MSRR
* Macros for assembly to use these?
* Other bitfield manipulation helpers that can operate on U128, e.g.
FIELD_GET() and FIELD_PREP() ?
Without end-to-end usage this is a bit academic. If the U128 definitions
are oainful to use from asm we might want separate hi64/lo64
definitions.
Mark.
> The above input generates the following macros
>
> #define TTBRx_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
> #define TTBRx_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
> #define TTBRx_D128_EL1_BADDR_HIGH_SHIFT 80
> #define TTBRx_D128_EL1_BADDR_HIGH_WIDTH 8
>
> #define TTBRx_D128_EL1_ASID GENMASK_U128(63, 48)
> #define TTBRx_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
> #define TTBRx_D128_EL1_ASID_SHIFT 48
> #define TTBRx_D128_EL1_ASID_WIDTH 16
>
> #define TTBRx_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
> #define TTBRx_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
> #define TTBRx_D128_EL1_BADDR_LOW_SHIFT 5
> #define TTBRx_D128_EL1_BADDR_LOW_WIDTH 43
>
> #define TTBRx_D128_EL1_SKL GENMASK_U128(2, 1)
> #define TTBRx_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
> #define TTBRx_D128_EL1_SKL_SHIFT 1
> #define TTBRx_D128_EL1_SKL_WIDTH 2
>
> #define TTBRx_D128_EL1_CnP GENMASK_U128(0, 0)
> #define TTBRx_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
> #define TTBRx_D128_EL1_CnP_SHIFT 0
> #define TTBRx_D128_EL1_CnP_WIDTH 1
>
> #define TTBRx_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
> #define TTBRx_D128_EL1_RES1 (UL(0))
> #define TTBRx_D128_EL1_UNKN (UL(0))
>
> B. Example Sysreg128
>
> ------------------------------
> Sysreg128 TTBR1_D128_EL1 3 0 2 0 1
> Res0 127:88
> Field 87:80 BADDR_HIGH
> Res0 79:64
> Field 63:48 ASID
> Field 47:5 BADDR_LOW
> Res0 4:3
> Field 2:1 SKL
> Field 0 CnP
> EndSysreg128
> ------------------------------
>
> The above input generates the following macros
>
> #define REG_TTBR1_D128_EL1 S3_0_C2_C0_1
> #define SYS_TTBR1_D128_EL1 sys_reg(3, 0, 2, 0, 1)
> #define SYS_TTBR1_D128_EL1_Op0 3
> #define SYS_TTBR1_D128_EL1_Op1 0
> #define SYS_TTBR1_D128_EL1_CRn 2
> #define SYS_TTBR1_D128_EL1_CRm 0
> #define SYS_TTBR1_D128_EL1_Op2 1
>
> #define TTBR1_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
> #define TTBR1_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
> #define TTBR1_D128_EL1_BADDR_HIGH_SHIFT 80
> #define TTBR1_D128_EL1_BADDR_HIGH_WIDTH 8
>
> #define TTBR1_D128_EL1_ASID GENMASK_U128(63, 48)
> #define TTBR1_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
> #define TTBR1_D128_EL1_ASID_SHIFT 48
> #define TTBR1_D128_EL1_ASID_WIDTH 16
>
> #define TTBR1_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
> #define TTBR1_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
> #define TTBR1_D128_EL1_BADDR_LOW_SHIFT 5
> #define TTBR1_D128_EL1_BADDR_LOW_WIDTH 43
>
> #define TTBR1_D128_EL1_SKL GENMASK_U128(2, 1)
> #define TTBR1_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
> #define TTBR1_D128_EL1_SKL_SHIFT 1
> #define TTBR1_D128_EL1_SKL_WIDTH 2
>
> #define TTBR1_D128_EL1_CnP GENMASK_U128(0, 0)
> #define TTBR1_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
> #define TTBR1_D128_EL1_CnP_SHIFT 0
> #define TTBR1_D128_EL1_CnP_WIDTH 1
>
> #define TTBR1_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
> #define TTBR1_D128_EL1_RES1 (UL(0))
> #define TTBR1_D128_EL1_UNKN (UL(0))
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Anshuman Khandual (1):
> arm64/tools/sysreg: Add Sysreg128/SysregFields128
>
> arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
> 1 file changed, 231 insertions(+)
>
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-01 5:44 ` [PATCH 1/1] " Anshuman Khandual
@ 2024-08-03 11:12 ` Mark Rutland
2024-08-05 3:27 ` Anshuman Khandual
0 siblings, 1 reply; 7+ messages in thread
From: Mark Rutland @ 2024-08-03 11:12 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
On Thu, Aug 01, 2024 at 11:14:36AM +0530, Anshuman Khandual wrote:
> FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
> defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
> new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
> utilizes recently added macro GENMASK_U128() while also adding some helpers
> such as define_field_128() and parse_bitdef_128().
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
> 1 file changed, 231 insertions(+)
Having Sysreg128 and SysregFields128 sounds reasonable, though I suspect
we can share more code with Sysreg and SysregFields (e.g. by always
using GENMASK128() even for regular SYsreg and SysregFIilds).
Regardless of this patch in particular, I think we want to see some
end-to-end usage (i.e. some actual bit definitions, along with asm and C
code that uses these definitions) so that we're confident this is the
right way to capture these definitions.
Sending this piecemeal, separate to those elements and sepate to
GENMASK_U128() makes this very painful to review effectively. Please
combine those elements into a single series so that reviewers can see
the entire picture.
Mark.
> diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
> index d1254a056114..a1571881d1c3 100755
> --- a/arch/arm64/tools/gen-sysreg.awk
> +++ b/arch/arm64/tools/gen-sysreg.awk
> @@ -56,6 +56,13 @@ function define_field(reg, field, msb, lsb) {
> define(reg "_" field "_WIDTH", msb - lsb + 1)
> }
>
> +function define_field_128(reg, field, msb, lsb) {
> + define(reg "_" field, "GENMASK_U128(" msb ", " lsb ")")
> + define(reg "_" field "_MASK", "GENMASK_U128(" msb ", " lsb ")")
> + define(reg "_" field "_SHIFT", lsb)
> + define(reg "_" field "_WIDTH", msb - lsb + 1)
> +}
> +
> # Print a field _SIGNED definition for a field
> function define_field_sign(reg, field, sign) {
> define(reg "_" field "_SIGNED", sign)
> @@ -89,6 +96,33 @@ function parse_bitdef(reg, field, bitdef, _bits)
> next_bit = lsb - 1
> }
>
> +function parse_bitdef_128(reg, field, bitdef, _bits)
> +{
> + if (bitdef ~ /^[0-9]+$/) {
> + msb = bitdef
> + lsb = bitdef
> + } else if (split(bitdef, _bits, ":") == 2) {
> + msb = _bits[1]
> + lsb = _bits[2]
> + } else {
> + fatal("invalid bit-range definition '" bitdef "'")
> + }
> +
> +
> + if (msb != next_bit)
> + fatal(reg "." field " starts at " msb " not " next_bit)
> + if (127 < msb || msb < 0)
> + fatal(reg "." field " invalid high bit in '" bitdef "'")
> + if (127 < lsb || lsb < 0)
> + fatal(reg "." field " invalid low bit in '" bitdef "'")
> + if (msb < lsb)
> + fatal(reg "." field " invalid bit-range '" bitdef "'")
> + if (low > high)
> + fatal(reg "." field " has invalid range " high "-" low)
> +
> + next_bit = lsb - 1
> +}
> +
> BEGIN {
> print "#ifndef __ASM_SYSREG_DEFS_H"
> print "#define __ASM_SYSREG_DEFS_H"
> @@ -111,6 +145,99 @@ END {
> /^$/ { next }
> /^[\t ]*#/ { next }
>
> +/^SysregFields128/ && block_current() == "Root" {
> + block_push("SysregFields128")
> +
> + expect_fields(2)
> +
> + reg = $2
> +
> + res0 = "UL(0)"
> + res1 = "UL(0)"
> + unkn = "UL(0)"
> +
> + next_bit = 127
> +
> + next
> +}
> +
> +/^EndSysregFields128/ && block_current() == "SysregFields128" {
> + if (next_bit > 0)
> + fatal("Unspecified bits in " reg)
> +
> + define(reg "_RES0", "(" res0 ")")
> + define(reg "_RES1", "(" res1 ")")
> + define(reg "_UNKN", "(" unkn ")")
> + print ""
> +
> + reg = null
> + res0 = null
> + res1 = null
> + unkn = null
> +
> + block_pop()
> + next
> +}
> +
> +/^Sysreg128/ && block_current() == "Root" {
> + block_push("Sysreg128")
> +
> + expect_fields(7)
> +
> + reg = $2
> + op0 = $3
> + op1 = $4
> + crn = $5
> + crm = $6
> + op2 = $7
> +
> + res0 = "UL(0)"
> + res1 = "UL(0)"
> + unkn = "UL(0)"
> +
> + define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
> + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
> +
> + define("SYS_" reg "_Op0", op0)
> + define("SYS_" reg "_Op1", op1)
> + define("SYS_" reg "_CRn", crn)
> + define("SYS_" reg "_CRm", crm)
> + define("SYS_" reg "_Op2", op2)
> +
> + print ""
> +
> + next_bit = 127
> +
> + next
> +}
> +
> +/^EndSysreg128/ && block_current() == "Sysreg128" {
> + if (next_bit > 0)
> + fatal("Unspecified bits in " reg)
> +
> + if (res0 != null)
> + define(reg "_RES0", "(" res0 ")")
> + if (res1 != null)
> + define(reg "_RES1", "(" res1 ")")
> + if (unkn != null)
> + define(reg "_UNKN", "(" unkn ")")
> + if (res0 != null || res1 != null || unkn != null)
> + print ""
> +
> + reg = null
> + op0 = null
> + op1 = null
> + crn = null
> + crm = null
> + op2 = null
> + res0 = null
> + res1 = null
> + unkn = null
> +
> + block_pop()
> + next
> +}
> +
> /^SysregFields/ && block_current() == "Root" {
> block_push("SysregFields")
>
> @@ -223,6 +350,22 @@ END {
> next
> }
>
> +/^Fields/ && block_current() == "Sysreg128" {
> + expect_fields(2)
> +
> + if (next_bit != 127)
> + fatal("Some fields already defined for " reg)
> +
> + print "/* For " reg " fields see " $2 " */"
> + print ""
> +
> + next_bit = 0
> + res0 = null
> + res1 = null
> + unkn = null
> +
> + next
> +}
>
> /^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> expect_fields(2)
> @@ -234,6 +377,16 @@ END {
> next
> }
>
> +/^Res0/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + expect_fields(2)
> + parse_bitdef_128(reg, "RES0", $2)
> + field = "RES0_" msb "_" lsb
> +
> + res0 = res0 " | GENMASK_U128(" msb ", " lsb ")"
> +
> + next
> +}
> +
> /^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> expect_fields(2)
> parse_bitdef(reg, "RES1", $2)
> @@ -244,6 +397,16 @@ END {
> next
> }
>
> +/^Res1/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + expect_fields(2)
> + parse_bitdef_128(reg, "RES1", $2)
> + field = "RES1_" msb "_" lsb
> +
> + res1 = res1 " | GENMASK_U128(" msb ", " lsb ")"
> +
> + next
> +}
> +
> /^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> expect_fields(2)
> parse_bitdef(reg, "UNKN", $2)
> @@ -254,6 +417,16 @@ END {
> next
> }
>
> +/^Unkn/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + expect_fields(2)
> + parse_bitdef_128(reg, "UNKN", $2)
> + field = "UNKN_" msb "_" lsb
> +
> + unkn = unkn " | GENMASK_U128(" msb ", " lsb ")"
> +
> + next
> +}
> +
> /^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> expect_fields(3)
> field = $3
> @@ -265,6 +438,17 @@ END {
> next
> }
>
> +/^Field/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + expect_fields(3)
> + field = $3
> + parse_bitdef_128(reg, field, $2)
> +
> + define_field_128(reg, field, msb, lsb)
> + print ""
> +
> + next
> +}
> +
> /^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> expect_fields(2)
> parse_bitdef(reg, field, $2)
> @@ -272,6 +456,14 @@ END {
> next
> }
>
> +/^Raz/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + expect_fields(2)
> + parse_bitdef_128(reg, field, $2)
> +
> + next
> +}
> +
> +
> /^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> block_push("Enum")
>
> @@ -285,6 +477,19 @@ END {
> next
> }
>
> +/^SignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + block_push("Enum")
> +
> + expect_fields(3)
> + field = $3
> + parse_bitdef_128(reg, field, $2)
> +
> + define_field_128(reg, field, msb, lsb)
> + define_field_sign(reg, field, "true")
> +
> + next
> +}
> +
> /^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> block_push("Enum")
>
> @@ -298,6 +503,20 @@ END {
> next
> }
>
> +/^UnsignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + block_push("Enum")
> +
> + expect_fields(3)
> + field = $3
> + parse_bitdef_128(reg, field, $2)
> +
> + define_field_128(reg, field, msb, lsb)
> + define_field_sign(reg, field, "false")
> +
> + next
> +}
> +
> +
> /^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
> block_push("Enum")
>
> @@ -310,6 +529,18 @@ END {
> next
> }
>
> +/^Enum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") {
> + block_push("Enum")
> +
> + expect_fields(3)
> + field = $3
> + parse_bitdef_128(reg, field, $2)
> +
> + define_field_128(reg, field, msb, lsb)
> +
> + next
> +}
> +
> /^EndEnum/ && block_current() == "Enum" {
>
> field = null
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-03 11:07 ` [PATCH 0/1] " Mark Rutland
@ 2024-08-05 3:00 ` Anshuman Khandual
2024-08-06 13:28 ` Mark Rutland
0 siblings, 1 reply; 7+ messages in thread
From: Anshuman Khandual @ 2024-08-05 3:00 UTC (permalink / raw)
To: Mark Rutland
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
On 8/3/24 16:37, Mark Rutland wrote:
> On Thu, Aug 01, 2024 at 11:14:35AM +0530, Anshuman Khandual wrote:
>> FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
>> defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
>> new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
>> utilizes recently added macro GENMASK_U128() while also adding some helpers
>> such as define_field_128() and parse_bitdef_128().
>>
>> This patch applies after the following series which adds GENMASK_U128()
>>
>> https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/
>
> Is that patch merged or not? It wouod make a lot more sense to send them
> together as one series.
The latest series [1] here has been reviewed and merged in bitmap-for-next
tree for testing purpose. Also there has been an additional patch [2] just
to keep the GENMASK_U128() helpers inside !__ASSEMBLY__ guard.
[1] https://lore.kernel.org/all/20240801071646.682731-1-anshuman.khandual@arm.com/
[2] https://lore.kernel.org/all/20240803133753.1598137-1-yury.norov@gmail.com/
GENMASK_U128() series could have been part of this series, although 128 bit
mask creation seems generic enough to stand on its own.
>
>>
>> A. Example for SysregFields128
>>
>> ------------------------------
>> SysregFields128 TTBRx_D128_EL1
>> Res0 127:88
>> Field 87:80 BADDR_HIGH
>> Res0 79:64
>> Field 63:48 ASID
>> Field 47:5 BADDR_LOW
>> Res0 4:3
>> Field 2:1 SKL
>> Field 0 CnP
>> EndSysregFields128
>> ------------------------------
>
> Ok, so we get the definitions, but do we have all the other helpers we'd
> need to make that useable, i.e.
The first objective was to get the definitions right, so that they could
be stored in the new gcc __unit128 data type.
>
> * read_sysreg() and write_sysreg() variants that can use MRRS/MSRR
>
> * Macros for assembly to use these?
>
> * Other bitfield manipulation helpers that can operate on U128, e.g.
> FIELD_GET() and FIELD_PREP() ?
These are still work in progress, but will share when available.
>
> Without end-to-end usage this is a bit academic. If the U128 definitions
> are oainful to use from asm we might want separate hi64/lo64
> definitions.
Right, U128 definitions are difficult to use in asm code because they way
gcc compiler deals with 128 bit data types. Should the separate hi64/lo64
definitions be generic or platform specific without adding them to kernel
bitops ?
>
> Mark.
>
>> The above input generates the following macros
>>
>> #define TTBRx_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
>> #define TTBRx_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
>> #define TTBRx_D128_EL1_BADDR_HIGH_SHIFT 80
>> #define TTBRx_D128_EL1_BADDR_HIGH_WIDTH 8
>>
>> #define TTBRx_D128_EL1_ASID GENMASK_U128(63, 48)
>> #define TTBRx_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
>> #define TTBRx_D128_EL1_ASID_SHIFT 48
>> #define TTBRx_D128_EL1_ASID_WIDTH 16
>>
>> #define TTBRx_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
>> #define TTBRx_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
>> #define TTBRx_D128_EL1_BADDR_LOW_SHIFT 5
>> #define TTBRx_D128_EL1_BADDR_LOW_WIDTH 43
>>
>> #define TTBRx_D128_EL1_SKL GENMASK_U128(2, 1)
>> #define TTBRx_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
>> #define TTBRx_D128_EL1_SKL_SHIFT 1
>> #define TTBRx_D128_EL1_SKL_WIDTH 2
>>
>> #define TTBRx_D128_EL1_CnP GENMASK_U128(0, 0)
>> #define TTBRx_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
>> #define TTBRx_D128_EL1_CnP_SHIFT 0
>> #define TTBRx_D128_EL1_CnP_WIDTH 1
>>
>> #define TTBRx_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
>> #define TTBRx_D128_EL1_RES1 (UL(0))
>> #define TTBRx_D128_EL1_UNKN (UL(0))
>>
>> B. Example Sysreg128
>>
>> ------------------------------
>> Sysreg128 TTBR1_D128_EL1 3 0 2 0 1
>> Res0 127:88
>> Field 87:80 BADDR_HIGH
>> Res0 79:64
>> Field 63:48 ASID
>> Field 47:5 BADDR_LOW
>> Res0 4:3
>> Field 2:1 SKL
>> Field 0 CnP
>> EndSysreg128
>> ------------------------------
>>
>> The above input generates the following macros
>>
>> #define REG_TTBR1_D128_EL1 S3_0_C2_C0_1
>> #define SYS_TTBR1_D128_EL1 sys_reg(3, 0, 2, 0, 1)
>> #define SYS_TTBR1_D128_EL1_Op0 3
>> #define SYS_TTBR1_D128_EL1_Op1 0
>> #define SYS_TTBR1_D128_EL1_CRn 2
>> #define SYS_TTBR1_D128_EL1_CRm 0
>> #define SYS_TTBR1_D128_EL1_Op2 1
>>
>> #define TTBR1_D128_EL1_BADDR_HIGH GENMASK_U128(87, 80)
>> #define TTBR1_D128_EL1_BADDR_HIGH_MASK GENMASK_U128(87, 80)
>> #define TTBR1_D128_EL1_BADDR_HIGH_SHIFT 80
>> #define TTBR1_D128_EL1_BADDR_HIGH_WIDTH 8
>>
>> #define TTBR1_D128_EL1_ASID GENMASK_U128(63, 48)
>> #define TTBR1_D128_EL1_ASID_MASK GENMASK_U128(63, 48)
>> #define TTBR1_D128_EL1_ASID_SHIFT 48
>> #define TTBR1_D128_EL1_ASID_WIDTH 16
>>
>> #define TTBR1_D128_EL1_BADDR_LOW GENMASK_U128(47, 5)
>> #define TTBR1_D128_EL1_BADDR_LOW_MASK GENMASK_U128(47, 5)
>> #define TTBR1_D128_EL1_BADDR_LOW_SHIFT 5
>> #define TTBR1_D128_EL1_BADDR_LOW_WIDTH 43
>>
>> #define TTBR1_D128_EL1_SKL GENMASK_U128(2, 1)
>> #define TTBR1_D128_EL1_SKL_MASK GENMASK_U128(2, 1)
>> #define TTBR1_D128_EL1_SKL_SHIFT 1
>> #define TTBR1_D128_EL1_SKL_WIDTH 2
>>
>> #define TTBR1_D128_EL1_CnP GENMASK_U128(0, 0)
>> #define TTBR1_D128_EL1_CnP_MASK GENMASK_U128(0, 0)
>> #define TTBR1_D128_EL1_CnP_SHIFT 0
>> #define TTBR1_D128_EL1_CnP_WIDTH 1
>>
>> #define TTBR1_D128_EL1_RES0 (UL(0) | GENMASK_U128(127, 88) | GENMASK_U128(79, 64) | GENMASK_U128(4, 3))
>> #define TTBR1_D128_EL1_RES1 (UL(0))
>> #define TTBR1_D128_EL1_UNKN (UL(0))
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>>
>> Anshuman Khandual (1):
>> arm64/tools/sysreg: Add Sysreg128/SysregFields128
>>
>> arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
>> 1 file changed, 231 insertions(+)
>>
>> --
>> 2.30.2
>>
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-03 11:12 ` Mark Rutland
@ 2024-08-05 3:27 ` Anshuman Khandual
0 siblings, 0 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-08-05 3:27 UTC (permalink / raw)
To: Mark Rutland
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
On 8/3/24 16:42, Mark Rutland wrote:
> On Thu, Aug 01, 2024 at 11:14:36AM +0530, Anshuman Khandual wrote:
>> FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
>> defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
>> new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
>> utilizes recently added macro GENMASK_U128() while also adding some helpers
>> such as define_field_128() and parse_bitdef_128().
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Brown <broonie@kernel.org>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>> arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++
>> 1 file changed, 231 insertions(+)
> Having Sysreg128 and SysregFields128 sounds reasonable, though I suspect
> we can share more code with Sysreg and SysregFields (e.g. by always
> using GENMASK128() even for regular SYsreg and SysregFIilds).
GENMASK_U128() should deliver same bit masks that could be used instead
of earlier GENMASK_ULL() bit masks. Sounds good.
>
> Regardless of this patch in particular, I think we want to see some
> end-to-end usage (i.e. some actual bit definitions, along with asm and C
> code that uses these definitions) so that we're confident this is the
> right way to capture these definitions.
>
> Sending this piecemeal, separate to those elements and sepate to
> GENMASK_U128() makes this very painful to review effectively. Please
> combine those elements into a single series so that reviewers can see
> the entire picture.
Sure, will try and combine the elements as as much possible.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128
2024-08-05 3:00 ` Anshuman Khandual
@ 2024-08-06 13:28 ` Mark Rutland
0 siblings, 0 replies; 7+ messages in thread
From: Mark Rutland @ 2024-08-06 13:28 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linux-arm-kernel, Catalin Marinas, Will Deacon, Mark Brown,
linux-kernel
On Mon, Aug 05, 2024 at 08:30:48AM +0530, Anshuman Khandual wrote:
> On 8/3/24 16:37, Mark Rutland wrote:
> > On Thu, Aug 01, 2024 at 11:14:35AM +0530, Anshuman Khandual wrote:
> >> FEAT_SYSREG128 enables 128 bit wide system registers which also need to be
> >> defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two
> >> new field types i.e Sysreg128 and SysregFields128 for that same purpose. It
> >> utilizes recently added macro GENMASK_U128() while also adding some helpers
> >> such as define_field_128() and parse_bitdef_128().
> >>
> >> This patch applies after the following series which adds GENMASK_U128()
> >>
> >> https://lore.kernel.org/all/20240725054808.286708-1-anshuman.khandual@arm.com/
> >
> > Is that patch merged or not? It wouod make a lot more sense to send them
> > together as one series.
>
> The latest series [1] here has been reviewed and merged in bitmap-for-next
> tree for testing purpose. Also there has been an additional patch [2] just
> to keep the GENMASK_U128() helpers inside !__ASSEMBLY__ guard.
>
> [1] https://lore.kernel.org/all/20240801071646.682731-1-anshuman.khandual@arm.com/
> [2] https://lore.kernel.org/all/20240803133753.1598137-1-yury.norov@gmail.com/
>
> GENMASK_U128() series could have been part of this series, although 128 bit
> mask creation seems generic enough to stand on its own.
>
> >> A. Example for SysregFields128
> >>
> >> ------------------------------
> >> SysregFields128 TTBRx_D128_EL1
> >> Res0 127:88
> >> Field 87:80 BADDR_HIGH
> >> Res0 79:64
> >> Field 63:48 ASID
> >> Field 47:5 BADDR_LOW
> >> Res0 4:3
> >> Field 2:1 SKL
> >> Field 0 CnP
> >> EndSysregFields128
> >> ------------------------------
> >
> > Ok, so we get the definitions, but do we have all the other helpers we'd
> > need to make that useable, i.e.
>
> The first objective was to get the definitions right, so that they could
> be stored in the new gcc __unit128 data type.
I can understand that being the first thing you do while prototyping,
but upstream we don't even know that we *want* to use __unit128, becuase
whether that is desireable depends on how we can *consume* the values.
> > * read_sysreg() and write_sysreg() variants that can use MRRS/MSRR
> >
> > * Macros for assembly to use these?
> >
> > * Other bitfield manipulation helpers that can operate on U128, e.g.
> > FIELD_GET() and FIELD_PREP() ?
>
> These are still work in progress, but will share when available.
>
> > Without end-to-end usage this is a bit academic. If the U128 definitions
> > are oainful to use from asm we might want separate hi64/lo64
> > definitions.
>
> Right, U128 definitions are difficult to use in asm code because they way
> gcc compiler deals with 128 bit data types.
I meant that this is likely to be painful even for plain where the
compiler is not involved, because the *assembler* cannot handle bits
127:64, e.g.
| [mark@gravadlaks:~]% cat test.S
| .if ((1 << 32) >> 32) != 1
| .error "Oh no! absolute expressions are evaluated as 32-bits or less"
| .endif
|
| .if ((((1 << 32) << 32) >> 32) >> 32) != 1
| .error "Oh no! absolute expressions are evaluated as 64-bits or less"
| .endif
| [mark@gravadlaks:~]% as test.S -o test.o
| test.S: Assembler messages:
| test.S:6: Error: Oh no! absolute expressions are evaluated as 64-bits or less
... and so either we have to handle the hi64/lo64 halves explicitly when
generating definitions, or we need the assembler to gain support for
128-bit absolute expressions.
... and if we go for the former, we don't need U128 at all; hence why it
would have made more sense to do this in one go.
> Should the separate hi64/lo64 definitions be generic or platform
> specific without adding them to kernel bitops ?
I don't understand that question here. I was describing the problem of
the bit definitions, not operations operating upon those definitions.
Mark.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-08-06 13:29 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-01 5:44 [PATCH 0/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Anshuman Khandual
2024-08-01 5:44 ` [PATCH 1/1] " Anshuman Khandual
2024-08-03 11:12 ` Mark Rutland
2024-08-05 3:27 ` Anshuman Khandual
2024-08-03 11:07 ` [PATCH 0/1] " Mark Rutland
2024-08-05 3:00 ` Anshuman Khandual
2024-08-06 13:28 ` Mark Rutland
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