Re: [PATCH 02/39] drm/imx: Add i.MX95 Display Controller DomainBlend

[Frank Li <Frank.li@nxp.com>]

On Sat, Oct 11, 2025 at 06:51:17PM +0200, Marek Vasut wrote:
> i.MX95 Display Controller display engine consists of all processing
> units that operate in a display clock domain. Add DomainBlend driver
> which is specific to i.MX95 and required to get any display output on
> that SoC.
>
> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Liu Ying <victor.liu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: imx@lists.linux.dev
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
>  drivers/gpu/drm/imx/dc/Makefile  |   2 +-
>  drivers/gpu/drm/imx/dc/dc-crtc.c |   2 +
>  drivers/gpu/drm/imx/dc/dc-db.c   | 226 +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/imx/dc/dc-de.c   |   2 +
>  drivers/gpu/drm/imx/dc/dc-de.h   |  11 ++
>  drivers/gpu/drm/imx/dc/dc-drv.c  |   1 +
>  drivers/gpu/drm/imx/dc/dc-drv.h  |   3 +
>  drivers/gpu/drm/imx/dc/dc-kms.h  |   4 +
>  8 files changed, 250 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/imx/dc/dc-db.c
>
> diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makefile
> index b9d33c074984a..20386e4082e56 100644
> --- a/drivers/gpu/drm/imx/dc/Makefile
> +++ b/drivers/gpu/drm/imx/dc/Makefile
> @@ -1,6 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>
> -imx8-dc-drm-objs := dc-cf.o dc-crtc.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o \
> +imx8-dc-drm-objs := dc-cf.o dc-crtc.o dc-db.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o \
>  		    dc-fu.o dc-fw.o dc-ic.o dc-kms.o dc-lb.o dc-pe.o \
>  		    dc-plane.o dc-tc.o
>
...
> +
> +#include "dc-drv.h"
> +#include "dc-pe.h"
> +
> +#define PIXENGCFG_DYNAMIC			0x8
> +#define  PIXENGCFG_DYNAMIC_PRIM_SEL_MASK	GENMASK(5, 0)
> +#define  PIXENGCFG_DYNAMIC_PRIM_SEL(x)		\
> +		FIELD_PREP(PIXENGCFG_DYNAMIC_PRIM_SEL_MASK, (x))
> +#define  PIXENGCFG_DYNAMIC_SEC_SEL_MASK		GENMASK(13, 8)
> +#define  PIXENGCFG_DYNAMIC_SEC_SEL(x)		\
> +		FIELD_PREP(PIXENGCFG_DYNAMIC_SEC_SEL_MASK, (x))
> +
> +#define STATICCONTROL				0x8
> +#define  SHDTOKSEL_MASK				GENMASK(6, 4)
> +#define  SHDTOKSEL(x)				FIELD_PREP(SHDTOKSEL_MASK, (x))
> +#define  SHDLDSEL_MASK				GENMASK(3, 1)
> +#define  SHDLDSEL(x)				FIELD_PREP(SHDLDSEL_MASK, (x))

Can you keep bit fields as consistent order,  from 31..0 or 0..31.

> +
> +#define CONTROL					0xc
> +#define  SHDTOKGEN				BIT(0)
> +
...
> +
> +enum dc_db_blend_func {
> +	DC_DOMAINBLEND_BLEND_ZERO,
> +	DC_DOMAINBLEND_BLEND_ONE,
> +	DC_DOMAINBLEND_BLEND_PRIM_ALPHA,
> +	DC_DOMAINBLEND_BLEND_ONE_MINUS_PRIM_ALPHA,
> +	DC_DOMAINBLEND_BLEND_SEC_ALPHA,
> +	DC_DOMAINBLEND_BLEND_ONE_MINUS_SEC_ALPHA,
> +	DC_DOMAINBLEND_BLEND_CONST_ALPHA,
> +	DC_DOMAINBLEND_BLEND_ONE_MINUS_CONST_ALPHA,
> +};
> +
> +enum dc_db_shadow_sel {
> +	SW = 0x4,
> +	SW_PRIM = 0x5,
> +	SW_SEC = 0x6,
> +};
> +
> +static const struct dc_subdev_info dc_db_info[] = {
> +	{ .reg_start = 0x4b6a0000, .id = 0, },
> +	{ .reg_start = 0x4b720000, .id = 1, },
> +};

Not sure why need map register address to id? Does graphic link or use
dt cells pass it as argument.

I have find use .id at this driver.

> +
> +static const struct regmap_range dc_db_regmap_ranges[] = {
> +	regmap_reg_range(STATICCONTROL, BLENDCONTROL),
> +};
> +
...
> +
> +static inline void dc_db_enable_shden(struct dc_db *db)
> +{
> +	regmap_write_bits(db->reg_cfg, STATICCONTROL, SHDEN, SHDEN);
> +}
> +
> +static inline void dc_db_shdtoksel(struct dc_db *db, enum dc_db_shadow_sel sel)
> +{
> +	regmap_write_bits(db->reg_cfg, STATICCONTROL, SHDTOKSEL_MASK,
> +			  SHDTOKSEL(sel));
> +}
> +
> +static inline void dc_db_shdldsel(struct dc_db *db, enum dc_db_shadow_sel sel)
> +{
> +	regmap_write_bits(db->reg_cfg, STATICCONTROL, SHDLDSEL_MASK,
> +			  SHDLDSEL(sel));
> +}
> +
> +void dc_db_shdtokgen(struct dc_db *db)
> +{
> +	regmap_write(db->reg_cfg, CONTROL, SHDTOKGEN);
> +}
> +
> +static void dc_db_mode(struct dc_db *db, enum dc_db_mode mode)
> +{
> +	regmap_write(db->reg_cfg, MODECONTROL, mode);
> +}
> +
> +static inline void dc_db_alphamaskmode_disable(struct dc_db *db)
> +{
> +	regmap_write_bits(db->reg_cfg, ALPHACONTROL, ALPHAMASKENABLE, 0);
> +}

This helper function just write value to one register, not helper much
at all.

> +
> +static inline void dc_db_blendcontrol(struct dc_db *db)
> +{
> +	u32 val = PRIM_A_BLD_FUNC(DC_DOMAINBLEND_BLEND_ZERO) |
> +		  SEC_A_BLD_FUNC(DC_DOMAINBLEND_BLEND_ZERO) |
> +		  PRIM_C_BLD_FUNC(DC_DOMAINBLEND_BLEND_ZERO) |
> +		  SEC_C_BLD_FUNC(DC_DOMAINBLEND_BLEND_ONE);
> +
> +	regmap_write(db->reg_cfg, BLENDCONTROL, val);
> +}
> +
> +void dc_db_init(struct dc_db *db)
> +{
> +	dc_db_enable_shden(db);
> +	dc_db_shdtoksel(db, SW);
> +	dc_db_shdldsel(db, SW);
> +	dc_db_mode(db, DB_PRIMARY);
> +	dc_db_alphamaskmode_disable(db);
> +	dc_db_blendcontrol(db);
> +}
> +
...
>
> +struct dc_db {
> +	struct device *dev;
> +	struct regmap *reg_cfg;
> +	int id;

where actually use this id?

Frank

> +};
> +
>  struct dc_fg {
>  	struct device *dev;
>  	struct regmap *reg;
> @@ -30,6 +36,7 @@ struct dc_tc {
>  struct dc_de {
>  	struct device *dev;
>  	struct regmap *reg_top;
> +	struct dc_db *db;
>  	struct dc_fg *fg;
>  	struct dc_tc *tc;
>  	int irq_shdload;
> @@ -37,6 +44,10 @@ struct dc_de {
>  	int irq_seqcomplete;
>  };
>
> +/* Domain Blend Unit */
> +void dc_db_init(struct dc_db *db);
> +void dc_db_shdtokgen(struct dc_db *db);
> +
>  /* Frame Generator Unit */
>  void dc_fg_cfg_videomode(struct dc_fg *fg, struct drm_display_mode *m);
>  void dc_fg_enable(struct dc_fg *fg);
> diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-drv.c
> index 04f021d2d6cfc..f108964bf89f4 100644
> --- a/drivers/gpu/drm/imx/dc/dc-drv.c
> +++ b/drivers/gpu/drm/imx/dc/dc-drv.c
> @@ -263,6 +263,7 @@ static struct platform_driver dc_driver = {
>
>  static struct platform_driver * const dc_drivers[] = {
>  	&dc_cf_driver,
> +	&dc_db_driver,
>  	&dc_de_driver,
>  	&dc_ed_driver,
>  	&dc_fg_driver,
> diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-drv.h
> index eb61b8c762693..17ce2d748262b 100644
> --- a/drivers/gpu/drm/imx/dc/dc-drv.h
> +++ b/drivers/gpu/drm/imx/dc/dc-drv.h
> @@ -40,6 +40,8 @@ struct dc_drm_device {
>  	struct dc_ed *ed_safe[DC_DISPLAYS];
>  	/** @ed_cont: extdst list(content stream) */
>  	struct dc_ed *ed_cont[DC_DISPLAYS];
> +	/** @lb: domainblend list */
> +	struct dc_db *db[DC_DISPLAYS];
>  	/** @fg: framegen list */
>  	struct dc_fg *fg[DC_DISPLAYS];
>  	/** @fu_disp: fetchunit list(used by display engine) */
> @@ -71,6 +73,7 @@ void dc_kms_uninit(struct dc_drm_device *dc_drm);
>  int dc_plane_init(struct dc_drm_device *dc_drm, struct dc_plane *dc_plane);
>
>  extern struct platform_driver dc_cf_driver;
> +extern struct platform_driver dc_db_driver;
>  extern struct platform_driver dc_de_driver;
>  extern struct platform_driver dc_ed_driver;
>  extern struct platform_driver dc_fg_driver;
> diff --git a/drivers/gpu/drm/imx/dc/dc-kms.h b/drivers/gpu/drm/imx/dc/dc-kms.h
> index cd7860eff986a..3e61dbb87afe7 100644
> --- a/drivers/gpu/drm/imx/dc/dc-kms.h
> +++ b/drivers/gpu/drm/imx/dc/dc-kms.h
> @@ -48,6 +48,8 @@ struct dc_crtc {
>  	struct dc_ed *ed_cont;
>  	/** @ed_safe: safety stream extdst */
>  	struct dc_ed *ed_safe;
> +	/** @db: domain blend */
> +	struct dc_db *db;
>  	/** @fg: framegen */
>  	struct dc_fg *fg;
>  	/**
> @@ -122,6 +124,8 @@ struct dc_plane {
>  	struct dc_fu *fu;
>  	/** @cf: content stream constframe */
>  	struct dc_cf *cf;
> +	/** @db: domainblend */
> +	struct dc_db *db;
>  	/** @lb: layerblend */
>  	struct dc_lb *lb;
>  	/** @ed: content stream extdst */
> --
> 2.51.0
>