From: Frank Li <Frank.li@nxp.com>
To: Marek Vasut <marek.vasut@mailbox.org>
Cc: dri-devel@lists.freedesktop.org, Abel Vesa <abelvesa@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Liu Ying <victor.liu@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>, Peng Fan <peng.fan@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 13/39] drm/imx: dc: fu: Describe remaining register offsets
Date: Mon, 13 Oct 2025 14:34:13 -0400 [thread overview]
Message-ID: <aO1GJX/2MsA0a2x9@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20251011170213.128907-14-marek.vasut@mailbox.org>
On Sat, Oct 11, 2025 at 06:51:28PM +0200, Marek Vasut wrote:
> Describe the rest of register offsets in struct dc_fu { } and
> use them throughout the driver. This is a preparatory change
> for i.MX95 addition. No functional change.
Nit: wrap at 75 chars to try to use full line.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
> ---
> Cc: Abel Vesa <abelvesa@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> Cc: Liu Ying <victor.liu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Thomas Zimmermann <tzimmermann@suse.de>
> Cc: devicetree@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: imx@lists.linux.dev
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-clk@vger.kernel.org
> ---
> drivers/gpu/drm/imx/dc/dc-fl.c | 12 ++++++++----
> drivers/gpu/drm/imx/dc/dc-fu.c | 6 +++---
> drivers/gpu/drm/imx/dc/dc-fu.h | 4 ++++
> drivers/gpu/drm/imx/dc/dc-fw.c | 10 +++++++---
> 4 files changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/imx/dc/dc-fl.c b/drivers/gpu/drm/imx/dc/dc-fl.c
> index d4e746f8c4297..8571871c6a683 100644
> --- a/drivers/gpu/drm/imx/dc/dc-fl.c
> +++ b/drivers/gpu/drm/imx/dc/dc-fl.c
> @@ -63,20 +63,20 @@ static void dc_fl_set_fmt(struct dc_fu *fu, enum dc_fu_frac frac,
>
> dc_fu_set_src_bpp(fu, frac, format->cpp[0] * 8);
>
> - regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac),
> + regmap_write_bits(fu->reg_cfg, fu->reg_layerproperty[frac],
> YUVCONVERSIONMODE_MASK,
> YUVCONVERSIONMODE(YUVCONVERSIONMODE_OFF));
>
> dc_fu_get_pixel_format_bits(fu, format->format, &bits);
> dc_fu_get_pixel_format_shifts(fu, format->format, &shifts);
>
> - regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits);
> - regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts);
> + regmap_write(fu->reg_cfg, fu->reg_colorcomponentbits[frac], bits);
> + regmap_write(fu->reg_cfg, fu->reg_colorcomponentshift[frac], shifts);
> }
>
> static void dc_fl_set_framedimensions(struct dc_fu *fu, int w, int h)
> {
> - regmap_write(fu->reg_cfg, FRAMEDIMENSIONS,
> + regmap_write(fu->reg_cfg, fu->reg_framedimensions,
> FRAMEWIDTH(w) | FRAMEHEIGHT(h));
> }
>
> @@ -133,12 +133,16 @@ static int dc_fl_bind(struct device *dev, struct device *master, void *data)
> fu->reg_baseaddr[i] = BASEADDRESS(i);
> fu->reg_sourcebufferattributes[i] = SOURCEBUFFERATTRIBUTES(i);
> fu->reg_sourcebufferdimension[i] = SOURCEBUFFERDIMENSION(i);
> + fu->reg_colorcomponentbits[i] = COLORCOMPONENTBITS(i);
> + fu->reg_colorcomponentshift[i] = COLORCOMPONENTSHIFT(i);
> fu->reg_layeroffset[i] = LAYEROFFSET(i);
> fu->reg_clipwindowoffset[i] = CLIPWINDOWOFFSET(i);
> fu->reg_clipwindowdimensions[i] = CLIPWINDOWDIMENSIONS(i);
> fu->reg_constantcolor[i] = CONSTANTCOLOR(i);
> fu->reg_layerproperty[i] = LAYERPROPERTY(i);
> }
> + fu->reg_burstbuffermanagement = BURSTBUFFERMANAGEMENT;
> + fu->reg_framedimensions = FRAMEDIMENSIONS;
> snprintf(fu->name, sizeof(fu->name), "FetchLayer%d", id);
>
> dc_fl_set_ops(fu);
> diff --git a/drivers/gpu/drm/imx/dc/dc-fu.c b/drivers/gpu/drm/imx/dc/dc-fu.c
> index f94c591c81589..cc8b0d05891fd 100644
> --- a/drivers/gpu/drm/imx/dc/dc-fu.c
> +++ b/drivers/gpu/drm/imx/dc/dc-fu.c
> @@ -113,13 +113,13 @@ void dc_fu_shdldreq_sticky(struct dc_fu *fu, u8 layer_mask)
>
> static inline void dc_fu_set_linemode(struct dc_fu *fu, enum dc_linemode mode)
> {
> - regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT, LINEMODE_MASK,
> + regmap_write_bits(fu->reg_cfg, fu->reg_burstbuffermanagement, LINEMODE_MASK,
> mode);
> }
>
> static inline void dc_fu_set_numbuffers(struct dc_fu *fu, unsigned int num)
> {
> - regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT,
> + regmap_write_bits(fu->reg_cfg, fu->reg_burstbuffermanagement,
> SETNUMBUFFERS_MASK, SETNUMBUFFERS(num));
> }
>
> @@ -132,7 +132,7 @@ static void dc_fu_set_burstlength(struct dc_fu *fu, dma_addr_t baddr)
> burst_size = min(burst_size, 128U);
> burst_length = burst_size / 8;
>
> - regmap_write_bits(fu->reg_cfg, BURSTBUFFERMANAGEMENT,
> + regmap_write_bits(fu->reg_cfg, fu->reg_burstbuffermanagement,
> SETBURSTLENGTH_MASK, SETBURSTLENGTH(burst_length));
> }
>
> diff --git a/drivers/gpu/drm/imx/dc/dc-fu.h b/drivers/gpu/drm/imx/dc/dc-fu.h
> index e016e1ea5b4e0..2a330c0abf6a1 100644
> --- a/drivers/gpu/drm/imx/dc/dc-fu.h
> +++ b/drivers/gpu/drm/imx/dc/dc-fu.h
> @@ -105,11 +105,15 @@ struct dc_fu {
> u32 reg_baseaddr[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_sourcebufferattributes[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_sourcebufferdimension[DC_FETCHUNIT_FRAC_NUM];
> + u32 reg_colorcomponentbits[DC_FETCHUNIT_FRAC_NUM];
> + u32 reg_colorcomponentshift[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_layeroffset[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_clipwindowoffset[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_clipwindowdimensions[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_constantcolor[DC_FETCHUNIT_FRAC_NUM];
> u32 reg_layerproperty[DC_FETCHUNIT_FRAC_NUM];
> + u32 reg_burstbuffermanagement;
> + u32 reg_framedimensions;
> unsigned int id;
> enum dc_link_id link_id;
> struct dc_fu_ops ops;
> diff --git a/drivers/gpu/drm/imx/dc/dc-fw.c b/drivers/gpu/drm/imx/dc/dc-fw.c
> index c1131b7b17c2f..dc036121f0d23 100644
> --- a/drivers/gpu/drm/imx/dc/dc-fw.c
> +++ b/drivers/gpu/drm/imx/dc/dc-fw.c
> @@ -91,15 +91,15 @@ static void dc_fw_set_fmt(struct dc_fu *fu, enum dc_fu_frac frac,
> regmap_write_bits(fu->reg_cfg, CONTROL, RASTERMODE_MASK,
> RASTERMODE(RASTERMODE_NORMAL));
>
> - regmap_write_bits(fu->reg_cfg, LAYERPROPERTY(frac),
> + regmap_write_bits(fu->reg_cfg, fu->reg_layerproperty[frac],
> YUVCONVERSIONMODE_MASK,
> YUVCONVERSIONMODE(YUVCONVERSIONMODE_OFF));
>
> dc_fu_get_pixel_format_bits(fu, format->format, &bits);
> dc_fu_get_pixel_format_shifts(fu, format->format, &shifts);
>
> - regmap_write(fu->reg_cfg, COLORCOMPONENTBITS(frac), bits);
> - regmap_write(fu->reg_cfg, COLORCOMPONENTSHIFT(frac), shifts);
> + regmap_write(fu->reg_cfg, fu->reg_colorcomponentbits[frac], bits);
> + regmap_write(fu->reg_cfg, fu->reg_colorcomponentshift[frac], shifts);
> }
>
> static void dc_fw_set_framedimensions(struct dc_fu *fu, int w, int h)
> @@ -170,12 +170,16 @@ static int dc_fw_bind(struct device *dev, struct device *master, void *data)
> fu->reg_baseaddr[i] = BASEADDRESS(i);
> fu->reg_sourcebufferattributes[i] = SOURCEBUFFERATTRIBUTES(i);
> fu->reg_sourcebufferdimension[i] = SOURCEBUFFERDIMENSION(i);
> + fu->reg_colorcomponentbits[i] = COLORCOMPONENTBITS(i);
> + fu->reg_colorcomponentshift[i] = COLORCOMPONENTSHIFT(i);
> fu->reg_layeroffset[i] = LAYEROFFSET(i);
> fu->reg_clipwindowoffset[i] = CLIPWINDOWOFFSET(i);
> fu->reg_clipwindowdimensions[i] = CLIPWINDOWDIMENSIONS(i);
> fu->reg_constantcolor[i] = CONSTANTCOLOR(i);
> fu->reg_layerproperty[i] = LAYERPROPERTY(i);
> }
> + fu->reg_burstbuffermanagement = BURSTBUFFERMANAGEMENT;
> + fu->reg_framedimensions = FRAMEDIMENSIONS;
> snprintf(fu->name, sizeof(fu->name), "FetchWarp%d", id);
>
> dc_fw_set_ops(fu);
> --
> 2.51.0
>
next prev parent reply other threads:[~2025-10-13 18:34 UTC|newest]
Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-11 16:51 [PATCH 00/39] Add i.MX95 DPU/DSI/LVDS support Marek Vasut
2025-10-11 16:51 ` [PATCH 01/39] dt-bindings: display: imx: Document i.MX95 Display Controller DomainBlend Marek Vasut
2025-10-15 13:24 ` Rob Herring
2025-10-16 2:07 ` Liu Ying
2025-10-17 15:15 ` Marek Vasut
2025-10-18 6:09 ` Ying Liu
2025-11-02 16:41 ` Marek Vasut
2025-11-04 3:31 ` Liu Ying
2025-10-21 6:52 ` Krzysztof Kozlowski
2025-10-11 16:51 ` [PATCH 02/39] drm/imx: Add " Marek Vasut
2025-10-13 16:38 ` Frank Li
2025-10-14 11:50 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 03/39] dt-bindings: display: imx: Document i.MX95 Display Controller processing units Marek Vasut
2025-10-13 16:49 ` Frank Li
2025-10-14 11:52 ` Marek Vasut
2025-10-15 8:59 ` Liu Ying
2025-10-15 10:19 ` Marek Vasut
2025-10-16 2:28 ` Liu Ying
2025-10-16 2:58 ` Liu Ying
2025-10-17 15:18 ` Marek Vasut
2025-10-18 5:44 ` Ying Liu
2025-10-11 16:51 ` [PATCH 04/39] drm/imx: dc: Use bulk clock Marek Vasut
2025-10-13 16:54 ` Frank Li
2025-10-14 12:02 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 05/39] drm/imx: dc: Rework dc_subdev_get_id() to drop ARRAY_SIZE() use Marek Vasut
2025-10-13 16:56 ` Frank Li
2025-10-14 14:03 ` Marek Vasut
2025-10-14 15:11 ` Frank Li
2025-10-14 21:11 ` Marek Vasut
2025-10-15 9:14 ` Liu Ying
2025-10-15 14:31 ` Frank Li
2025-10-16 2:50 ` Liu Ying
2025-10-11 16:51 ` [PATCH 06/39] drm/imx: dc: Rename i.MX8QXP specific Link IDs Marek Vasut
2025-10-13 16:58 ` Frank Li
2025-10-11 16:51 ` [PATCH 07/39] drm/imx: dc: cf: Pass struct dc_subdev_info via OF match data Marek Vasut
2025-10-13 17:01 ` Frank Li
2025-10-11 16:51 ` [PATCH 08/39] drm/imx: dc: de: Pass struct dc_de_subdev_match_data " Marek Vasut
2025-10-13 17:05 ` Frank Li
2025-10-11 16:51 ` [PATCH 09/39] drm/imx: dc: ed: Rework dc_ed_pec_src_sel() to drop ARRAY_SIZE() use Marek Vasut
2025-10-13 18:24 ` Frank Li
2025-10-11 16:51 ` [PATCH 10/39] drm/imx: dc: ed: Pass struct dc_ed_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:26 ` Frank Li
2025-10-11 16:51 ` [PATCH 11/39] drm/imx: dc: fg: Parametrize register access Marek Vasut
2025-10-13 18:29 ` Frank Li
2025-10-11 16:51 ` [PATCH 12/39] drm/imx: dc: ed: Pass struct dc_fg_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:31 ` Frank Li
2025-10-11 16:51 ` [PATCH 13/39] drm/imx: dc: fu: Describe remaining register offsets Marek Vasut
2025-10-13 18:34 ` Frank Li [this message]
2025-10-11 16:51 ` [PATCH 14/39] drm/imx: dc: fu: Inline FRAC_OFFSET into FetchLayer and FetchWrap Marek Vasut
2025-10-13 18:39 ` Frank Li
2025-10-11 16:51 ` [PATCH 15/39] drm/imx: dc: fu: Pass struct dc_fu_subdev_match_data via OF match data Marek Vasut
2025-10-13 18:43 ` Frank Li
2025-10-11 16:51 ` [PATCH 16/39] drm/imx: dc: lb: Pass struct dc_lb_subdev_match_data " Marek Vasut
2025-10-13 18:45 ` Frank Li
2025-10-11 16:51 ` [PATCH 17/39] drm/imx: dc: tc: Pass struct dc_tc_subdev_match_data " Marek Vasut
2025-10-11 16:51 ` [PATCH 18/39] drm/imx: dc: ic: Pass struct dc_ic_subdev_match_data " Marek Vasut
2025-10-11 16:51 ` [PATCH 19/39] drm/imx: dc: ic: Use DT node as interrupt controller name Marek Vasut
2025-10-11 16:51 ` [PATCH 20/39] drm/imx: dc: Configure display CSR clock feed select Marek Vasut
2025-10-13 18:48 ` Frank Li
2025-10-17 15:20 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 21/39] drm/imx: dc: crtc: Do not check disabled CRTCs Marek Vasut
2025-10-13 18:50 ` Frank Li
2025-10-14 21:41 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 22/39] drm/imx: dc: Keep FU unit running on i.MX95 Marek Vasut
2025-10-13 18:52 ` Frank Li
2025-10-11 16:51 ` [PATCH 23/39] drm/imx: dc: Add OF match data for i.MX95 Marek Vasut
2025-10-13 18:54 ` Frank Li
2025-10-11 16:51 ` [PATCH 24/39] drm/imx: Add more RGB swizzling options Marek Vasut
2025-10-11 16:51 ` [PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel interleaver support Marek Vasut
2025-10-13 18:57 ` Frank Li
2025-10-17 14:55 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 26/39] drm/bridge: imx: Add " Marek Vasut
2025-10-13 19:02 ` Frank Li
2025-10-11 16:51 ` [PATCH 27/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel link support Marek Vasut
2025-10-13 19:08 ` Frank Li
2025-10-17 15:01 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 28/39] drm/bridge: imx: Add " Marek Vasut
2025-10-13 19:10 ` Frank Li
2025-10-11 16:51 ` [PATCH 29/39] dt-bindings: display: bridge: Document Freescale i.MX95 MIPI DSI Marek Vasut
2025-10-13 19:13 ` Frank Li
2025-10-17 15:37 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 30/39] drm/bridge: imx93-mipi-dsi: Add i.MX95 PLL initialization Marek Vasut
2025-10-11 16:51 ` [PATCH 31/39] dt-bindings: clock: Split support for i.MX95 LVDS CSR Marek Vasut
2025-10-13 19:17 ` Frank Li
2025-10-17 15:49 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 32/39] dt-bindings: display: bridge: Document i.MX95 LVDS display bridge binding Marek Vasut
2025-10-13 19:20 ` Frank Li
2025-10-17 15:04 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 33/39] drm: bridge: imx: Add i.MX95 LVDS Display Bridge (LDB) driver Marek Vasut
2025-10-11 16:51 ` [PATCH 34/39] dt-bindings: display: bridge: ldb: Add an i.MX95 entry Marek Vasut
2025-10-13 11:34 ` Rob Herring (Arm)
2025-10-11 16:51 ` [PATCH 35/39] drm/bridge: fsl-ldb: Parse register offsets from DT Marek Vasut
2025-10-13 19:23 ` Frank Li
2025-10-17 15:39 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 36/39] drm/bridge: fsl-ldb: Add i.MX95 support Marek Vasut
2025-10-13 19:24 ` Frank Li
2025-10-11 16:51 ` [PATCH 37/39] dt-bindings: interrupt-controller: fsl,irqsteer: " Marek Vasut
2025-10-13 19:25 ` Frank Li
2025-10-15 13:31 ` Rob Herring (Arm)
2025-10-11 16:51 ` [PATCH 38/39] dt-bindings: clock: support i.MX95 Display Stream CSR module Marek Vasut
2025-10-13 19:26 ` Frank Li
2025-10-17 15:05 ` Marek Vasut
2025-10-15 13:33 ` Rob Herring
2025-10-17 15:08 ` Marek Vasut
2025-10-11 16:51 ` [PATCH 39/39] arm64: dts: imx95: Describe display pipeline Marek Vasut
2025-10-14 8:51 ` [PATCH 00/39] Add i.MX95 DPU/DSI/LVDS support Liu Ying
2025-10-14 21:55 ` Marek Vasut
2025-10-15 10:00 ` Liu Ying
2025-10-15 16:18 ` Marek Vasut
2025-10-20 2:15 ` Ying Liu
2025-11-02 16:33 ` Marek Vasut
2025-11-04 7:00 ` Liu Ying
2025-10-14 9:13 ` Liu Ying
2025-10-14 22:09 ` Marek Vasut
2025-10-15 10:09 ` Liu Ying
2025-10-17 15:54 ` Marek Vasut
2025-10-20 2:35 ` Liu Ying
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