* [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini
@ 2025-10-09 10:54 Maud Spierings via B4 Relay
2025-10-09 10:54 ` [PATCH 1/5] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings
Add initial support for the Moduline IV and Moduline Mini embedded
controllers.
These systems are powered by the Ka-Ro Electronics tx8m-1610 COM, which
features an imx8mm SoC.
Signed-off-by: Maud Spierings <maudspierings@gocontroll.com>
---
Maud Spierings (5):
dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini
arm64: dts: imx8mm: Add pinctrl config definitions
arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM
arm64: dts: freescale: Add the GOcontroll Moduline IV
arm64: dts: freescale: Add the GOcontroll Moduline Mini
Documentation/devicetree/bindings/arm/fsl.yaml | 2 +
arch/arm64/boot/dts/freescale/Makefile | 3 +
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 33 +
.../imx8mm-tx8m-1610-moduline-iv-306-d.dts | 801 +++++++++++++++++++++
.../imx8mm-tx8m-1610-moduline-mini-111.dts | 691 ++++++++++++++++++
.../arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 562 +++++++++++++++
6 files changed, 2092 insertions(+)
---
base-commit: 7c3ba4249a3604477ea9c077e10089ba7ddcaa03
change-id: 20251009-mini_iv-a05e5c2c1223
Best regards,
--
Maud Spierings <maudspierings@gocontroll.com>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/5] dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay @ 2025-10-09 10:54 ` Maud Spierings via B4 Relay 2025-10-09 18:26 ` Conor Dooley 2025-10-09 10:54 ` [PATCH 2/5] arm64: dts: imx8mm: Add pinctrl config definitions Maud Spierings via B4 Relay ` (3 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings From: Maud Spierings <maudspierings@gocontroll.com> Document the compatible strings for the Moduline IV and Mini. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 00cdf490b0620..41eb19e3530da 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -963,6 +963,8 @@ properties: - fsl,imx8mm-evkb # i.MX8MM EVKB Board - gateworks,imx8mm-gw75xx-0x # i.MX8MM Gateworks Board - gateworks,imx8mm-gw7904 + - gocontroll,moduline-iv + - gocontroll,moduline-mini - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit -- 2.51.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/5] dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini 2025-10-09 10:54 ` [PATCH 1/5] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay @ 2025-10-09 18:26 ` Conor Dooley 0 siblings, 0 replies; 9+ messages in thread From: Conor Dooley @ 2025-10-09 18:26 UTC (permalink / raw) To: maudspierings Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, linux-kernel, imx, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 52 bytes --] Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/5] arm64: dts: imx8mm: Add pinctrl config definitions 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 1/5] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay @ 2025-10-09 10:54 ` Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM Maud Spierings via B4 Relay ` (2 subsequent siblings) 4 siblings, 0 replies; 9+ messages in thread From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings From: Maud Spierings <maudspierings@gocontroll.com> Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> --- arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index b1f11098d248e..31557b7b9ccc1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -6,6 +6,39 @@ #ifndef __DTS_IMX8MM_PINFUNC_H #define __DTS_IMX8MM_PINFUNC_H +/* Drive Strength */ +#define MX8MM_DSE_X1 0x0 +#define MX8MM_DSE_X2 0x4 +#define MX8MM_DSE_X4 0x2 +#define MX8MM_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MM_FSEL_FAST 0x10 +#define MX8MM_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MM_ODE_ENABLE 0x20 +#define MX8MM_ODE_DISABLE 0x0 + +#define MX8MM_PULL_DOWN 0x0 +#define MX8MM_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MM_HYS_CMOS 0x0 +#define MX8MM_HYS_SCHMITT 0x80 + +#define MX8MM_PULL_ENABLE 0x100 +#define MX8MM_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MM_SION 0x40000000 + +/* long defaults */ +#define MX8MM_USDHC_DATA_DEFAULT (MX8MM_FSEL_FAST | MX8MM_PULL_UP | \ + MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) +#define MX8MM_I2C_DEFAULT (MX8MM_DSE_X6 | MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | \ + MX8MM_PULL_ENABLE | MX8MM_SION) + /* * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> -- 2.51.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 1/5] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 2/5] arm64: dts: imx8mm: Add pinctrl config definitions Maud Spierings via B4 Relay @ 2025-10-09 10:54 ` Maud Spierings via B4 Relay 2025-10-09 14:48 ` Frank Li 2025-10-09 10:54 ` [PATCH 4/5] arm64: dts: freescale: Add the GOcontroll Moduline IV Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 5/5] arm64: dts: freescale: Add the GOcontroll Moduline Mini Maud Spierings via B4 Relay 4 siblings, 1 reply; 9+ messages in thread From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings From: Maud Spierings <maudspierings@gocontroll.com> The Ka-Ro Electronics tx8m-1610 is a COM based on the imx8mm SOC. It has 1 GB of ram and 4 GB of eMMC storage on board. Add it to enable boards based on this module Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> --- .../arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 562 +++++++++++++++++++++ 1 file changed, 562 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi new file mode 100644 index 0000000000000..6ed86b10c4310 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de> + * 2025 Maud Spierings <maudspierings@gocontroll.com> + */ + +#include "imx8mm.dtsi" + +/ { + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_3v3_etn>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-etn"; + vin-supply = <®_vdd_3v3>; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; +}; + +&fec1 { + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-supply = <®_3v3_etn>; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_ethphy_rst>; + pinctrl-names = "default"; + reset-delay-us = <25000>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clk IMX8MM_CLK_ENET_REF>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_152", + "SODIMM_42", + "SODIMM_153", + "PMIC_IRQ_B", + "SODIMM_154", + "SODIMM_155", + "SODIMM_156", + "SODIMM_157", + "SODIMM_158", + "SODIMM_159", + "SODIMM_161", + "SODIMM_162", + "SODIMM_34", + "SODIMM_36", + "SODIMM_27", + "SODIMM_28", + "", + "", + "", + "", + "", + "", + "", + "ENET_POWER", + "", + "", + "", + "", + "ENET_nINT", + "ENET_nRST", + "", + ""; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_51", + "SODIMM_57", + "SODIMM_56", + "SODIMM_52", + "SODIMM_53", + "SODIMM_54", + "SODIMM_55", + "SODIMM_15", + "SODIMM_45", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio3 { + gpio-line-names = "SODIMM_103", + "SODIMM_104", + "SODIMM_105", + "SODIMM_106", + "SODIMM_107", + "SODIMM_112", + "SODIMM_108", + "SODIMM_109", + "SODIMM_95", + "SODIMM_110", + "SODIMM_96", + "SODIMM_97", + "SODIMM_98", + "SODIMM_99", + "SODIMM_113", + "SODIMM_114", + "SODIMM_115", + "SODIMM_101", + "SODIMM_100", + "SODIMM_77", + "SODIMM_72", + "SODIMM_73", + "SODIMM_74", + "SODIMM_75", + "SODIMM_76", + "SODIMM_43", + "", + "", + "", + "", + "", + ""; +}; + +&gpio4 { + gpio-line-names = "SODIMM_178", + "SODIMM_180", + "SODIMM_184", + "SODIMM_185", + "SODIMM_186", + "SODIMM_187", + "SODIMM_188", + "SODIMM_189", + "SODIMM_190", + "SODIMM_191", + "SODIMM_179", + "SODIMM_181", + "SODIMM_192", + "SODIMM_193", + "SODIMM_194", + "SODIMM_195", + "SODIMM_196", + "SODIMM_197", + "SODIMM_198", + "SODIMM_199", + "SODIMM_182", + "SODIMM_79", + "SODIMM_78", + "SODIMM_84", + "SODIMM_87", + "SODIMM_86", + "SODIMM_85", + "SODIMM_83", + "SODIMM_81", + "SODIMM_80", + "SODIMM_90", + "SODIMM_93"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_92", + "SODIMM_91", + "SODIMM_89", + "SODIMM_144", + "SODIMM_143", + "SODIMM_146", + "SODIMM_68", + "SODIMM_67", + "SODIMM_70", + "SODIMM_69", + "SODIMM_48", + "SODIMM_46", + "SODIMM_47", + "SODIMM_44", + "PMIC_SCL", + "PMIC_SDA", + "SODIMM_41", + "SODIMM_40", + "SODIMM_148", + "SODIMM_149", + "SODIMM_150", + "SODIMM_151", + "SODIMM_60", + "SODIMM_59", + "SODIMM_64", + "SODIMM_63", + "SODIMM_62", + "SODIMM_61", + "SODIMM_66", + "SODIMM_65", + "", + ""; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <780000>; + regulator-name = "buck1"; + regulator-ramp-delay = <1250>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck2"; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <950000>; + rohm,dvs-idle-voltage = <810000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck3"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "buck4"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1700000>; + regulator-name = "buck5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + /* + * The default output voltage is 1.1V, bumped + * to 1.35V in HW by a 499R/2.2K voltage divider in the + * feedback path. + */ + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "buck6"; + }; + + reg_snvs_1v8: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1980000>; + regulator-min-microvolt = <1620000>; + regulator-name = "ldo1"; + }; + + reg_snvs_0v8: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <760000>; + regulator-name = "ldo2"; + }; + + reg_vdda_1v8: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "ldo3"; + }; + + reg_vdd_phy_0v9: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <855000>; + regulator-name = "ldo4"; + }; + + ldo5_reg: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "ldo5"; + }; + + reg_vdd_phy_1v2: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1260000>; + regulator-min-microvolt = <1140000>; + regulator-name = "ldo6"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ethphy_int: etnphy-intgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst: etnphy-rstgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK + (MX8MM_FSEL_FAST | MX8MM_SION) + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + status = "okay"; +}; -- 2.51.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM 2025-10-09 10:54 ` [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM Maud Spierings via B4 Relay @ 2025-10-09 14:48 ` Frank Li 2025-10-09 14:50 ` Maud Spierings 0 siblings, 1 reply; 9+ messages in thread From: Frank Li @ 2025-10-09 14:48 UTC (permalink / raw) To: maudspierings Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, linux-kernel, imx, linux-arm-kernel On Thu, Oct 09, 2025 at 12:54:19PM +0200, Maud Spierings via B4 Relay wrote: > From: Maud Spierings <maudspierings@gocontroll.com> > > The Ka-Ro Electronics tx8m-1610 is a COM based on the imx8mm SOC. It has > 1 GB of ram and 4 GB of eMMC storage on board. > > Add it to enable boards based on this module > > Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> > --- > .../arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 562 +++++++++++++++++++++ > 1 file changed, 562 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi > new file mode 100644 > index 0000000000000..6ed86b10c4310 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi > @@ -0,0 +1,562 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de> > + * 2025 Maud Spierings <maudspierings@gocontroll.com> > + */ > + > +#include "imx8mm.dtsi" > + > +/ { > + reg_3v3_etn: regulator-3v3-etn { > + compatible = "regulator-fixed"; > + enable-active-high; > + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; > + pinctrl-0 = <&pinctrl_reg_3v3_etn>; > + pinctrl-names = "default"; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "3v3-etn"; > + vin-supply = <®_vdd_3v3>; > + }; > +}; > + > +&A53_0 { > + cpu-supply = <®_vdd_arm>; > +}; > + > +&A53_1 { > + cpu-supply = <®_vdd_arm>; > +}; > + > +&A53_2 { > + cpu-supply = <®_vdd_arm>; > +}; > + > +&A53_3 { > + cpu-supply = <®_vdd_arm>; > +}; > + > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > + > + ddrc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + }; > + }; > +}; > + > +&fec1 { > + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, > + <&clk IMX8MM_CLK_ENET_TIMER>, > + <&clk IMX8MM_CLK_ENET_REF>, > + <&clk IMX8MM_CLK_ENET_REF>; Need align to previous line < > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, > + <&clk IMX8MM_SYS_PLL2_100M>, > + <&clk IMX8MM_SYS_PLL2_50M>, > + <&clk IMX8MM_SYS_PLL2_50M>; > + assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; > + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, > + <&clk IMX8MM_CLK_ENET1_ROOT>, > + <&clk IMX8MM_CLK_ENET_TIMER>, > + <&clk IMX8MM_CLK_ENET_REF>; > + phy-handle = <ðphy0>; > + phy-mode = "rmii"; > + phy-supply = <®_3v3_etn>; > + pinctrl-0 = <&pinctrl_fec1>; > + pinctrl-names = "default"; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-0 = <&pinctrl_ethphy_rst>; > + pinctrl-names = "default"; > + reset-delay-us = <25000>; > + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; > + reset-post-delay-us = <100>; > + > + ethphy0: ethernet-phy@0 { > + reg = <0>; > + clocks = <&clk IMX8MM_CLK_ENET_REF>; > + smsc,disable-energy-detect; > + }; > + }; > +}; > + > +&gpio1 { > + gpio-line-names = "SODIMM_152", > + "SODIMM_42", > + "SODIMM_153", > + "PMIC_IRQ_B", > + "SODIMM_154", > + "SODIMM_155", > + "SODIMM_156", > + "SODIMM_157", > + "SODIMM_158", > + "SODIMM_159", > + "SODIMM_161", > + "SODIMM_162", > + "SODIMM_34", > + "SODIMM_36", > + "SODIMM_27", > + "SODIMM_28", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "ENET_POWER", > + "", > + "", > + "", > + "", > + "ENET_nINT", > + "ENET_nRST", > + "", > + ""; I think gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", ... pack 4 lines to one line to help readablity. Frank Li > +}; > + > +&gpio2 { > + gpio-line-names = "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "SODIMM_51", > + "SODIMM_57", > + "SODIMM_56", > + "SODIMM_52", > + "SODIMM_53", > + "SODIMM_54", > + "SODIMM_55", > + "SODIMM_15", > + "SODIMM_45", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + "", > + ""; > +}; > + > +&gpio3 { > + gpio-line-names = "SODIMM_103", > + "SODIMM_104", > + "SODIMM_105", > + "SODIMM_106", > + "SODIMM_107", > + "SODIMM_112", > + "SODIMM_108", > + "SODIMM_109", > + "SODIMM_95", > + "SODIMM_110", > + "SODIMM_96", > + "SODIMM_97", > + "SODIMM_98", > + "SODIMM_99", > + "SODIMM_113", > + "SODIMM_114", > + "SODIMM_115", > + "SODIMM_101", > + "SODIMM_100", > + "SODIMM_77", > + "SODIMM_72", > + "SODIMM_73", > + "SODIMM_74", > + "SODIMM_75", > + "SODIMM_76", > + "SODIMM_43", > + "", > + "", > + "", > + "", > + "", > + ""; > +}; > + > +&gpio4 { > + gpio-line-names = "SODIMM_178", > + "SODIMM_180", > + "SODIMM_184", > + "SODIMM_185", > + "SODIMM_186", > + "SODIMM_187", > + "SODIMM_188", > + "SODIMM_189", > + "SODIMM_190", > + "SODIMM_191", > + "SODIMM_179", > + "SODIMM_181", > + "SODIMM_192", > + "SODIMM_193", > + "SODIMM_194", > + "SODIMM_195", > + "SODIMM_196", > + "SODIMM_197", > + "SODIMM_198", > + "SODIMM_199", > + "SODIMM_182", > + "SODIMM_79", > + "SODIMM_78", > + "SODIMM_84", > + "SODIMM_87", > + "SODIMM_86", > + "SODIMM_85", > + "SODIMM_83", > + "SODIMM_81", > + "SODIMM_80", > + "SODIMM_90", > + "SODIMM_93"; > +}; > + > +&gpio5 { > + gpio-line-names = "SODIMM_92", > + "SODIMM_91", > + "SODIMM_89", > + "SODIMM_144", > + "SODIMM_143", > + "SODIMM_146", > + "SODIMM_68", > + "SODIMM_67", > + "SODIMM_70", > + "SODIMM_69", > + "SODIMM_48", > + "SODIMM_46", > + "SODIMM_47", > + "SODIMM_44", > + "PMIC_SCL", > + "PMIC_SDA", > + "SODIMM_41", > + "SODIMM_40", > + "SODIMM_148", > + "SODIMM_149", > + "SODIMM_150", > + "SODIMM_151", > + "SODIMM_60", > + "SODIMM_59", > + "SODIMM_64", > + "SODIMM_63", > + "SODIMM_62", > + "SODIMM_61", > + "SODIMM_66", > + "SODIMM_65", > + "", > + ""; > +}; > + > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-0 = <&pinctrl_i2c1>; > + pinctrl-1 = <&pinctrl_i2c1_gpio>; > + pinctrl-names = "default", "gpio"; > + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > + > + pmic: pmic@4b { > + compatible = "rohm,bd71847"; > + reg = <0x4b>; > + interrupt-parent = <&gpio1>; > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > + pinctrl-0 = <&pinctrl_pmic>; > + pinctrl-names = "default"; > + rohm,reset-snvs-powered; > + > + regulators { > + reg_vdd_soc: BUCK1 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <900000>; > + regulator-min-microvolt = <780000>; > + regulator-name = "buck1"; > + regulator-ramp-delay = <1250>; > + }; > + > + reg_vdd_arm: BUCK2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <950000>; > + regulator-min-microvolt = <805000>; > + regulator-name = "buck2"; > + regulator-ramp-delay = <1250>; > + rohm,dvs-run-voltage = <950000>; > + rohm,dvs-idle-voltage = <810000>; > + }; > + > + reg_vdd_dram: BUCK3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <900000>; > + regulator-min-microvolt = <805000>; > + regulator-name = "buck3"; > + }; > + > + reg_vdd_3v3: BUCK4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "buck4"; > + }; > + > + reg_vdd_1v8: BUCK5 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1950000>; > + regulator-min-microvolt = <1700000>; > + regulator-name = "buck5"; > + }; > + > + BUCK6 { > + regulator-always-on; > + regulator-boot-on; > + /* > + * The default output voltage is 1.1V, bumped > + * to 1.35V in HW by a 499R/2.2K voltage divider in the > + * feedback path. > + */ > + regulator-max-microvolt = <1100000>; > + regulator-min-microvolt = <1100000>; > + regulator-name = "buck6"; > + }; > + > + reg_snvs_1v8: LDO1 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1980000>; > + regulator-min-microvolt = <1620000>; > + regulator-name = "ldo1"; > + }; > + > + reg_snvs_0v8: LDO2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <900000>; > + regulator-min-microvolt = <760000>; > + regulator-name = "ldo2"; > + }; > + > + reg_vdda_1v8: LDO3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1890000>; > + regulator-min-microvolt = <1710000>; > + regulator-name = "ldo3"; > + }; > + > + reg_vdd_phy_0v9: LDO4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1000000>; > + regulator-min-microvolt = <855000>; > + regulator-name = "ldo4"; > + }; > + > + ldo5_reg: LDO5 { > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1800000>; > + regulator-name = "ldo5"; > + }; > + > + reg_vdd_phy_1v2: LDO6 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1260000>; > + regulator-min-microvolt = <1140000>; > + regulator-name = "ldo6"; > + }; > + }; > + }; > +}; > + > +&iomuxc { > + pinctrl_ethphy_int: etnphy-intgrp { > + fsl,pins = < > + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 > + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) > + >; > + }; > + > + pinctrl_ethphy_rst: etnphy-rstgrp { > + fsl,pins = < > + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 > + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + >; > + }; > + > + pinctrl_fec1: fec1grp { > + fsl,pins = < > + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC > + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO > + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK > + (MX8MM_FSEL_FAST | MX8MM_SION) > + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) > + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) > + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 > + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) > + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 > + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) > + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER > + MX8MM_FSEL_FAST > + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL > + MX8MM_FSEL_FAST > + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL > + MX8MM_I2C_DEFAULT > + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA > + MX8MM_I2C_DEFAULT > + >; > + }; > + > + pinctrl_i2c1_gpio: i2c1-gpiogrp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 > + MX8MM_I2C_DEFAULT > + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 > + MX8MM_I2C_DEFAULT > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 > + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + >; > + }; > + > + pinctrl_reg_3v3_etn: reg-3v3-etngrp { > + fsl,pins = < > + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 > + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > + MX8MM_USDHC_DATA_DEFAULT > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) > + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) > + >; > + }; > +}; > + > +&usdhc1 { > + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; > + assigned-clock-rates = <400000000>; > + bus-width = <8>; > + non-removable; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + vmmc-supply = <®_vdd_3v3>; > + vqmmc-supply = <®_vdd_1v8>; > + status = "okay"; > +}; > > -- > 2.51.0 > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM 2025-10-09 14:48 ` Frank Li @ 2025-10-09 14:50 ` Maud Spierings 0 siblings, 0 replies; 9+ messages in thread From: Maud Spierings @ 2025-10-09 14:50 UTC (permalink / raw) To: Frank Li Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, linux-kernel, imx, linux-arm-kernel Thanks for the review! On 10/9/25 16:48, Frank Li wrote: > On Thu, Oct 09, 2025 at 12:54:19PM +0200, Maud Spierings via B4 Relay wrote: >> From: Maud Spierings <maudspierings@gocontroll.com> >> >> The Ka-Ro Electronics tx8m-1610 is a COM based on the imx8mm SOC. It has >> 1 GB of ram and 4 GB of eMMC storage on board. >> >> Add it to enable boards based on this module >> >> Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> >> --- >> .../arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi | 562 +++++++++++++++++++++ >> 1 file changed, 562 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi >> new file mode 100644 >> index 0000000000000..6ed86b10c4310 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi >> @@ -0,0 +1,562 @@ >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >> +/* >> + * Copyright (C) 2021 Lothar Waßmann <LW@KARO-electronics.de> >> + * 2025 Maud Spierings <maudspierings@gocontroll.com> >> + */ >> + >> +#include "imx8mm.dtsi" >> + >> +/ { >> + reg_3v3_etn: regulator-3v3-etn { >> + compatible = "regulator-fixed"; >> + enable-active-high; >> + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; >> + pinctrl-0 = <&pinctrl_reg_3v3_etn>; >> + pinctrl-names = "default"; >> + regulator-boot-on; >> + regulator-max-microvolt = <3300000>; >> + regulator-min-microvolt = <3300000>; >> + regulator-name = "3v3-etn"; >> + vin-supply = <®_vdd_3v3>; >> + }; >> +}; >> + >> +&A53_0 { >> + cpu-supply = <®_vdd_arm>; >> +}; >> + >> +&A53_1 { >> + cpu-supply = <®_vdd_arm>; >> +}; >> + >> +&A53_2 { >> + cpu-supply = <®_vdd_arm>; >> +}; >> + >> +&A53_3 { >> + cpu-supply = <®_vdd_arm>; >> +}; >> + >> +&ddrc { >> + operating-points-v2 = <&ddrc_opp_table>; >> + >> + ddrc_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-400000000 { >> + opp-hz = /bits/ 64 <400000000>; >> + }; >> + }; >> +}; >> + >> +&fec1 { >> + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, >> + <&clk IMX8MM_CLK_ENET_TIMER>, >> + <&clk IMX8MM_CLK_ENET_REF>, >> + <&clk IMX8MM_CLK_ENET_REF>; > > Need align to previous line < oop yeah thats my bad. >> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, >> + <&clk IMX8MM_SYS_PLL2_100M>, >> + <&clk IMX8MM_SYS_PLL2_50M>, >> + <&clk IMX8MM_SYS_PLL2_50M>; >> + assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; >> + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, >> + <&clk IMX8MM_CLK_ENET1_ROOT>, >> + <&clk IMX8MM_CLK_ENET_TIMER>, >> + <&clk IMX8MM_CLK_ENET_REF>; >> + phy-handle = <ðphy0>; >> + phy-mode = "rmii"; >> + phy-supply = <®_3v3_etn>; >> + pinctrl-0 = <&pinctrl_fec1>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + >> + mdio { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + pinctrl-0 = <&pinctrl_ethphy_rst>; >> + pinctrl-names = "default"; >> + reset-delay-us = <25000>; >> + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; >> + reset-post-delay-us = <100>; >> + >> + ethphy0: ethernet-phy@0 { >> + reg = <0>; >> + clocks = <&clk IMX8MM_CLK_ENET_REF>; >> + smsc,disable-energy-detect; >> + }; >> + }; >> +}; >> + >> +&gpio1 { >> + gpio-line-names = "SODIMM_152", >> + "SODIMM_42", >> + "SODIMM_153", >> + "PMIC_IRQ_B", >> + "SODIMM_154", >> + "SODIMM_155", >> + "SODIMM_156", >> + "SODIMM_157", >> + "SODIMM_158", >> + "SODIMM_159", >> + "SODIMM_161", >> + "SODIMM_162", >> + "SODIMM_34", >> + "SODIMM_36", >> + "SODIMM_27", >> + "SODIMM_28", >> + "", >> + "", >> + "", >> + "", >> + "", >> + "", >> + "", >> + "ENET_POWER", >> + "", >> + "", >> + "", >> + "", >> + "ENET_nINT", >> + "ENET_nRST", >> + "", >> + ""; > > I think > gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", > "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", > ... > > pack 4 lines to one line to help readablity. I followed the same pattern I used in imx8mp-tx8p-ml81.dtsi, but if you want me to change it I will. Kind regards, maud ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/5] arm64: dts: freescale: Add the GOcontroll Moduline IV 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay ` (2 preceding siblings ...) 2025-10-09 10:54 ` [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM Maud Spierings via B4 Relay @ 2025-10-09 10:54 ` Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 5/5] arm64: dts: freescale: Add the GOcontroll Moduline Mini Maud Spierings via B4 Relay 4 siblings, 0 replies; 9+ messages in thread From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings From: Maud Spierings <maudspierings@gocontroll.com> The Moduline IV is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 8 Moduline IO modules - 4 CAN busses - 1 LIN bus - 1 Ethernet - 4 RGB leds - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx8mm-tx8m-1610-moduline-iv-306-d.dts | 801 +++++++++++++++++++++ 2 files changed, 803 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 525ef180481d3..b2fef44e0a370 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -124,6 +124,8 @@ imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts new file mode 100644 index 0000000000000..52a8caf4e078e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings <maudspierings@gocontroll.com> + */ + +/dts-v1/; + +#include "imx8mm-tx8m-1610.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-iv", "fsl,imx8mm"; + hardware = "Moduline IV V3.06-D"; + model = "GOcontroll Moduline IV"; + + aliases { + usb-host = &usbotg2; + usbotg = &usbotg1; + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_m2: regulator-3v3-m2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_m2>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-m.2"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 17 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_can3_stby: regulator-can3-stby { + compatible = "regulator-fixed"; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can3_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can3-stby"; + }; + + reg_can4_stby: regulator-can4-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 8 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can4_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can4-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI 2 */ +&ecspi1 { + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + cs-gpios = < + &gpio1 9 GPIO_ACTIVE_LOW + &gpio1 0 GPIO_ACTIVE_LOW + &gpio5 2 GPIO_ACTIVE_LOW + &gpio4 27 GPIO_ACTIVE_LOW + &gpio3 1 GPIO_ACTIVE_LOW + >; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@2 { + compatible = "gocontroll,moduline-module-slot"; + reg = <2>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + slot-number = <5>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@3 { + compatible = "gocontroll,moduline-module-slot"; + reg = <3>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <6>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@4 { + compatible = "microchip,mcp3004"; + reg = <4>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + cs-gpios = < + &gpio3 23 GPIO_ACTIVE_LOW + &gpio5 9 GPIO_ACTIVE_LOW + &gpio3 2 GPIO_ACTIVE_LOW + &gpio5 25 GPIO_ACTIVE_LOW + >; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + slot-number = <7>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <8>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { // reg vdd? + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can1_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + cs-gpios = < + &gpio1 4 GPIO_ACTIVE_LOW + &gpio1 10 GPIO_ACTIVE_LOW + &gpio5 5 GPIO_ACTIVE_LOW + &gpio5 4 GPIO_ACTIVE_LOW + >; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can3>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can3_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can4>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can4_stby>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = <LED_COLOR_ID_RGB>; + label = "case-led1"; + + led@0 { + color = <LED_COLOR_ID_RED>; + reg = <0>; + }; + + led@1 { + color = <LED_COLOR_ID_GREEN>; + reg = <1>; + }; + + led@2 { + color = <LED_COLOR_ID_BLUE>; + reg = <2>; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = <LED_COLOR_ID_RGB>; + label = "case-led2"; + + led@0 { + color = <LED_COLOR_ID_RED>; + reg = <0>; + }; + + led@1 { + color = <LED_COLOR_ID_GREEN>; + reg = <1>; + }; + + led@2 { + color = <LED_COLOR_ID_BLUE>; + reg = <2>; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = <LED_COLOR_ID_RGB>; + label = "case-led3"; + + led@0 { + color = <LED_COLOR_ID_RED>; + reg = <0>; + }; + + led@1 { + color = <LED_COLOR_ID_GREEN>; + reg = <1>; + }; + + led@2 { + color = <LED_COLOR_ID_BLUE>; + reg = <2>; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = <LED_COLOR_ID_RGB>; + label = "case-led4"; + + led@0 { + color = <LED_COLOR_ID_RED>; + reg = <0>; + }; + + led@1 { + color = <LED_COLOR_ID_GREEN>; + reg = <1>; + }; + + led@2 { + color = <LED_COLOR_ID_BLUE>; + reg = <2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can3_reg: can3reggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can4: can4grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can4_reg: can4reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 + MX8MM_DSE_X1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_reg_m2: reg-m2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_m2>; + vddio-supply = <®_3v3_m2>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_m2>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; -- 2.51.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/5] arm64: dts: freescale: Add the GOcontroll Moduline Mini 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay ` (3 preceding siblings ...) 2025-10-09 10:54 ` [PATCH 4/5] arm64: dts: freescale: Add the GOcontroll Moduline IV Maud Spierings via B4 Relay @ 2025-10-09 10:54 ` Maud Spierings via B4 Relay 4 siblings, 0 replies; 9+ messages in thread From: Maud Spierings via B4 Relay @ 2025-10-09 10:54 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Maud Spierings From: Maud Spierings <maudspierings@gocontroll.com> The Moduline Mini is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. Features: - up to 4 Moduline IO modules - 2 CAN busses - 1 Ethernet - 4 RGB leds - 1 3D accelerometer - optional Wi-Fi/Bluetooth - optional 4G/GPS Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../imx8mm-tx8m-1610-moduline-mini-111.dts | 691 +++++++++++++++++++++ 2 files changed, 692 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b2fef44e0a370..0a84c7dc89e39 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -125,6 +125,7 @@ imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts new file mode 100644 index 0000000000000..651524781a7ba --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings <maudspierings@gocontroll.com> + */ + +/dts-v1/; + +#include "imx8mm-tx8m-1610.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-mini", "fsl,imx8mm"; + hardware = "Moduline Mini V1.11"; + model = "GOcontroll Moduline Mini"; + + aliases { + usb-host = &usbotg2; + usbotg = &usbotg1; + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_comm: regulator-3v3-communication { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_comm>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + /* also powers the cellular modem which can't vote on the regulator */ + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_comm"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + cs-gpios = < + &gpio4 27 GPIO_ACTIVE_LOW + &gpio3 23 GPIO_ACTIVE_LOW + &gpio3 1 GPIO_ACTIVE_LOW + >; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@2 { + compatible = "microchip,mcp3004"; + reg = <2>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + cs-gpios = < + &gpio3 24 GPIO_ACTIVE_LOW + &gpio3 9 GPIO_ACTIVE_LOW + >; + status = "okay"; + + can@0 { + compatible = "microchip,mcp25625"; + reg = <0>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can1_stby>; + }; + + can@1 { + compatible = "microchip,mcp25625"; + reg = <1>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + cs-gpios = < + &gpio1 9 GPIO_ACTIVE_LOW + &gpio1 2 GPIO_ACTIVE_LOW + >; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = <LED_COLOR_ID_RGB>; + label = "case-led1"; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = <LED_COLOR_ID_RGB>; + label = "case-led2"; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = <LED_COLOR_ID_RGB>; + label = "case-led3"; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = <LED_COLOR_ID_RGB>; + label = "case-led4"; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + + accelerometer@18 { + compatible = "st,lis2dw12"; + reg = <0x18>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>, <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_lis_int>; + pinctrl-names = "default"; + vddio-supply = <®_vdd_3v3>; + vdd-supply = <®_vdd_3v3>; + }; + + humidity-sensor@5f { + compatible = "st,hts221"; + reg = <0x5f>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_hts_int>; + pinctrl-names = "default"; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 + MX8MM_DSE_X1 + >; + }; + + pinctrl_hts_int: htsintgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_lis_int: lisintgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_reg_comm: reg_commgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + MX8MM_DSE_X1 + >; + }; + + pinctrl_sysfs_gpios: sysfsgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 + MX8MM_DSE_X1 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_comm>; + vddio-supply = <®_3v3_comm>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_comm>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; -- 2.51.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-10-09 18:26 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-09 10:54 [PATCH 0/5] arm64: dts: freescale: add support for the GOcontroll Moduline IV/Mini Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 1/5] dt-bindings: arm: fsl: Add " Maud Spierings via B4 Relay 2025-10-09 18:26 ` Conor Dooley 2025-10-09 10:54 ` [PATCH 2/5] arm64: dts: imx8mm: Add pinctrl config definitions Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 3/5] arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM Maud Spierings via B4 Relay 2025-10-09 14:48 ` Frank Li 2025-10-09 14:50 ` Maud Spierings 2025-10-09 10:54 ` [PATCH 4/5] arm64: dts: freescale: Add the GOcontroll Moduline IV Maud Spierings via B4 Relay 2025-10-09 10:54 ` [PATCH 5/5] arm64: dts: freescale: Add the GOcontroll Moduline Mini Maud Spierings via B4 Relay
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