[PATCH 0/3] Add device tree support for NVIDIA Tegra CMDQV

[PATCH 0/3] Add device tree support for NVIDIA Tegra CMDQV

[Ashish Mhetre]

This series adds device tree support for the CMDQ-Virtualization (CMDQV)
hardware on NVIDIA Tegra264 SoCs.

CMDQV is a hardware block that works alongside the ARM SMMUv3 to assist in
virtualizing the command queue. It was previously only supported through
ACPI on Tegra241. This series extends the existing driver to support device
tree based initialization, which is required for Tegra264 platforms.

The series is structured as follows:

Patch 1: Extends the tegra241-cmdqv driver to support device tree probing
         alongside the existing ACPI support. The SMMU driver now parses
         the nvidia,cmdqv phandle to associate each SMMU with its
         corresponding CMDQV instance.

Patch 2: Adds device tree binding documentation for nvidia,tegra264-cmdqv
         and extends the arm,smmu-v3 binding with an optional nvidia,cmdqv
         property.

Patch 3: Adds CMDQV device nodes to the Tegra264 device tree and enables
         them on the tegra264-p3834 platform.

The implementation mirrors the existing ACPI probe path to minimize code
divergence and maintain consistency with Tegra241 support.

Ashish Mhetre (3):
  iommu/arm-smmu-v3: Add device-tree support for CMDQV driver
  dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
  arm64: dts: nvidia: Add nodes for CMDQV

 .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
 .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++++
 .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 50 +++++++++++++++++++
 drivers/iommu/arm/Kconfig                     |  1 -
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 30 +++++++++++
 .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c    | 43 +++++++++++++++-
 7 files changed, 186 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

-- 
2.25.1

[PATCH 1/3] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver

[Ashish Mhetre]

Add device tree support to the CMDQV driver to enable usage on Tegra264
SoCs. The implementation mirrors the existing ACPI probe path, parsing
the nvidia,cmdqv phandle from the SMMU device tree node to associate
each SMMU with its corresponding CMDQV instance.

Remove the ACPI dependency from Kconfig as the driver now supports both
ACPI and device tree initialization through conditional compilation.

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
 drivers/iommu/arm/Kconfig                     |  1 -
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 30 +++++++++++++
 .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c    | 43 ++++++++++++++++++-
 3 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig
index ef42bbe07dbe..5fac08b89dee 100644
--- a/drivers/iommu/arm/Kconfig
+++ b/drivers/iommu/arm/Kconfig
@@ -121,7 +121,6 @@ config ARM_SMMU_V3_KUNIT_TEST
 
 config TEGRA241_CMDQV
 	bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"
-	depends on ACPI
 	help
 	  Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The
 	  CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index a33fbd12a0dd..b2657eaa9e17 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -4530,6 +4530,34 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
 	return 0;
 }
 
+#ifdef CONFIG_TEGRA241_CMDQV
+static void tegra_cmdqv_dt_probe(struct device_node *smmu_node,
+				 struct arm_smmu_device *smmu)
+{
+	struct platform_device *pdev;
+	struct device_node *np;
+
+	np = of_parse_phandle(smmu_node, "nvidia,cmdqv", 0);
+	if (!np)
+		return;
+
+	pdev = of_find_device_by_node(np);
+	of_node_put(np);
+	if (!pdev)
+		return;
+
+	smmu->impl_dev = &pdev->dev;
+	smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV;
+	dev_info(smmu->dev, "found companion CMDQV device: %s\n",
+			dev_name(smmu->impl_dev));
+}
+#else
+static void tegra_cmdqv_dt_probe(struct device_node *smmu_node,
+				 struct arm_smmu_device *smmu)
+{
+}
+#endif
+
 #ifdef CONFIG_ACPI
 #ifdef CONFIG_TEGRA241_CMDQV
 static void acpi_smmu_dsdt_probe_tegra241_cmdqv(struct acpi_iort_node *node,
@@ -4634,6 +4662,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
 	if (of_dma_is_coherent(dev->of_node))
 		smmu->features |= ARM_SMMU_FEAT_COHERENCY;
 
+	tegra_cmdqv_dt_probe(dev->of_node, smmu);
+
 	return ret;
 }
 
diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
index 378104cd395e..a5eb8e23083c 100644
--- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
+++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
@@ -11,6 +11,8 @@
 #include <linux/iommufd.h>
 #include <linux/iopoll.h>
 #include <uapi/linux/iommufd.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
 
 #include <acpi/acpixf.h>
 
@@ -917,6 +919,26 @@ tegra241_cmdqv_find_acpi_resource(struct device *dev, int *irq)
 	return res;
 }
 
+static struct resource *
+tegra241_cmdqv_find_dt_resource(struct device *dev, int *irq)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "no memory resource found for CMDQV\n");
+		return NULL;
+	}
+
+	if (irq)
+		*irq = platform_get_irq_byname_optional(pdev, "cmdqv");
+	if (!irq || *irq <= 0)
+		dev_warn(dev, "no interrupt. errors will not be reported\n");
+
+	return res;
+}
+
 static int tegra241_cmdqv_init_structures(struct arm_smmu_device *smmu)
 {
 	struct tegra241_cmdqv *cmdqv =
@@ -1048,11 +1070,14 @@ struct arm_smmu_device *tegra241_cmdqv_probe(struct arm_smmu_device *smmu)
 
 	if (!smmu->dev->of_node)
 		res = tegra241_cmdqv_find_acpi_resource(smmu->impl_dev, &irq);
+	else
+		res = tegra241_cmdqv_find_dt_resource(smmu->impl_dev, &irq);
 	if (!res)
 		goto out_fallback;
 
 	new_smmu = __tegra241_cmdqv_probe(smmu, res, irq);
-	kfree(res);
+	if (!smmu->dev->of_node)
+		kfree(res);
 
 	if (new_smmu)
 		return new_smmu;
@@ -1346,4 +1371,20 @@ tegra241_cmdqv_init_vintf_user(struct arm_vsmmu *vsmmu,
 	return ret;
 }
 
+static const struct of_device_id tegra241_cmdqv_of_match[] = {
+	{ .compatible = "nvidia,tegra264-cmdqv" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, tegra241_cmdqv_of_match);
+
+static struct platform_driver tegra241_cmdqv_driver = {
+	.driver = {
+		.name = "tegra241-cmdqv",
+		.of_match_table = tegra241_cmdqv_of_match,
+	},
+};
+module_platform_driver(tegra241_cmdqv_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra241 Command Queue Virtualization Driver");
+MODULE_LICENSE("GPL");
 MODULE_IMPORT_NS("IOMMUFD");
-- 
2.25.1

[PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Ashish Mhetre]

The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.

Add a new device tree binding document for nvidia,tegra264-cmdqv.

Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
property. This property is a phandle to the CMDQV device node, allowing
the SMMU driver to associate with its corresponding CMDQV instance.

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
 .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
 .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 75fcf4cb52d9..edc0c20a0c80 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -58,6 +58,15 @@ properties:
 
   msi-parent: true
 
+  nvidia,cmdqv:
+    description: |
+      A phandle to its pairing CMDQV extension for an implementation on NVIDIA
+      Tegra SoC.
+
+      If this property is absent, CMDQ-Virtualization won't be used and SMMU
+      will only use its own CMDQ.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
   hisilicon,broken-prefetch-cmd:
     type: boolean
     description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
@@ -92,4 +101,5 @@ examples:
             dma-coherent;
             #iommu-cells = <1>;
             msi-parent = <&its 0xff0000>;
+            nvidia,cmdqv = <&cmdqv>;
     };
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
new file mode 100644
index 000000000000..f22c370278a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 CMDQV
+description: |
+  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
+  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
+
+maintainers:
+  - NVIDIA Corporation <linux-tegra@nvidia.com>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-cmdqv
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    items:
+      - const: cmdqv
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    cmdqv: cmdqv@8105200000 {
+        compatible = "nvidia,tegra264-cmdqv";
+        reg = <0x81 0x05200000 0x0 0x00830000>;
+        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "cmdqv";
+    };
-- 
2.25.1

[PATCH 3/3] arm64: dts: nvidia: Add nodes for CMDQV

[Ashish Mhetre]

The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.

Add device tree nodes for the CMDQV hardware in the Tegra264 SoC
device tree and enable them on the tegra264-p3834 platform where
SMMUs are enabled. Each SMMU instance is paired with its corresponding
CMDQV instance via the nvidia,cmdqv property.

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
 .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 50 +++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 06795c82427a..375d122b92fa 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
@@ -26,5 +26,13 @@ iommu@5000000 {
 		iommu@6000000 {
 			status = "okay";
 		};
+
+		cmdqv@5200000 {
+			status = "okay";
+		};
+
+		cmdqv@6200000 {
+			status = "okay";
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 872a69553e3c..609f6f5f7ef5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -212,6 +212,7 @@ smmu1: iommu@5000000 {
 
 			#iommu-cells = <1>;
 			dma-coherent;
+			nvidia,cmdqv = <&cmdqv1>;
 		};
 
 		smmu2: iommu@6000000 {
@@ -224,6 +225,25 @@ smmu2: iommu@6000000 {
 
 			#iommu-cells = <1>;
 			dma-coherent;
+			nvidia,cmdqv = <&cmdqv2>;
+		};
+
+		cmdqv1: cmdqv@5200000 {
+			compatible = "nvidia,tegra264-cmdqv";
+			status = "disabled";
+
+			reg = <0x00 0x5200000 0x0 0x830000>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cmdqv";
+		};
+
+		cmdqv2: cmdqv@6200000 {
+			compatible = "nvidia,tegra264-cmdqv";
+			status = "disabled";
+
+			reg = <0x00 0x6200000 0x0 0x830000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cmdqv";
 		};
 
 		mc: memory-controller@8020000 {
@@ -288,6 +308,7 @@ smmu0: iommu@a000000 {
 
 			#iommu-cells = <1>;
 			dma-coherent;
+			nvidia,cmdqv = <&cmdqv0>;
 		};
 
 		smmu4: iommu@b000000 {
@@ -300,6 +321,25 @@ smmu4: iommu@b000000 {
 
 			#iommu-cells = <1>;
 			dma-coherent;
+			nvidia,cmdqv = <&cmdqv4>;
+		};
+
+		cmdqv0: cmdqv@a200000 {
+			compatible = "nvidia,tegra264-cmdqv";
+			status = "disabled";
+
+			reg = <0x00 0xa200000 0x0 0x830000>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cmdqv";
+		};
+
+		cmdqv4: cmdqv@b200000 {
+			compatible = "nvidia,tegra264-cmdqv";
+			status = "disabled";
+
+			reg = <0x00 0xb200000 0x0 0x830000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cmdqv";
 		};
 
 		i2c14: i2c@c410000 {
@@ -541,6 +581,16 @@ smmu3: iommu@6000000 {
 
 			#iommu-cells = <1>;
 			dma-coherent;
+			nvidia,cmdqv = <&cmdqv3>;
+		};
+
+		cmdqv3: cmdqv@6200000 {
+			compatible = "nvidia,tegra264-cmdqv";
+			status = "disabled";
+
+			reg = <0x00 0x6200000 0x0 0x830000>;
+			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cmdqv";
 		};
 	};
 
-- 
2.25.1

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Krzysztof Kozlowski]

On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
> The Command Queue Virtualization (CMDQV) hardware is part of the
> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
> virtualizing the command queue for the SMMU.

If this is specific to Nvidia, then I think you need specific front
compatible and disallow it for other vendors.

> 
> Add a new device tree binding document for nvidia,tegra264-cmdqv.
> 
> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
> property. This property is a phandle to the CMDQV device node, allowing
> the SMMU driver to associate with its corresponding CMDQV instance.
> 
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
>  .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>  .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++++++
>  2 files changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index 75fcf4cb52d9..edc0c20a0c80 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -58,6 +58,15 @@ properties:
>  
>    msi-parent: true
>  
> +  nvidia,cmdqv:
> +    description: |
> +      A phandle to its pairing CMDQV extension for an implementation on NVIDIA
> +      Tegra SoC.
> +
> +      If this property is absent, CMDQ-Virtualization won't be used and SMMU
> +      will only use its own CMDQ.
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
>    hisilicon,broken-prefetch-cmd:
>      type: boolean
>      description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
> @@ -92,4 +101,5 @@ examples:
>              dma-coherent;
>              #iommu-cells = <1>;
>              msi-parent = <&its 0xff0000>;
> +            nvidia,cmdqv = <&cmdqv>;
>      };
> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> new file mode 100644
> index 000000000000..f22c370278a3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra264 CMDQV

Missing blank line

> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
> +  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
> +
> +maintainers:
> +  - NVIDIA Corporation <linux-tegra@nvidia.com>

No. It should be a person. If entire Nvidia cannot find a person, I
don't think we are interested in having this in the kernel.

> +
> +properties:
> +  compatible:
> +    const: nvidia,tegra264-cmdqv
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-names:
> +    items:
> +      - const: cmdqv

Drop interript names, obvious.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    cmdqv: cmdqv@8105200000 {

Drop unused label

Best regards,
Krzysztof

Re: [PATCH 1/3] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver

[Nicolin Chen]

On Fri, Oct 31, 2025 at 06:29:57AM +0000, Ashish Mhetre wrote:
> Add device tree support to the CMDQV driver to enable usage on Tegra264
> SoCs. The implementation mirrors the existing ACPI probe path, parsing
> the nvidia,cmdqv phandle from the SMMU device tree node to associate
> each SMMU with its corresponding CMDQV instance.
> 
> Remove the ACPI dependency from Kconfig as the driver now supports both
> ACPI and device tree initialization through conditional compilation.
> 
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>

Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>

With two nits:

> diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig
> index ef42bbe07dbe..5fac08b89dee 100644
> --- a/drivers/iommu/arm/Kconfig
> +++ b/drivers/iommu/arm/Kconfig
> @@ -121,7 +121,6 @@ config ARM_SMMU_V3_KUNIT_TEST
>  
>  config TEGRA241_CMDQV
>  	bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"
> -	depends on ACPI

Perhaps:
depends on OF || ACPI

and update the commit message.

> +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node,
> +				 struct arm_smmu_device *smmu)
> +{
> +	struct platform_device *pdev;
> +	struct device_node *np;
> +
> +	np = of_parse_phandle(smmu_node, "nvidia,cmdqv", 0);
> +	if (!np)
> +		return;
> +
> +	pdev = of_find_device_by_node(np);
> +	of_node_put(np);
> +	if (!pdev)
> +		return;
> +
> +	smmu->impl_dev = &pdev->dev;
> +	smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV;
> +	dev_info(smmu->dev, "found companion CMDQV device: %s\n",
> +			dev_name(smmu->impl_dev));

	dev_info(smmu->dev, "found companion CMDQV device: %s\n",
		 dev_name(smmu->impl_dev));

Nicolin

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Nicolin Chen]

On Fri, Oct 31, 2025 at 09:14:25AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
> > +  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
> > +  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
> > +
> > +maintainers:
> > +  - NVIDIA Corporation <linux-tegra@nvidia.com>
> 
> No. It should be a person. If entire Nvidia cannot find a person, I
> don't think we are interested in having this in the kernel.

I was the submitter of the driver. I can take it up.

Thanks
Nicolin

Re: [PATCH 1/3] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver

[Ashish Mhetre]

On 10/31/2025 10:59 PM, Nicolin Chen wrote:
> On Fri, Oct 31, 2025 at 06:29:57AM +0000, Ashish Mhetre wrote:
>> Add device tree support to the CMDQV driver to enable usage on Tegra264
>> SoCs. The implementation mirrors the existing ACPI probe path, parsing
>> the nvidia,cmdqv phandle from the SMMU device tree node to associate
>> each SMMU with its corresponding CMDQV instance.
>>
>> Remove the ACPI dependency from Kconfig as the driver now supports both
>> ACPI and device tree initialization through conditional compilation.
>>
>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
>
> With two nits:

Thanks Nic, I'll address these in next version and add reviewed by.
>> diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig
>> index ef42bbe07dbe..5fac08b89dee 100644
>> --- a/drivers/iommu/arm/Kconfig
>> +++ b/drivers/iommu/arm/Kconfig
>> @@ -121,7 +121,6 @@ config ARM_SMMU_V3_KUNIT_TEST
>>   
>>   config TEGRA241_CMDQV
>>   	bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3"
>> -	depends on ACPI
> Perhaps:
> depends on OF || ACPI
>
> and update the commit message.

Sure, I will fix this in V2.
>> +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node,
>> +				 struct arm_smmu_device *smmu)
>> +{
>> +	struct platform_device *pdev;
>> +	struct device_node *np;
>> +
>> +	np = of_parse_phandle(smmu_node, "nvidia,cmdqv", 0);
>> +	if (!np)
>> +		return;
>> +
>> +	pdev = of_find_device_by_node(np);
>> +	of_node_put(np);
>> +	if (!pdev)
>> +		return;
>> +
>> +	smmu->impl_dev = &pdev->dev;
>> +	smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV;
>> +	dev_info(smmu->dev, "found companion CMDQV device: %s\n",
>> +			dev_name(smmu->impl_dev));
> 	dev_info(smmu->dev, "found companion CMDQV device: %s\n",
> 		 dev_name(smmu->impl_dev));

Ack,  I'll fix this in next version
> Nicolin

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Ashish Mhetre]

On 10/31/2025 1:44 PM, Krzysztof Kozlowski wrote:
> External email: Use caution opening links or attachments
>
>
> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
>> The Command Queue Virtualization (CMDQV) hardware is part of the
>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>> virtualizing the command queue for the SMMU.
> If this is specific to Nvidia, then I think you need specific front
> compatible and disallow it for other vendors.

Yes, CMDQV is specific to Nvidia. There isn't currently a vendor-specific
compatible for Nvidia's arm,smmu-v3 implementation. Would it be acceptable
to document this as Nvidia-specific in the description? Or can we add a
new Nvidia-specific compatible string like "nvidia,smmu-v3" if that's
preferred and use conditional schema to restrict the property?
>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>
>> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
>> property. This property is a phandle to the CMDQV device node, allowing
>> the SMMU driver to associate with its corresponding CMDQV instance.
>>
>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>> ---
>>   .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++++++
>>   2 files changed, 56 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> index 75fcf4cb52d9..edc0c20a0c80 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>> @@ -58,6 +58,15 @@ properties:
>>
>>     msi-parent: true
>>
>> +  nvidia,cmdqv:
>> +    description: |
>> +      A phandle to its pairing CMDQV extension for an implementation on NVIDIA
>> +      Tegra SoC.
>> +
>> +      If this property is absent, CMDQ-Virtualization won't be used and SMMU
>> +      will only use its own CMDQ.
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +
>>     hisilicon,broken-prefetch-cmd:
>>       type: boolean
>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>> @@ -92,4 +101,5 @@ examples:
>>               dma-coherent;
>>               #iommu-cells = <1>;
>>               msi-parent = <&its 0xff0000>;
>> +            nvidia,cmdqv = <&cmdqv>;
>>       };
>> diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>> new file mode 100644
>> index 000000000000..f22c370278a3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra264 CMDQV
> Missing blank line

Ack, I will correct this in V2.
>> +description: |
> Do not need '|' unless you need to preserve formatting.

Okay, I'll remove this in next version.
>> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
>> +  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
>> +
>> +maintainers:
>> +  - NVIDIA Corporation <linux-tegra@nvidia.com>
> No. It should be a person. If entire Nvidia cannot find a person, I
> don't think we are interested in having this in the kernel.

Okay, I'll add Nicolin as maintainer.
>> +
>> +properties:
>> +  compatible:
>> +    const: nvidia,tegra264-cmdqv
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  interrupt-names:
>> +    items:
>> +      - const: cmdqv
> Drop interript names, obvious.

Sure, I will update in V2.
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    cmdqv: cmdqv@8105200000 {
> Drop unused label

Okay, I will remove the label.
> Best regards,
> Krzysztof
>

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Ashish Mhetre]

On 11/3/2025 7:24 PM, Ashish Mhetre wrote:
>
> On 10/31/2025 1:44 PM, Krzysztof Kozlowski wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
>>> The Command Queue Virtualization (CMDQV) hardware is part of the
>>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>>> virtualizing the command queue for the SMMU.
>> If this is specific to Nvidia, then I think you need specific front
>> compatible and disallow it for other vendors.
>
> Yes, CMDQV is specific to Nvidia. There isn't currently a vendor-specific
> compatible for Nvidia's arm,smmu-v3 implementation. Would it be 
> acceptable
> to document this as Nvidia-specific in the description? Or can we add a
> new Nvidia-specific compatible string like "nvidia,smmu-v3" if that's
> preferred and use conditional schema to restrict the property?

Hi Krzysztof, Thierry,
Any suggestions on this?

>>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>>
>>> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
>>> property. This property is a phandle to the CMDQV device node, allowing
>>> the SMMU driver to associate with its corresponding CMDQV instance.
>>>
>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>> ---
>>>   .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 
>>> +++++++++++++++++++
>>>   2 files changed, 56 insertions(+)
>>>   create mode 100644 
>>> Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml 
>>> b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> index 75fcf4cb52d9..edc0c20a0c80 100644
>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> @@ -58,6 +58,15 @@ properties:
>>>
>>>     msi-parent: true
>>>
>>> +  nvidia,cmdqv:
>>> +    description: |
>>> +      A phandle to its pairing CMDQV extension for an 
>>> implementation on NVIDIA
>>> +      Tegra SoC.
>>> +
>>> +      If this property is absent, CMDQ-Virtualization won't be used 
>>> and SMMU
>>> +      will only use its own CMDQ.
>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>> +
>>>     hisilicon,broken-prefetch-cmd:
>>>       type: boolean
>>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>>> @@ -92,4 +101,5 @@ examples:
>>>               dma-coherent;
>>>               #iommu-cells = <1>;
>>>               msi-parent = <&its 0xff0000>;
>>> +            nvidia,cmdqv = <&cmdqv>;
>>>       };
>>> diff --git 
>>> a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml 
>>> b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>> new file mode 100644
>>> index 000000000000..f22c370278a3
>>> --- /dev/null
>>> +++ 
>>> b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>> @@ -0,0 +1,46 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: NVIDIA Tegra264 CMDQV
>> Missing blank line
>
> Ack, I will correct this in V2.
>>> +description: |
>> Do not need '|' unless you need to preserve formatting.
>
> Okay, I'll remove this in next version.
>>> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 
>>> implementation
>>> +  on Tegra264 SoCs. It assists in virtualizing the command queue 
>>> for the SMMU.
>>> +
>>> +maintainers:
>>> +  - NVIDIA Corporation <linux-tegra@nvidia.com>
>> No. It should be a person. If entire Nvidia cannot find a person, I
>> don't think we are interested in having this in the kernel.
>
> Okay, I'll add Nicolin as maintainer.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: nvidia,tegra264-cmdqv
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: cmdqv
>> Drop interript names, obvious.
>
> Sure, I will update in V2.
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - interrupt-names
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> +    cmdqv: cmdqv@8105200000 {
>> Drop unused label
>
> Okay, I will remove the label.
>> Best regards,
>> Krzysztof
>>

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Ashish Mhetre]

On 11/3/2025 7:24 PM, Ashish Mhetre wrote:
>
> On 10/31/2025 1:44 PM, Krzysztof Kozlowski wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
>>> The Command Queue Virtualization (CMDQV) hardware is part of the
>>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>>> virtualizing the command queue for the SMMU.
>> If this is specific to Nvidia, then I think you need specific front
>> compatible and disallow it for other vendors.
>
> Yes, CMDQV is specific to Nvidia. There isn't currently a vendor-specific
> compatible for Nvidia's arm,smmu-v3 implementation. Would it be 
> acceptable
> to document this as Nvidia-specific in the description? Or can we add a
> new Nvidia-specific compatible string like "nvidia,smmu-v3" if that's
> preferred and use conditional schema to restrict the property?

Hi Will, Robin,

Do you have any suggestions on this? I have followed existing ACPI approach
for implementing DT support. Will it be fine to add separate compatible 
string
for Nvidia Tegra264 SMMU to restrict the usage of CMDQV?

>>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>>
>>> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
>>> property. This property is a phandle to the CMDQV device node, allowing
>>> the SMMU driver to associate with its corresponding CMDQV instance.
>>>
>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>> ---
>>>   .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 
>>> +++++++++++++++++++
>>>   2 files changed, 56 insertions(+)
>>>   create mode 100644 
>>> Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml 
>>> b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> index 75fcf4cb52d9..edc0c20a0c80 100644
>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>> @@ -58,6 +58,15 @@ properties:
>>>
>>>     msi-parent: true
>>>
>>> +  nvidia,cmdqv:
>>> +    description: |
>>> +      A phandle to its pairing CMDQV extension for an 
>>> implementation on NVIDIA
>>> +      Tegra SoC.
>>> +
>>> +      If this property is absent, CMDQ-Virtualization won't be used 
>>> and SMMU
>>> +      will only use its own CMDQ.
>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>> +
>>>     hisilicon,broken-prefetch-cmd:
>>>       type: boolean
>>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>>> @@ -92,4 +101,5 @@ examples:
>>>               dma-coherent;
>>>               #iommu-cells = <1>;
>>>               msi-parent = <&its 0xff0000>;
>>> +            nvidia,cmdqv = <&cmdqv>;
>>>       };
>>> diff --git 
>>> a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml 
>>> b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>> new file mode 100644
>>> index 000000000000..f22c370278a3
>>> --- /dev/null
>>> +++ 
>>> b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
>>> @@ -0,0 +1,46 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: NVIDIA Tegra264 CMDQV
>> Missing blank line
>
> Ack, I will correct this in V2.
>>> +description: |
>> Do not need '|' unless you need to preserve formatting.
>
> Okay, I'll remove this in next version.
>>> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 
>>> implementation
>>> +  on Tegra264 SoCs. It assists in virtualizing the command queue 
>>> for the SMMU.
>>> +
>>> +maintainers:
>>> +  - NVIDIA Corporation <linux-tegra@nvidia.com>
>> No. It should be a person. If entire Nvidia cannot find a person, I
>> don't think we are interested in having this in the kernel.
>
> Okay, I'll add Nicolin as maintainer.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: nvidia,tegra264-cmdqv
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-names:
>>> +    items:
>>> +      - const: cmdqv
>> Drop interript names, obvious.
>
> Sure, I will update in V2.
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - interrupt-names
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +
>>> +    cmdqv: cmdqv@8105200000 {
>> Drop unused label
>
> Okay, I will remove the label.
>> Best regards,
>> Krzysztof
>>

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Robin Murphy]

On 2025-11-20 6:07 am, Ashish Mhetre wrote:
> 
> On 11/3/2025 7:24 PM, Ashish Mhetre wrote:
>>
>> On 10/31/2025 1:44 PM, Krzysztof Kozlowski wrote:
>>> External email: Use caution opening links or attachments
>>>
>>>
>>> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
>>>> The Command Queue Virtualization (CMDQV) hardware is part of the
>>>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>>>> virtualizing the command queue for the SMMU.
>>> If this is specific to Nvidia, then I think you need specific front
>>> compatible and disallow it for other vendors.
>>
>> Yes, CMDQV is specific to Nvidia. There isn't currently a vendor-specific
>> compatible for Nvidia's arm,smmu-v3 implementation. Would it be 
>> acceptable
>> to document this as Nvidia-specific in the description? Or can we add a
>> new Nvidia-specific compatible string like "nvidia,smmu-v3" if that's
>> preferred and use conditional schema to restrict the property?
> 
> Hi Will, Robin,
> 
> Do you have any suggestions on this? I have followed existing ACPI approach
> for implementing DT support.

No, the way the ACPI binding is implemented has the lookup going *from* 
the CMDQV node back to the SMMU instance (via the matching identifier) - 
this is entirely the opposite. The literal DT equivalent would be to use 
for_each_matching_node/for_each_compatible_node to scan the CMDQV nodes 
for a property indicating the relevant SMMU.

I'm not hugely fussed either way though - since the fact is the Tegra234 
SMMU does have this custom modification, a specific 
"nvidia,tegra234-smmu", "arm,smmu-v3" compatible isn't inappropriate, 
even if it really doesn't make any difference to architectural SMMU 
operation without awareness of the other CMDQV nodes.

Thanks,
Robin.

> Will it be fine to add separate compatible 
> string
> for Nvidia Tegra264 SMMU to restrict the usage of CMDQV?
> 
>>>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>>>
>>>> Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
>>>> property. This property is a phandle to the CMDQV device node, allowing
>>>> the SMMU driver to associate with its corresponding CMDQV instance.
>>>>
>>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>>> ---
>>>>   .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>>>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++ 
>>>> ++++
>>>>   2 files changed, 56 insertions(+)
>>>>   create mode 100644 Documentation/devicetree/bindings/iommu/ 
>>>> nvidia,tegra264-cmdqv.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu- 
>>>> v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>> index 75fcf4cb52d9..edc0c20a0c80 100644
>>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>> @@ -58,6 +58,15 @@ properties:
>>>>
>>>>     msi-parent: true
>>>>
>>>> +  nvidia,cmdqv:
>>>> +    description: |
>>>> +      A phandle to its pairing CMDQV extension for an 
>>>> implementation on NVIDIA
>>>> +      Tegra SoC.
>>>> +
>>>> +      If this property is absent, CMDQ-Virtualization won't be used 
>>>> and SMMU
>>>> +      will only use its own CMDQ.
>>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>>> +
>>>>     hisilicon,broken-prefetch-cmd:
>>>>       type: boolean
>>>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>>>> @@ -92,4 +101,5 @@ examples:
>>>>               dma-coherent;
>>>>               #iommu-cells = <1>;
>>>>               msi-parent = <&its 0xff0000>;
>>>> +            nvidia,cmdqv = <&cmdqv>;
>>>>       };
>>>> diff --git a/Documentation/devicetree/bindings/iommu/ 
>>>> nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/ 
>>>> iommu/nvidia,tegra264-cmdqv.yaml
>>>> new file mode 100644
>>>> index 000000000000..f22c370278a3
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264- 
>>>> cmdqv.yaml
>>>> @@ -0,0 +1,46 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: NVIDIA Tegra264 CMDQV
>>> Missing blank line
>>
>> Ack, I will correct this in V2.
>>>> +description: |
>>> Do not need '|' unless you need to preserve formatting.
>>
>> Okay, I'll remove this in next version.
>>>> +  The CMDQ-Virtualization hardware block is part of the SMMUv3 
>>>> implementation
>>>> +  on Tegra264 SoCs. It assists in virtualizing the command queue 
>>>> for the SMMU.
>>>> +
>>>> +maintainers:
>>>> +  - NVIDIA Corporation <linux-tegra@nvidia.com>
>>> No. It should be a person. If entire Nvidia cannot find a person, I
>>> don't think we are interested in having this in the kernel.
>>
>> Okay, I'll add Nicolin as maintainer.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: nvidia,tegra264-cmdqv
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  interrupts:
>>>> +    maxItems: 1
>>>> +
>>>> +  interrupt-names:
>>>> +    items:
>>>> +      - const: cmdqv
>>> Drop interript names, obvious.
>>
>> Sure, I will update in V2.
>>>> +
>>>> +required:
>>>> +  - compatible
>>>> +  - reg
>>>> +  - interrupts
>>>> +  - interrupt-names
>>>> +
>>>> +additionalProperties: false
>>>> +
>>>> +examples:
>>>> +  - |
>>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>>> +
>>>> +    cmdqv: cmdqv@8105200000 {
>>> Drop unused label
>>
>> Okay, I will remove the label.
>>> Best regards,
>>> Krzysztof
>>>

Re: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

[Ashish Mhetre]

On 11/20/2025 3:53 PM, Robin Murphy wrote:
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>
>
> On 2025-11-20 6:07 am, Ashish Mhetre wrote:
>>
>> On 11/3/2025 7:24 PM, Ashish Mhetre wrote:
>>>
>>> On 10/31/2025 1:44 PM, Krzysztof Kozlowski wrote:
>>>> External email: Use caution opening links or attachments
>>>>
>>>>
>>>> On Fri, Oct 31, 2025 at 06:29:58AM +0000, Ashish Mhetre wrote:
>>>>> The Command Queue Virtualization (CMDQV) hardware is part of the
>>>>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>>>>> virtualizing the command queue for the SMMU.
>>>> If this is specific to Nvidia, then I think you need specific front
>>>> compatible and disallow it for other vendors.
>>>
>>> Yes, CMDQV is specific to Nvidia. There isn't currently a 
>>> vendor-specific
>>> compatible for Nvidia's arm,smmu-v3 implementation. Would it be
>>> acceptable
>>> to document this as Nvidia-specific in the description? Or can we add a
>>> new Nvidia-specific compatible string like "nvidia,smmu-v3" if that's
>>> preferred and use conditional schema to restrict the property?
>>
>> Hi Will, Robin,
>>
>> Do you have any suggestions on this? I have followed existing ACPI 
>> approach
>> for implementing DT support.
>
> No, the way the ACPI binding is implemented has the lookup going *from*
> the CMDQV node back to the SMMU instance (via the matching identifier) -
> this is entirely the opposite. The literal DT equivalent would be to use
> for_each_matching_node/for_each_compatible_node to scan the CMDQV nodes
> for a property indicating the relevant SMMU.
>
> I'm not hugely fussed either way though - since the fact is the Tegra234
> SMMU does have this custom modification, a specific
> "nvidia,tegra234-smmu", "arm,smmu-v3" compatible isn't inappropriate,
> even if it really doesn't make any difference to architectural SMMU
> operation without awareness of the other CMDQV nodes.
>
> Thanks,
> Robin.
>

Thanks for the suggestions Robin. Approach 2 is much simpler with current
implementation I have. I will proceed with adding Nvidia specific compatible
string "nvidia,tegra264-smmu", "arm,smmu-v3" in V2.

>> Will it be fine to add separate compatible
>> string
>> for Nvidia Tegra264 SMMU to restrict the usage of CMDQV?
>>
>>>>> Add a new device tree binding document for nvidia,tegra264-cmdqv.
>>>>>
>>>>> Also update the arm,smmu-v3 binding to include an optional 
>>>>> nvidia,cmdqv
>>>>> property. This property is a phandle to the CMDQV device node, 
>>>>> allowing
>>>>> the SMMU driver to associate with its corresponding CMDQV instance.
>>>>>
>>>>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>>>>> ---
>>>>>   .../bindings/iommu/arm,smmu-v3.yaml           | 10 ++++
>>>>>   .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++
>>>>> ++++
>>>>>   2 files changed, 56 insertions(+)
>>>>>   create mode 100644 Documentation/devicetree/bindings/iommu/
>>>>> nvidia,tegra264-cmdqv.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-
>>>>> v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>>> index 75fcf4cb52d9..edc0c20a0c80 100644
>>>>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
>>>>> @@ -58,6 +58,15 @@ properties:
>>>>>
>>>>>     msi-parent: true
>>>>>
>>>>> +  nvidia,cmdqv:
>>>>> +    description: |
>>>>> +      A phandle to its pairing CMDQV extension for an
>>>>> implementation on NVIDIA
>>>>> +      Tegra SoC.
>>>>> +
>>>>> +      If this property is absent, CMDQ-Virtualization won't be used
>>>>> and SMMU
>>>>> +      will only use its own CMDQ.
>>>>> +    $ref: /schemas/types.yaml#/definitions/phandle
>>>>> +
>>>>>     hisilicon,broken-prefetch-cmd:
>>>>>       type: boolean
>>>>>       description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
>>>>> @@ -92,4 +101,5 @@ examples:
>>>>>               dma-coherent;
>>>>>               #iommu-cells = <1>;
>>>>>               msi-parent = <&its 0xff0000>;
>>>>> +            nvidia,cmdqv = <&cmdqv>;
>>>>>       };
>>>>> diff --git a/Documentation/devicetree/bindings/iommu/
>>>>> nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/
>>>>> iommu/nvidia,tegra264-cmdqv.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..f22c370278a3
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-
>>>>> cmdqv.yaml
>>>>> @@ -0,0 +1,46 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: NVIDIA Tegra264 CMDQV
>>>> Missing blank line
>>>
>>> Ack, I will correct this in V2.
>>>>> +description: |
>>>> Do not need '|' unless you need to preserve formatting.
>>>
>>> Okay, I'll remove this in next version.
>>>>> +  The CMDQ-Virtualization hardware block is part of the SMMUv3
>>>>> implementation
>>>>> +  on Tegra264 SoCs. It assists in virtualizing the command queue
>>>>> for the SMMU.
>>>>> +
>>>>> +maintainers:
>>>>> +  - NVIDIA Corporation <linux-tegra@nvidia.com>
>>>> No. It should be a person. If entire Nvidia cannot find a person, I
>>>> don't think we are interested in having this in the kernel.
>>>
>>> Okay, I'll add Nicolin as maintainer.
>>>>> +
>>>>> +properties:
>>>>> +  compatible:
>>>>> +    const: nvidia,tegra264-cmdqv
>>>>> +
>>>>> +  reg:
>>>>> +    maxItems: 1
>>>>> +
>>>>> +  interrupts:
>>>>> +    maxItems: 1
>>>>> +
>>>>> +  interrupt-names:
>>>>> +    items:
>>>>> +      - const: cmdqv
>>>> Drop interript names, obvious.
>>>
>>> Sure, I will update in V2.
>>>>> +
>>>>> +required:
>>>>> +  - compatible
>>>>> +  - reg
>>>>> +  - interrupts
>>>>> +  - interrupt-names
>>>>> +
>>>>> +additionalProperties: false
>>>>> +
>>>>> +examples:
>>>>> +  - |
>>>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>>>> +
>>>>> +    cmdqv: cmdqv@8105200000 {
>>>> Drop unused label
>>>
>>> Okay, I will remove the label.
>>>> Best regards,
>>>> Krzysztof
>>>>