[PATCH 0/4] arm64: insn: fix sysreg encodings, simplify dependent code

[PATCH 0/4] arm64: insn: fix sysreg encodings, simplify dependent code

[Ada Couprie Diaz]

Hello,

This is a follow-up to [0] which goes further than initially anticipated.
Indeed, after Vladimir's comment I checked what was going on
in more details and realized that the system register definitions had some
mistakes, were quite inconsistent and duplicated the sysreg definitions
in `arch/arm64/include/sysreg.h`.

Thus this series takes the approach of re-using the encodings we already
define and depend on, and making easier to re-use if needed.
That meant I could also clean up unecessary operations and distinctions.

This simplification _could_ be taken further by completely removing the
insn enum in favour of using the sysreg.h definitions directly,
but I figured it was useful to keep the enum for typing/argument hints.

I was unsure of how to split this series, so patch 2 and 3 could reasonably
be squashed into patch 4 if that does not make the commit too unscrutable.

Thank you in advance,
Ada

[0]: https://lore.kernel.org/r/20260928133034.243541-1-ada.coupriediaz@arm.com 

Ada Couprie Diaz (4):
  arm64: sysreg: generate TPIDR, SP and DAIF encodings
  arm64: insn: fix system register inconsistencies
  arm64: insn: operate on MSR/MRS sysreg field via defines
  arm64: insn: clean-up sysregs handling

 arch/arm64/include/asm/insn.h          | 41 ++++++++++----------------
 arch/arm64/include/asm/sysreg.h        |  8 -----
 arch/arm64/kernel/probes/decode-insn.c |  2 +-
 arch/arm64/lib/insn.c                  |  8 ++---
 arch/arm64/tools/sysreg                | 37 +++++++++++++++++++++++
 5 files changed, 57 insertions(+), 39 deletions(-)


base-commit: 93f51579e7df248780214094418f205253383cc5
-- 
2.43.0

[PATCH 1/4] arm64: sysreg: generate TPIDR, SP and DAIF encodings

[Ada Couprie Diaz]

Introduce missing SYS_DAIF and SYS_SP_EL0 encodings in preparation
for a future commit.
While we are here, replace SYS_SP_EL{1,2} manual encodings with
automatically generated ones.

As the future commit will make use of SYS_TPIDR_EL{1,2} encodings,
replace their and related registers manual encodings with
automatically generated ones as well.

Clean up manual `SYS_CONTEXTIDR_EL2` definition, as it was already
generated.

Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
 arch/arm64/include/asm/sysreg.h |  8 -------
 arch/arm64/tools/sysreg         | 37 +++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7aa08d59d4944..7948b8c74cf49 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -418,10 +418,6 @@
 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
 
-#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
-#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
-#define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
-
 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
 
 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
@@ -520,7 +516,6 @@
 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
-#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
 #define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
 #define SYS_SPSR_abt			sys_reg(3, 4, 4, 3, 1)
 #define SYS_SPSR_und			sys_reg(3, 4, 4, 3, 2)
@@ -580,8 +575,6 @@
 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
 
-#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
-#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
 #define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)
 
 #define __AMEV_op2(m)			(m & 0x7)
@@ -623,7 +616,6 @@
 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
 
-#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
 
 /* AT instructions */
 #define AT_Op0 1
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index e2d37ee221b84..7349744f14211 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2958,6 +2958,10 @@ Res0	4:1
 Field	0	PCRSEL
 EndSysreg
 
+Sysreg	SP_EL0	3	0	4	1	0
+Field	63:0	SP
+EndSysreg
+
 Sysreg	ALLINT	3	0	4	3	0
 Res0	63:14
 Field	13	ALLINT
@@ -3811,6 +3815,15 @@ Sysreg	GCSPR_EL0	3	3	2	5	1
 Fields	GCSPR_ELx
 EndSysreg
 
+Sysreg	DAIF	3	3	4	2	1
+Res0	63:10
+Field	9	D
+Field	8	A
+Field	7	I
+Field	6	F
+Res0	5:0
+EndSysreg
+
 Sysreg	SVCR	3	3	4	2	2
 Res0	63:2
 Field	1	ZA
@@ -3885,6 +3898,22 @@ UnsignedEnum	2:0	F8S1
 EndEnum
 EndSysreg
 
+Sysreg	TPIDR_EL0	3	3	13	0	2
+Field	63:0	ThreadID
+EndSysreg
+
+Sysreg	TPIDRRO_EL0	3	3	13	0	3
+Field	63:0	ThreadID
+EndSysreg
+
+Sysreg	TPIDR2_EL0	3	3	13	0	5
+Field	63:0	ThreadID
+EndSysreg
+
+Sysreg	SP_EL1	3	4	4	1	0
+Field	63:0	SP
+EndSysreg
+
 Sysreg	SCTLR_EL2	3	4	1	0	0
 Field	63	TIDCP
 Field	62	SPINTMASK
@@ -5425,6 +5454,10 @@ Sysreg	CONTEXTIDR_EL2	3	4	13	0	1
 Fields	CONTEXTIDR_ELx
 EndSysreg
 
+Sysreg	TPIDR_EL2	3	4	13	0	2
+Field	63:0	ThreadID
+EndSysreg
+
 Sysreg	CNTPOFF_EL2	3	4	14	0	6
 Field	63:0	PhysicalOffset
 EndSysreg
@@ -5465,6 +5498,10 @@ Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
 Mapping	CONTEXTIDR_EL1
 EndSysreg
 
+Sysreg	SP_EL2	3	6	4	1	0
+Field	63:0	SP
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field	63:48	ASID
 Field	47:1	BADDR
-- 
2.43.0

[PATCH 2/4] arm64: insn: fix system register inconsistencies

[Ada Couprie Diaz]

Two registers in `enum aarch64_insn_special_register` are defined
incorrectly :
 - SPSR_IRQ is named SPSR_I*N*Q
 - SP_EL2's encoding is incorrect and does not correspond to ant register

Fix those issues and re-order the registers by value.
Update `enum aarch64_insn_system_register` values and order to be in line
with `enum aarch64_insn_special_register`, so that we can make
`aarch64_insn_gen_mrs()` use the same mask as
`aarch64_insn_extract_system_reg()` while we're here.

This does not change the behaviour, as `aarch64_insn_encode_register()`
always masks the lower bits and the top bit of registers are always set.

Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
 arch/arm64/include/asm/insn.h | 12 ++++++------
 arch/arm64/lib/insn.c         |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index c91a8431c961e..2e45f6e80d15f 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -119,27 +119,27 @@ enum aarch64_insn_special_register {
 	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
 	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
 	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
-	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
 	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
+	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
 	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
 	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
 	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
 	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
 	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
 	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
-	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
+	AARCH64_INSN_SPCLREG_SPSR_IRQ	= 0xE218,
 	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
 	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
 	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
 	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
 	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
-	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
+	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF208,
 };
 
 enum aarch64_insn_system_register {
-	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0x4684,
-	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0x6682,
-	AARCH64_INSN_SYSREG_SP_EL0	= 0x4208,
+	AARCH64_INSN_SYSREG_SP_EL0	= 0xC208,
+	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0xC684,
+	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0xE682,
 };
 
 enum aarch64_insn_variant {
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 5c37f3a4c402b..94ee1aae2f5b7 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -1566,7 +1566,7 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
 {
 	u32 insn = aarch64_insn_get_mrs_value();
 
-	insn &= ~GENMASK(19, 0);
+	insn &= ~GENMASK(20, 5);
 	insn |= sysreg << 5;
 	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
 					    insn, result);
-- 
2.43.0

[PATCH 3/4] arm64: insn: operate on MSR/MRS sysreg field via defines

[Ada Couprie Diaz]

Replace the few instances of hard-coded system register offset and masks
used to operate on MSR/MRS instructions with defines.
This will allow re-use in future commits while making the connection
between those values more explicit.

While we are here, mark `aarch64_insn_extract_system_reg()` `noinstr`
so it can be safe to use in alternative pacthing callbacks.

Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
 arch/arm64/include/asm/insn.h | 3 +++
 arch/arm64/lib/insn.c         | 8 ++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 2e45f6e80d15f..e020f9d8b83c2 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -113,6 +113,9 @@ enum aarch64_insn_register {
 	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 };
 
+#define AARCH64_INSN_SYSREG_OFFSET	5
+#define AARCH64_INSN_SYSREG_MASK	GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
+
 enum aarch64_insn_special_register {
 	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
 	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 94ee1aae2f5b7..2edc5a9c0a9c8 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -1362,9 +1362,9 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
 /*
  * Extract the Op/CR data from a msr/mrs instruction.
  */
-u32 aarch64_insn_extract_system_reg(u32 insn)
+noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
 {
-	return (insn & 0x1FFFE0) >> 5;
+	return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
 }
 
 bool aarch32_insn_is_wide(u32 insn)
@@ -1566,8 +1566,8 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
 {
 	u32 insn = aarch64_insn_get_mrs_value();
 
-	insn &= ~GENMASK(20, 5);
-	insn |= sysreg << 5;
+	insn &= ~AARCH64_INSN_SYSREG_MASK;
+	insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
 	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
 					    insn, result);
 }
-- 
2.43.0

[PATCH 4/4] arm64: insn: clean-up sysregs handling

[Ada Couprie Diaz]

System register encodings are already defined in <asm/sysreg.h>, so
use those definitions in <asm/insn.h> instead of duplicating them.
This will avoid future errors and deviations.

Remove the unnecessary shifts for encoding/decoding now that the enum
values directly match the encoded registers.

No code using the insn register encodings currently makes a distinction
between "regular" system registers and special-purpose registers,
so let's just drop the difference and merge the two enums.
Remove all unused registers while we are here.

Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
---
 arch/arm64/include/asm/insn.h          | 36 ++++++++------------------
 arch/arm64/kernel/probes/decode-insn.c |  2 +-
 arch/arm64/lib/insn.c                  |  4 +--
 3 files changed, 14 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index e020f9d8b83c2..6533191638804 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 
 #include <asm/insn-def.h>
+#include <asm/sysreg.h>
 
 #ifndef __ASSEMBLER__
 
@@ -113,38 +114,23 @@ enum aarch64_insn_register {
 	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 };
 
+/* System register encoding for MRS/MSR (register) instructions. */
 #define AARCH64_INSN_SYSREG_OFFSET	5
 #define AARCH64_INSN_SYSREG_MASK	GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
+#define AARCH64_INSN_SYSREG_FROM_DEF(sysreg) \
+	AARCH64_INSN_SYSREG_##sysreg = SYS_##sysreg
 
-enum aarch64_insn_special_register {
-	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
-	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
-	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
-	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
-	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
-	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
-	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
-	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
-	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
-	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
-	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
-	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
-	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
-	AARCH64_INSN_SPCLREG_SPSR_IRQ	= 0xE218,
-	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
-	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
-	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
-	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
-	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
-	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF208,
-};
 
+/* Do not duplicate encodings: we already define them in <asm/sysreg.h> */
 enum aarch64_insn_system_register {
-	AARCH64_INSN_SYSREG_SP_EL0	= 0xC208,
-	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0xC684,
-	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0xE682,
+	AARCH64_INSN_SYSREG_FROM_DEF(SP_EL0),
+	AARCH64_INSN_SYSREG_FROM_DEF(TPIDR_EL1),
+	AARCH64_INSN_SYSREG_FROM_DEF(DAIF),
+	AARCH64_INSN_SYSREG_FROM_DEF(TPIDR_EL2),
 };
 
+#undef AARCH64_INSN_SYSREG_FROM_DEF
+
 enum aarch64_insn_variant {
 	AARCH64_INSN_VARIANT_32BIT,
 	AARCH64_INSN_VARIANT_64BIT
diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c
index 4137cc5ef031f..bb0af08105885 100644
--- a/arch/arm64/kernel/probes/decode-insn.c
+++ b/arch/arm64/kernel/probes/decode-insn.c
@@ -40,7 +40,7 @@ static bool __kprobes aarch64_insn_is_steppable(u32 insn)
 		 */
 		if (aarch64_insn_is_mrs(insn))
 			return aarch64_insn_extract_system_reg(insn)
-			     != AARCH64_INSN_SPCLREG_DAIF;
+			     != AARCH64_INSN_SYSREG_DAIF;
 
 		/*
 		 * The HINT instruction is steppable only if it is in whitelist
diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
index 2edc5a9c0a9c8..1611c86885c9f 100644
--- a/arch/arm64/lib/insn.c
+++ b/arch/arm64/lib/insn.c
@@ -1364,7 +1364,7 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
  */
 noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
 {
-	return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
+	return insn & AARCH64_INSN_SYSREG_MASK;
 }
 
 bool aarch32_insn_is_wide(u32 insn)
@@ -1567,7 +1567,7 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
 	u32 insn = aarch64_insn_get_mrs_value();
 
 	insn &= ~AARCH64_INSN_SYSREG_MASK;
-	insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
+	insn |= sysreg;
 	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
 					    insn, result);
 }
-- 
2.43.0

Re: [PATCH 1/4] arm64: sysreg: generate TPIDR, SP and DAIF encodings

[Vladimir Murzin]

On 10/16/26 17:46, Ada Couprie Diaz wrote:
> Introduce missing SYS_DAIF and SYS_SP_EL0 encodings in preparation
> for a future commit.
> While we are here, replace SYS_SP_EL{1,2} manual encodings with
> automatically generated ones.
> 
> As the future commit will make use of SYS_TPIDR_EL{1,2} encodings,
> replace their and related registers manual encodings with
> automatically generated ones as well.
> 
> Clean up manual `SYS_CONTEXTIDR_EL2` definition, as it was already
> generated.
> 
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> ---
>  arch/arm64/include/asm/sysreg.h |  8 -------
>  arch/arm64/tools/sysreg         | 37 +++++++++++++++++++++++++++++++++
>  2 files changed, 37 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7aa08d59d4944..7948b8c74cf49 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -418,10 +418,6 @@
>  #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
>  #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
>  
> -#define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
> -#define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
> -#define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
> -
>  #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
>  
>  /* Definitions for system register interface to AMU for ARMv8.4 onwards */
> @@ -520,7 +516,6 @@
>  #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
>  #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
>  #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
> -#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
>  #define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
>  #define SYS_SPSR_abt			sys_reg(3, 4, 4, 3, 1)
>  #define SYS_SPSR_und			sys_reg(3, 4, 4, 3, 2)
> @@ -580,8 +575,6 @@
>  #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
>  #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
>  
> -#define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
> -#define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
>  #define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)
>  
>  #define __AMEV_op2(m)			(m & 0x7)
> @@ -623,7 +616,6 @@
>  #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
>  #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
>  
> -#define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
>  
>  /* AT instructions */
>  #define AT_Op0 1
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index e2d37ee221b84..7349744f14211 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2958,6 +2958,10 @@ Res0	4:1
>  Field	0	PCRSEL
>  EndSysreg
>  
> +Sysreg	SP_EL0	3	0	4	1	0
> +Field	63:0	SP
> +EndSysreg
> +
>  Sysreg	ALLINT	3	0	4	3	0
>  Res0	63:14
>  Field	13	ALLINT
> @@ -3811,6 +3815,15 @@ Sysreg	GCSPR_EL0	3	3	2	5	1
>  Fields	GCSPR_ELx
>  EndSysreg
>  
> +Sysreg	DAIF	3	3	4	2	1
> +Res0	63:10
> +Field	9	D
> +Field	8	A
> +Field	7	I
> +Field	6	F
> +Res0	5:0
> +EndSysreg
> +
>  Sysreg	SVCR	3	3	4	2	2
>  Res0	63:2
>  Field	1	ZA
> @@ -3885,6 +3898,22 @@ UnsignedEnum	2:0	F8S1
>  EndEnum
>  EndSysreg
>  
> +Sysreg	TPIDR_EL0	3	3	13	0	2
> +Field	63:0	ThreadID
> +EndSysreg
> +
> +Sysreg	TPIDRRO_EL0	3	3	13	0	3
> +Field	63:0	ThreadID
> +EndSysreg
> +
> +Sysreg	TPIDR2_EL0	3	3	13	0	5
> +Field	63:0	ThreadID
> +EndSysreg
> +
> +Sysreg	SP_EL1	3	4	4	1	0
> +Field	63:0	SP
> +EndSysreg
> +
>  Sysreg	SCTLR_EL2	3	4	1	0	0
>  Field	63	TIDCP
>  Field	62	SPINTMASK
> @@ -5425,6 +5454,10 @@ Sysreg	CONTEXTIDR_EL2	3	4	13	0	1
>  Fields	CONTEXTIDR_ELx
>  EndSysreg
>  
> +Sysreg	TPIDR_EL2	3	4	13	0	2
> +Field	63:0	ThreadID
> +EndSysreg
> +
>  Sysreg	CNTPOFF_EL2	3	4	14	0	6
>  Field	63:0	PhysicalOffset
>  EndSysreg
> @@ -5465,6 +5498,10 @@ Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
>  Mapping	CONTEXTIDR_EL1
>  EndSysreg
>  
> +Sysreg	SP_EL2	3	6	4	1	0
> +Field	63:0	SP
> +EndSysreg
> +
>  SysregFields TTBRx_EL1
>  Field	63:48	ASID
>  Field	47:1	BADDR
> -- 2.43.0
> 

I've cheeked replaced and removed encodings against generated sysreg-defs.h
and all look correct. New encodings matches ARM ARM.

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>

Re: [PATCH 2/4] arm64: insn: fix system register inconsistencies

[Vladimir Murzin]

On 10/16/26 17:46, Ada Couprie Diaz wrote:
> Two registers in `enum aarch64_insn_special_register` are defined
> incorrectly :
>  - SPSR_IRQ is named SPSR_I*N*Q
>  - SP_EL2's encoding is incorrect and does not correspond to ant register

Nitpick: s/ant/any ?

> 
> Fix those issues and re-order the registers by value.
> Update `enum aarch64_insn_system_register` values and order to be in line
> with `enum aarch64_insn_special_register`, so that we can make
> `aarch64_insn_gen_mrs()` use the same mask as
> `aarch64_insn_extract_system_reg()` while we're here.
> 
> This does not change the behaviour, as `aarch64_insn_encode_register()`
> always masks the lower bits and the top bit of registers are always set.
> 

I think aarch64_insn_encode_register() is not relevant here since
before the change bit[20] was set via aarch64_insn_get_mrs_value()
which returns 0xD5300000. With the change we'd do not rely on
aarch64_insn_get_mrs_value() any more.

> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> ---
>  arch/arm64/include/asm/insn.h | 12 ++++++------
>  arch/arm64/lib/insn.c         |  2 +-
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index c91a8431c961e..2e45f6e80d15f 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -119,27 +119,27 @@ enum aarch64_insn_special_register {
>  	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
>  	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
>  	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
> -	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
>  	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
> +	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,

Reorder, as promised in commit message

>  	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
>  	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
>  	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
>  	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
>  	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
>  	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
> -	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
> +	AARCH64_INSN_SPCLREG_SPSR_IRQ	= 0xE218,

Rename, as promised in commit message

>  	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
>  	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
>  	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
>  	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
>  	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
> -	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
> +	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF208,

Correct encoding, as promised in commit message

>  };
>  
>  enum aarch64_insn_system_register {
> -	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0x4684,
> -	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0x6682,
> -	AARCH64_INSN_SYSREG_SP_EL0	= 0x4208,
> +	AARCH64_INSN_SYSREG_SP_EL0	= 0xC208,
> +	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0xC684,
> +	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0xE682,

Aligns encoding (we basically account for bit[20] of mrs) with
aarch64_insn_special_register, again as promised in commit message

>  };
>  
>  enum aarch64_insn_variant {
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index 5c37f3a4c402b..94ee1aae2f5b7 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -1566,7 +1566,7 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
>  {
>  	u32 insn = aarch64_insn_get_mrs_value();
>  

insn is 0xD5300000, bit[20] is set

> -	insn &= ~GENMASK(19, 0);
> +	insn &= ~GENMASK(20, 5);

bit[20] is clear

>  	insn |= sysreg << 5;

bit[20] is set

>  	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
>  					    insn, result);
> -- 2.43.0
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>

Re: [PATCH 3/4] arm64: insn: operate on MSR/MRS sysreg field via defines

[Vladimir Murzin]

On 10/16/26 17:46, Ada Couprie Diaz wrote:
> Replace the few instances of hard-coded system register offset and masks
> used to operate on MSR/MRS instructions with defines.
> This will allow re-use in future commits while making the connection
> between those values more explicit.
> 
> While we are here, mark `aarch64_insn_extract_system_reg()` `noinstr`
> so it can be safe to use in alternative pacthing callbacks.
> 
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> ---
>  arch/arm64/include/asm/insn.h | 3 +++
>  arch/arm64/lib/insn.c         | 8 ++++----
>  2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index 2e45f6e80d15f..e020f9d8b83c2 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -113,6 +113,9 @@ enum aarch64_insn_register {
>  	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
>  };
>  
> +#define AARCH64_INSN_SYSREG_OFFSET	5
> +#define AARCH64_INSN_SYSREG_MASK	GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
> +
>  enum aarch64_insn_special_register {
>  	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
>  	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index 94ee1aae2f5b7..2edc5a9c0a9c8 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -1362,9 +1362,9 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
>  /*
>   * Extract the Op/CR data from a msr/mrs instruction.
>   */
> -u32 aarch64_insn_extract_system_reg(u32 insn)
> +noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
>  {
> -	return (insn & 0x1FFFE0) >> 5;
> +	return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
>  }
>  
>  bool aarch32_insn_is_wide(u32 insn)
> @@ -1566,8 +1566,8 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
>  {
>  	u32 insn = aarch64_insn_get_mrs_value();
>  
> -	insn &= ~GENMASK(20, 5);
> -	insn |= sysreg << 5;
> +	insn &= ~AARCH64_INSN_SYSREG_MASK;
> +	insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
>  	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
>  					    insn, result);
>  }
> -- 2.43.0
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>

Re: [PATCH 4/4] arm64: insn: clean-up sysregs handling

[Vladimir Murzin]

On 10/16/26 17:46, Ada Couprie Diaz wrote:
> System register encodings are already defined in <asm/sysreg.h>, so
> use those definitions in <asm/insn.h> instead of duplicating them.
> This will avoid future errors and deviations.
> 
> Remove the unnecessary shifts for encoding/decoding now that the enum
> values directly match the encoded registers.
> 
> No code using the insn register encodings currently makes a distinction
> between "regular" system registers and special-purpose registers,
> so let's just drop the difference and merge the two enums.
> Remove all unused registers while we are here.
> 
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> ---
>  arch/arm64/include/asm/insn.h          | 36 ++++++++------------------
>  arch/arm64/kernel/probes/decode-insn.c |  2 +-
>  arch/arm64/lib/insn.c                  |  4 +--
>  3 files changed, 14 insertions(+), 28 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index e020f9d8b83c2..6533191638804 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -12,6 +12,7 @@
>  #include <linux/types.h>
>  
>  #include <asm/insn-def.h>
> +#include <asm/sysreg.h>
>  
>  #ifndef __ASSEMBLER__
>  
> @@ -113,38 +114,23 @@ enum aarch64_insn_register {
>  	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
>  };
>  
> +/* System register encoding for MRS/MSR (register) instructions. */
>  #define AARCH64_INSN_SYSREG_OFFSET	5
>  #define AARCH64_INSN_SYSREG_MASK	GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
> +#define AARCH64_INSN_SYSREG_FROM_DEF(sysreg) \

bikeshedding: perhaps __AARCH64_INSN_SYSREG to match other helper macro in this
file?

> +	AARCH64_INSN_SYSREG_##sysreg = SYS_##sysreg
>  
> -enum aarch64_insn_special_register {
> -	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
> -	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
> -	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
> -	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
> -	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
> -	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
> -	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
> -	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
> -	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
> -	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
> -	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
> -	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
> -	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
> -	AARCH64_INSN_SPCLREG_SPSR_IRQ	= 0xE218,
> -	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
> -	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
> -	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
> -	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
> -	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
> -	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF208,
> -};
>  

The only register in use was AARCH64_INSN_SPCLREG_DAIF which is
now replaced with direct use of AARCH64_INSN_SYSREG_DAIF.

> +/* Do not duplicate encodings: we already define them in <asm/sysreg.h> */
>  enum aarch64_insn_system_register {
> -	AARCH64_INSN_SYSREG_SP_EL0	= 0xC208,
> -	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0xC684,
> -	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0xE682,
> +	AARCH64_INSN_SYSREG_FROM_DEF(SP_EL0),
> +	AARCH64_INSN_SYSREG_FROM_DEF(TPIDR_EL1),
> +	AARCH64_INSN_SYSREG_FROM_DEF(DAIF),
> +	AARCH64_INSN_SYSREG_FROM_DEF(TPIDR_EL2),
>  };
>  
> +#undef AARCH64_INSN_SYSREG_FROM_DEF
> +
>  enum aarch64_insn_variant {
>  	AARCH64_INSN_VARIANT_32BIT,
>  	AARCH64_INSN_VARIANT_64BIT
> diff --git a/arch/arm64/kernel/probes/decode-insn.c b/arch/arm64/kernel/probes/decode-insn.c
> index 4137cc5ef031f..bb0af08105885 100644
> --- a/arch/arm64/kernel/probes/decode-insn.c
> +++ b/arch/arm64/kernel/probes/decode-insn.c
> @@ -40,7 +40,7 @@ static bool __kprobes aarch64_insn_is_steppable(u32 insn)
>  		 */
>  		if (aarch64_insn_is_mrs(insn))
>  			return aarch64_insn_extract_system_reg(insn)
> -			     != AARCH64_INSN_SPCLREG_DAIF;
> +			     != AARCH64_INSN_SYSREG_DAIF;
>  
>  		/*
>  		 * The HINT instruction is steppable only if it is in whitelist
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index 2edc5a9c0a9c8..1611c86885c9f 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -1364,7 +1364,7 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
>   */
>  noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
>  {
> -	return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
> +	return insn & AARCH64_INSN_SYSREG_MASK;
>  }
>  
>  bool aarch32_insn_is_wide(u32 insn)
> @@ -1567,7 +1567,7 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
>  	u32 insn = aarch64_insn_get_mrs_value();
>  
>  	insn &= ~AARCH64_INSN_SYSREG_MASK;
> -	insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
> +	insn |= sysreg;
>  	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
>  					    insn, result);
>  }
> -- 2.43.0
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>