From: Jinjie Ruan <ruanjinjie@huawei.com>
To: Vladimir Murzin <vladimir.murzin@arm.com>,
<linux-arm-kernel@lists.infradead.org>
Cc: mark.rutland@arm.com, maz@kernel.org, will@kernel.org,
catalin.marinas@arm.com
Subject: Re: [RFC PATCH 09/36] arm64: irqflags: introduce arm64-specific irqflags type
Date: Fri, 10 Jul 2026 16:40:41 +0800 [thread overview]
Message-ID: <cb05707e-f623-4058-8c28-031b77f4454e@huawei.com> (raw)
In-Reply-To: <20260709121333.23507-10-vladimir.murzin@arm.com>
On 7/9/2026 8:13 PM, Vladimir Murzin wrote:
> From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>
> With pseudo-NMIs enabled, we have two mechanisms that control
> interrupt masking in parallel :
> - The DAIF flags, masking at the CPU
> - The GIC PMR, masking before the CPU
>
> However, our irqflags implementation currently assumes that only one
> of the two is used at a time, so both DAIF and PMR masking use the same
> `unsigned long flags` in their own way.
> This is incorrect, as some parts of the kernel will mask interrupts
> with DAIF directly or bypass the local_irq masking via the PMR,
> and makes tracking the state and changes of both in parallel impossible.
>
> The irqflags API expects `unsigned long`s to be passed around, but
> they should not be manipulated outside of the arch-specific code.
> So, we can encode the information we need however we want as long as
> we return and accept `unsigned long`s.
>
> Introduce a union type for arm64 irqflags whose first member is
> a struct allowing us to track DAIF and PMR in parallel, and the second
> is the `unsigned long` expected by the irqflags API.
>
> DAIF is a two byte value, to maintain compatibility with existing defines.
> PMR is a one byte value, which is the maximum amount of priority bits
> allowed by the GICv3 architecture.
>
> Update the internal irqflags functions to use this new union and convert
> back and forth with the irqflags unsigned long.
> There should be no functional changes.
>
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
> arch/arm64/include/asm/irqflags.h | 80 ++++++++++++++++++++-----------
> 1 file changed, 53 insertions(+), 27 deletions(-)
I believe that using the newly introduced arm64_exc_hwstate_t only at
the lowest level results in the least changes and is the most readable.
otherwise, LGTM
Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>
arch/arm64/include/asm/irqflags.h | 42
++++++++++++++++++++++++++++++++++++------
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/irqflags.h
b/arch/arm64/include/asm/irqflags.h
index a8cb5a5c93b7..4b4521007183 100644
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -9,6 +9,8 @@
#include <asm/ptrace.h>
#include <asm/sysreg.h>
+#include <linux/compiler.h>
+
/*
* Aarch64 has flags for masking: Debug, Asynchronous (serror),
Interrupts and
* FIQ exceptions, in the 'daif' register. We mask and unmask them in
'daif'
@@ -20,6 +22,22 @@
* exceptions should be unmasked.
*/
+ /*
+ * Internally, we want to independently manipulate and track the different
+ * interrupt masking mechanisms.
+ * Externally, the generic irqflags API expects unsgined longs to
represent
+ * the state of interrupts, which are treated as obscure arch-specific
data.
+ */
+typedef union arm64_exc_hwstate {
+ struct {
+ u16 daif;
+ u8 pmr;
+ };
+ unsigned long flags;
+} arm64_exc_hwstate_t;
+
+static_assert(sizeof(arm64_exc_hwstate_t) == sizeof(unsigned long));
+
static __always_inline void __daif_local_irq_enable(void)
{
barrier();
@@ -79,12 +97,16 @@ static __always_inline void arch_local_irq_disable(void)
static __always_inline unsigned long __daif_local_save_flags(void)
{
- return read_sysreg(daif);
+ arm64_exc_hwstate_t state = { .daif = read_sysreg(daif) };
+
+ return state.flags;
}
static __always_inline unsigned long __pmr_local_save_flags(void)
{
- return read_sysreg_s(SYS_ICC_PMR_EL1);
+ arm64_exc_hwstate_t state = { .pmr =
read_sysreg_s(SYS_ICC_PMR_EL1) };
+
+ return state.flags;
}
/*
@@ -101,12 +123,16 @@ static __always_inline unsigned long
arch_local_save_flags(void)
static __always_inline bool __daif_irqs_disabled_flags(unsigned long flags)
{
- return flags & PSR_I_BIT;
+ arm64_exc_hwstate_t hwstate = { .flags = flags };
+
+ return hwstate.daif & PSR_I_BIT;
}
static __always_inline bool __pmr_irqs_disabled_flags(unsigned long flags)
{
- return flags != GIC_PRIO_IRQON;
+ arm64_exc_hwstate_t hwstate = { .flags = flags };
+
+ return hwstate.pmr != GIC_PRIO_IRQON;
}
static __always_inline bool arch_irqs_disabled_flags(unsigned long flags)
@@ -171,15 +197,19 @@ static __always_inline unsigned long
arch_local_irq_save(void)
static __always_inline void __daif_local_irq_restore(unsigned long flags)
{
+ arm64_exc_hwstate_t hwstate = { .flags = flags };
+
barrier();
- write_sysreg(flags, daif);
+ write_sysreg(hwstate.daif, daif);
barrier();
}
static __always_inline void __pmr_local_irq_restore(unsigned long flags)
{
+ arm64_exc_hwstate_t hwstate = { .flags = flags };
+
barrier();
- write_sysreg_s(flags, SYS_ICC_PMR_EL1);
+ write_sysreg_s(hwstate.pmr, SYS_ICC_PMR_EL1);
pmr_sync();
barrier();
}
>
> diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h
> index a8cb5a5c93b7..7775904ba6a9 100644
> --- a/arch/arm64/include/asm/irqflags.h
> +++ b/arch/arm64/include/asm/irqflags.h
> @@ -9,6 +9,8 @@
> #include <asm/ptrace.h>
> #include <asm/sysreg.h>
>
> +#include <linux/compiler.h>
> +
> /*
> * Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
> * FIQ exceptions, in the 'daif' register. We mask and unmask them in 'daif'
> @@ -20,6 +22,22 @@
> * exceptions should be unmasked.
> */
>
> + /*
> + * Internally, we want to independently manipulate and track the different
> + * interrupt masking mechanisms.
> + * Externally, the generic irqflags API expects unsgined longs to represent
> + * the state of interrupts, which are treated as obscure arch-specific data.
> + */
> +typedef union arm64_exc_hwstate {
> + struct {
> + u16 daif;
> + u8 pmr;
> + };
> + unsigned long flags;
> +} arm64_exc_hwstate_t;
> +
> +static_assert(sizeof(arm64_exc_hwstate_t) == sizeof(unsigned long));
> +
> static __always_inline void __daif_local_irq_enable(void)
> {
> barrier();
> @@ -77,14 +95,14 @@ static __always_inline void arch_local_irq_disable(void)
> }
> }
>
> -static __always_inline unsigned long __daif_local_save_flags(void)
> +static __always_inline arm64_exc_hwstate_t __daif_local_save_flags(void)
> {
> - return read_sysreg(daif);
> + return (arm64_exc_hwstate_t){ .daif = read_sysreg(daif) };
> }
>
> -static __always_inline unsigned long __pmr_local_save_flags(void)
> +static __always_inline arm64_exc_hwstate_t __pmr_local_save_flags(void)
> {
> - return read_sysreg_s(SYS_ICC_PMR_EL1);
> + return (arm64_exc_hwstate_t){ .pmr = read_sysreg_s(SYS_ICC_PMR_EL1) };
> }
>
> /*
> @@ -93,28 +111,32 @@ static __always_inline unsigned long __pmr_local_save_flags(void)
> static __always_inline unsigned long arch_local_save_flags(void)
> {
> if (system_uses_irq_prio_masking()) {
> - return __pmr_local_save_flags();
> + return __pmr_local_save_flags().flags;
> } else {
> - return __daif_local_save_flags();
> + return __daif_local_save_flags().flags;
> }
> }
>
> -static __always_inline bool __daif_irqs_disabled_flags(unsigned long flags)
> +static __always_inline
> +bool __daif_irqs_disabled_flags(arm64_exc_hwstate_t hwstate)
> {
> - return flags & PSR_I_BIT;
> + return hwstate.daif & PSR_I_BIT;
> }
>
> -static __always_inline bool __pmr_irqs_disabled_flags(unsigned long flags)
> +static __always_inline
> +bool __pmr_irqs_disabled_flags(arm64_exc_hwstate_t hwstate)
> {
> - return flags != GIC_PRIO_IRQON;
> + return hwstate.pmr != GIC_PRIO_IRQON;
> }
>
> static __always_inline bool arch_irqs_disabled_flags(unsigned long flags)
> {
> + arm64_exc_hwstate_t hwstate = { .flags = flags };
> +
> if (system_uses_irq_prio_masking()) {
> - return __pmr_irqs_disabled_flags(flags);
> + return __pmr_irqs_disabled_flags(hwstate);
> } else {
> - return __daif_irqs_disabled_flags(flags);
> + return __daif_irqs_disabled_flags(hwstate);
> }
> }
>
> @@ -137,49 +159,51 @@ static __always_inline bool arch_irqs_disabled(void)
> }
> }
>
> -static __always_inline unsigned long __daif_local_irq_save(void)
> +static __always_inline arm64_exc_hwstate_t __daif_local_irq_save(void)
> {
> - unsigned long flags = __daif_local_save_flags();
> + arm64_exc_hwstate_t hwstate = __daif_local_save_flags();
>
> __daif_local_irq_disable();
>
> - return flags;
> + return hwstate;
> }
>
> -static __always_inline unsigned long __pmr_local_irq_save(void)
> +static __always_inline arm64_exc_hwstate_t __pmr_local_irq_save(void)
> {
> - unsigned long flags = __pmr_local_save_flags();
> + arm64_exc_hwstate_t hwstate = __pmr_local_save_flags();
>
> /*
> * There are too many states with IRQs disabled, just keep the current
> * state if interrupts are already disabled/masked.
> */
> - if (!__pmr_irqs_disabled_flags(flags))
> + if (!__pmr_irqs_disabled_flags(hwstate))
> __pmr_local_irq_disable();
>
> - return flags;
> + return hwstate;
> }
>
> static __always_inline unsigned long arch_local_irq_save(void)
> {
> if (system_uses_irq_prio_masking()) {
> - return __pmr_local_irq_save();
> + return __pmr_local_irq_save().flags;
> } else {
> - return __daif_local_irq_save();
> + return __daif_local_irq_save().flags;
> }
> }
>
> -static __always_inline void __daif_local_irq_restore(unsigned long flags)
> +static __always_inline
> +void __daif_local_irq_restore(arm64_exc_hwstate_t hwstate)
> {
> barrier();
> - write_sysreg(flags, daif);
> + write_sysreg(hwstate.daif, daif);
> barrier();
> }
>
> -static __always_inline void __pmr_local_irq_restore(unsigned long flags)
> +static __always_inline
> +void __pmr_local_irq_restore(arm64_exc_hwstate_t hwstate)
> {
> barrier();
> - write_sysreg_s(flags, SYS_ICC_PMR_EL1);
> + write_sysreg_s(hwstate.pmr, SYS_ICC_PMR_EL1);
> pmr_sync();
> barrier();
> }
> @@ -189,10 +213,12 @@ static __always_inline void __pmr_local_irq_restore(unsigned long flags)
> */
> static __always_inline void arch_local_irq_restore(unsigned long flags)
> {
> + arm64_exc_hwstate_t hwstate = { .flags = flags };
> +
> if (system_uses_irq_prio_masking()) {
> - __pmr_local_irq_restore(flags);
> + __pmr_local_irq_restore(hwstate);
> } else {
> - __daif_local_irq_restore(flags);
> + __daif_local_irq_restore(hwstate);
> }
> }
>
next prev parent reply other threads:[~2026-07-10 8:41 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 12:12 [RFC PATCH 00/36] arm64: Add support for FEAT_NMI Vladimir Murzin
2026-07-09 12:12 ` [RFC PATCH 01/36] arm64: ptrace: Remove INIT_PSTATE_EL2 Vladimir Murzin
2026-07-09 12:36 ` Jinjie Ruan
2026-07-09 12:12 ` [RFC PATCH 02/36] arm64: debug: don't mask DAIF for mdscr_write() Vladimir Murzin
2026-07-09 13:06 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 03/36] arm64: hibernate: mask DAIF before restoring hibernated kernel Vladimir Murzin
2026-07-09 13:19 ` Jinjie Ruan
2026-07-10 3:00 ` Jinjie Ruan
2026-07-10 3:28 ` Jinjie Ruan
2026-07-10 3:40 ` Liao, Chang
2026-07-09 12:13 ` [RFC PATCH 04/36] arm64: suspend: rely on daif helpers to handle PMR Vladimir Murzin
2026-07-10 3:41 ` Jinjie Ruan
2026-07-10 4:06 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 05/36] arm64: suspend: Initialize PMR on resume Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 06/36] arm64: irq: introduce a helper for GIC priority initialization Vladimir Murzin
2026-07-10 4:16 ` Jinjie Ruan
2026-07-10 7:29 ` Jinjie Ruan
2026-07-10 7:44 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 07/36] arm64: entry: mask DAIF before returning from C EL1 handlers Vladimir Murzin
2026-07-10 7:57 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 08/36] irqchip/gic-v3: make the unmasking of pseudo-NMIs explicit when handling IRQs Vladimir Murzin
2026-07-10 8:04 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 09/36] arm64: irqflags: introduce arm64-specific irqflags type Vladimir Murzin
2026-07-10 8:40 ` Jinjie Ruan [this message]
2026-07-09 12:13 ` [RFC PATCH 10/36] arm64: irqflags: save and use both DAIF and PMR Vladimir Murzin
2026-07-10 3:53 ` Liao, Chang
2026-07-10 8:11 ` Jinjie Ruan
2026-07-10 8:47 ` Jinjie Ruan
2026-07-10 9:02 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 11/36] arm64: interrupts: introduce interrupt masking helpers for entry code Vladimir Murzin
2026-07-10 9:19 ` Jinjie Ruan
2026-07-10 9:39 ` Liao, Chang
2026-07-10 9:39 ` Jinjie Ruan
2026-07-10 9:44 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 12/36] arm64: entry: replace DAIF helpers with entry helpers Vladimir Murzin
2026-07-10 9:36 ` Jinjie Ruan
2026-07-10 10:01 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 13/36] arm64: process: Use helper to check exception state Vladimir Murzin
2026-07-10 10:00 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 14/36] arm64: interrupts: introduce generic interrupt masking helpers Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 15/36] arm64: replace local_daif helpers Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 16/36] arm64: cpuidle: use new helpers to bypass interrupt priority masking Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 17/36] arm64: remove daifflags.h Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 18/36] arm64: gicv3: remove GIC_PRIO_PSR_I_SET Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 19/36] arm64: cpufeature: Remove system_has_prio_mask_debugging() Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 20/36] arm64: irqflags: Switch to CONFIG_DEBUG_IRQFLAGS Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 21/36] arm64: Kconfig: Remove CONFIG_ARM64_DEBUG_PRIORITY_MASKING Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 22/36] efi/runtime-wrappers: Permit architectures to override IRQ flags checks Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 23/36] arm64/efi: Implement override for " Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 24/36] arm64: booting: Document boot requirements for FEAT_NMI Vladimir Murzin
2026-07-10 2:39 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 25/36] arm64: sysreg: Add definitions for immediate versions of MSR ALLINT Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 26/36] arm64: ptrace: Add PSR_ALLINT_BIT Vladimir Murzin
2026-07-10 2:16 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 27/36] arm64: idreg: Add an override for FEAT_NMI Vladimir Murzin
2026-07-10 2:17 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 28/36] arm64: cpufeature: Detect PE support " Vladimir Murzin
2026-07-10 2:25 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 29/36] arm64: nmi: Manage masking for superpriority interrupts Vladimir Murzin
2026-07-10 10:04 ` Jinjie Ruan
2026-07-10 10:08 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 30/36] arm64: irq: Report FEAT_NMI masking local IRQs Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 31/36] arm64: nmi: Add handling of superpriority interrupts as NMIs Vladimir Murzin
2026-07-10 10:13 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 32/36] arm64: suspend: Always initialise PSTATE.ALLINT Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 33/36] arm64/efi: Add ALLINT to IRQ flags checks Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 34/36] arm64: kprobes: Disable NMIs Vladimir Murzin
2026-07-09 12:13 ` [RFC PATCH 35/36] arm64: nmi: Add Kconfig for NMI Vladimir Murzin
2026-07-10 2:41 ` Jinjie Ruan
2026-07-09 12:13 ` [RFC PATCH 36/36] irqchip/gic-v3: Implement FEAT_GICv3_NMI support Vladimir Murzin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cb05707e-f623-4058-8c28-031b77f4454e@huawei.com \
--to=ruanjinjie@huawei.com \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=vladimir.murzin@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox