* [PATCH 1/4] ARM: runtime patching of __virt_to_phys() and __phys_to_virt()
From: Russell King - ARM Linux @ 2011-01-04 16:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1101040926100.22191@xanadu.home>
On Tue, Jan 04, 2011 at 09:32:41AM -0500, Nicolas Pitre wrote:
> On Tue, 4 Jan 2011, Russell King - ARM Linux wrote:
> > This is basically my patch with a few blank lines removed, a couple
> > of \n's also removed, a #error if __virt_to_phys is defined by a platform,
> > a minor tweak to the assembly and it being only usable on PXA.
> >
> > I much prefer my patch over this as anyone can use it. That's one of
> > the reasons why I arranged the code testing for __virt_to_phys as I
> > did, so the config option could be offered without having a big long
> > dependency list attached to it.
>
> I don't think offering the option that people can turn on and not having
> the code effectively perform as expected is a good idea. People might
> be expecting the feature to be there while in practice it is ignored
> which would lead to confusion.
Our aims are different then. My aim is to move the code to a point where
it works for _everyone_ it possibly can - and theoretically that's every
platform except:
1. MSM due to their PHYS_OFFSET being 2MB aligned, rather than the more
normal 256MB alignment.
2. Anyone with complex V:P mappings
(1) is dealt with easily by a dependency in the configuration preventing
the option being visible. (2) is dealt with at runtime by ignoring the
configuration option - resulting in the p2v tables being empty. The end
result will still run on the platform, but it won't do the relocation
stuff. (2) could also be dealt with by adding the necessary dependencies
to the configuration option which is the longer term solution.
Lastly, marking the option as 'EXPERIMENTAL' is there to convey that it
may not work for everyone, and people should expect things not to work if
they enable such an option (and report when that's the case.)
Another reason why selecting this option is wrong is that it is incompatible
with XIP. If you're going to unconditionally enable it for platforms like
PXA, make sure you strip out all of PXA's XIP support before you do so,
otherwise you'll build a kernel which has absolutely no way of ever booting.
> As to the authorship, since I drafted the original design, Eric Miao did
> the first implementation to validate the concept, and the code surviving
> is mostly yours, I didn't know who to singularly attribute the patch to
> in the author field. I can put yourself there if you feel this is more
> appropriate.
The correct thing to do is to ensure that it has Eric's and my sign-offs.
If you compare Eric's to my version, mine has a fair amount of changes.
^ permalink raw reply
* [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
From: Sergei Shtylyov @ 2011-01-04 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294149984.1822.9.camel@eowin>
Hello.
Felipe Balbi wrote:
>>>> I think we will get more clarity once we start on this activity.
>>> I agree, but I personally don't see that many limiting factors.
>>> dmaengine is just a generic API for doing DMA transfers. If it's not
>>> enough for us currently, we extend it.
>> Putting MUSB DMA enignes into drivers/dma/ is the same as taking *any*
>> chip capable of bus-mastering DMA, "separating" its bus mastering related code
>> from its driver and putting this code into drivers/dma/. This doesn't make
>> sense, in my opinion. drivers/dma/ is for the dedicated DMA controllers (which
>> can *optionally* serve the slave devices).
> Do I really have to spell it out ? Really ?
Yes, I'm dense. :-)
Especially after Ajay claiming that Mentor and CPPI 3.0 DMA will be moved to
drivers/dma/...
> You don't need to physically move the part of the code to drivers/dma,
> but it has to use the API. The mentor DMA is internal to MUSB.
> tusb6010_omap.c isn't.
Yes, that's what I've already noted in this thread.
> Where it makes sense to move the code under drivers/dma, it will be
Surely OMAP DMA needs to be moved under drivers/dma/, not the TUSB code
interfacing it.
> done, where it doesn't, it won't be done, but it will use the same API.
> That's all.
I don't quite see how DMA engine API is beneficial to what we currently have...
> The end goal is just to drop all these ad-hoc "APIs" for accessing DMA
> on musb code.
The "ad-hoc" API is well suited for use with MUSB, while DMA engine API is
more abstract, I think. The "ad-hoc" API takes into account some things that the
DMA engine API just can't -- like the transfer mode and packet size...
WBR, Sergei
^ permalink raw reply
* [PATCH] arm/mach-stmp3xxx: remove headers for DUART
From: Wolfram Sang @ 2011-01-04 16:36 UTC (permalink / raw)
To: linux-arm-kernel
The DUART is an AMBA PL011 and its registers are already available in
linux/amba/serial.h. Support for the DUART can be obtained via the
existing pl011 driver.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: dmitry pervushin <dpervushin@embeddedalley.com>
---
Originally, these registers were used in a driver posted here:
http://www.spinics.net/lists/arm-kernel/msg65548.html
It was luckily never merged, because now we know that amba-pl011 should be
used. This duplicate was found because the situation for MXS (MX23/MX28) is the
same and meanwhile pl011 is basically working there.
arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h | 268 --------------------
arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h | 268 --------------------
2 files changed, 0 insertions(+), 536 deletions(-)
delete mode 100644 arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
delete mode 100644 arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * stmp378x: UARTDBG register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
-#define REGS_UARTDBG_PHYS 0x80070000
-#define REGS_UARTDBG_SIZE 0x2000
-
-#define HW_UARTDBGDR 0x00000000
-#define BP_UARTDBGDR_UNAVAILABLE 16
-#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
-#define BP_UARTDBGDR_RESERVED 12
-#define BM_UARTDBGDR_RESERVED 0x0000F000
-#define BF_UARTDBGDR_RESERVED(v) \
- (((v) << 12) & BM_UARTDBGDR_RESERVED)
-#define BM_UARTDBGDR_OE 0x00000800
-#define BM_UARTDBGDR_BE 0x00000400
-#define BM_UARTDBGDR_PE 0x00000200
-#define BM_UARTDBGDR_FE 0x00000100
-#define BP_UARTDBGDR_DATA 0
-#define BM_UARTDBGDR_DATA 0x000000FF
-#define BF_UARTDBGDR_DATA(v) \
- (((v) << 0) & BM_UARTDBGDR_DATA)
-#define HW_UARTDBGRSR_ECR 0x00000004
-#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
-#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
-#define BP_UARTDBGRSR_ECR_EC 4
-#define BM_UARTDBGRSR_ECR_EC 0x000000F0
-#define BF_UARTDBGRSR_ECR_EC(v) \
- (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
-#define BM_UARTDBGRSR_ECR_OE 0x00000008
-#define BM_UARTDBGRSR_ECR_BE 0x00000004
-#define BM_UARTDBGRSR_ECR_PE 0x00000002
-#define BM_UARTDBGRSR_ECR_FE 0x00000001
-#define HW_UARTDBGFR 0x00000018
-#define BP_UARTDBGFR_UNAVAILABLE 16
-#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGFR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
-#define BP_UARTDBGFR_RESERVED 9
-#define BM_UARTDBGFR_RESERVED 0x0000FE00
-#define BF_UARTDBGFR_RESERVED(v) \
- (((v) << 9) & BM_UARTDBGFR_RESERVED)
-#define BM_UARTDBGFR_RI 0x00000100
-#define BM_UARTDBGFR_TXFE 0x00000080
-#define BM_UARTDBGFR_RXFF 0x00000040
-#define BM_UARTDBGFR_TXFF 0x00000020
-#define BM_UARTDBGFR_RXFE 0x00000010
-#define BM_UARTDBGFR_BUSY 0x00000008
-#define BM_UARTDBGFR_DCD 0x00000004
-#define BM_UARTDBGFR_DSR 0x00000002
-#define BM_UARTDBGFR_CTS 0x00000001
-#define HW_UARTDBGILPR 0x00000020
-#define BP_UARTDBGILPR_UNAVAILABLE 8
-#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGILPR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
-#define BP_UARTDBGILPR_ILPDVSR 0
-#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
-#define BF_UARTDBGILPR_ILPDVSR(v) \
- (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
-#define HW_UARTDBGIBRD 0x00000024
-#define BP_UARTDBGIBRD_UNAVAILABLE 16
-#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
-#define BP_UARTDBGIBRD_BAUD_DIVINT 0
-#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
-#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
- (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
-#define HW_UARTDBGFBRD 0x00000028
-#define BP_UARTDBGFBRD_UNAVAILABLE 8
-#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
-#define BP_UARTDBGFBRD_RESERVED 6
-#define BM_UARTDBGFBRD_RESERVED 0x000000C0
-#define BF_UARTDBGFBRD_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
-#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
-#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
-#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
- (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
-#define HW_UARTDBGLCR_H 0x0000002c
-#define BP_UARTDBGLCR_H_UNAVAILABLE 16
-#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
-#define BP_UARTDBGLCR_H_RESERVED 8
-#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
-#define BF_UARTDBGLCR_H_RESERVED(v) \
- (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
-#define BM_UARTDBGLCR_H_SPS 0x00000080
-#define BP_UARTDBGLCR_H_WLEN 5
-#define BM_UARTDBGLCR_H_WLEN 0x00000060
-#define BF_UARTDBGLCR_H_WLEN(v) \
- (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
-#define BM_UARTDBGLCR_H_FEN 0x00000010
-#define BM_UARTDBGLCR_H_STP2 0x00000008
-#define BM_UARTDBGLCR_H_EPS 0x00000004
-#define BM_UARTDBGLCR_H_PEN 0x00000002
-#define BM_UARTDBGLCR_H_BRK 0x00000001
-#define HW_UARTDBGCR 0x00000030
-#define BP_UARTDBGCR_UNAVAILABLE 16
-#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGCR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
-#define BM_UARTDBGCR_CTSEN 0x00008000
-#define BM_UARTDBGCR_RTSEN 0x00004000
-#define BM_UARTDBGCR_OUT2 0x00002000
-#define BM_UARTDBGCR_OUT1 0x00001000
-#define BM_UARTDBGCR_RTS 0x00000800
-#define BM_UARTDBGCR_DTR 0x00000400
-#define BM_UARTDBGCR_RXE 0x00000200
-#define BM_UARTDBGCR_TXE 0x00000100
-#define BM_UARTDBGCR_LBE 0x00000080
-#define BP_UARTDBGCR_RESERVED 3
-#define BM_UARTDBGCR_RESERVED 0x00000078
-#define BF_UARTDBGCR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGCR_RESERVED)
-#define BM_UARTDBGCR_SIRLP 0x00000004
-#define BM_UARTDBGCR_SIREN 0x00000002
-#define BM_UARTDBGCR_UARTEN 0x00000001
-#define HW_UARTDBGIFLS 0x00000034
-#define BP_UARTDBGIFLS_UNAVAILABLE 16
-#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
-#define BP_UARTDBGIFLS_RESERVED 6
-#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
-#define BF_UARTDBGIFLS_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
-#define BP_UARTDBGIFLS_RXIFLSEL 3
-#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
-#define BF_UARTDBGIFLS_RXIFLSEL(v) \
- (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
-#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
-#define BP_UARTDBGIFLS_TXIFLSEL 0
-#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
-#define BF_UARTDBGIFLS_TXIFLSEL(v) \
- (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
-#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
-#define HW_UARTDBGIMSC 0x00000038
-#define BP_UARTDBGIMSC_UNAVAILABLE 16
-#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
-#define BP_UARTDBGIMSC_RESERVED 11
-#define BM_UARTDBGIMSC_RESERVED 0x0000F800
-#define BF_UARTDBGIMSC_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
-#define BM_UARTDBGIMSC_OEIM 0x00000400
-#define BM_UARTDBGIMSC_BEIM 0x00000200
-#define BM_UARTDBGIMSC_PEIM 0x00000100
-#define BM_UARTDBGIMSC_FEIM 0x00000080
-#define BM_UARTDBGIMSC_RTIM 0x00000040
-#define BM_UARTDBGIMSC_TXIM 0x00000020
-#define BM_UARTDBGIMSC_RXIM 0x00000010
-#define BM_UARTDBGIMSC_DSRMIM 0x00000008
-#define BM_UARTDBGIMSC_DCDMIM 0x00000004
-#define BM_UARTDBGIMSC_CTSMIM 0x00000002
-#define BM_UARTDBGIMSC_RIMIM 0x00000001
-#define HW_UARTDBGRIS 0x0000003c
-#define BP_UARTDBGRIS_UNAVAILABLE 16
-#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGRIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
-#define BP_UARTDBGRIS_RESERVED 11
-#define BM_UARTDBGRIS_RESERVED 0x0000F800
-#define BF_UARTDBGRIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGRIS_RESERVED)
-#define BM_UARTDBGRIS_OERIS 0x00000400
-#define BM_UARTDBGRIS_BERIS 0x00000200
-#define BM_UARTDBGRIS_PERIS 0x00000100
-#define BM_UARTDBGRIS_FERIS 0x00000080
-#define BM_UARTDBGRIS_RTRIS 0x00000040
-#define BM_UARTDBGRIS_TXRIS 0x00000020
-#define BM_UARTDBGRIS_RXRIS 0x00000010
-#define BM_UARTDBGRIS_DSRRMIS 0x00000008
-#define BM_UARTDBGRIS_DCDRMIS 0x00000004
-#define BM_UARTDBGRIS_CTSRMIS 0x00000002
-#define BM_UARTDBGRIS_RIRMIS 0x00000001
-#define HW_UARTDBGMIS 0x00000040
-#define BP_UARTDBGMIS_UNAVAILABLE 16
-#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGMIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
-#define BP_UARTDBGMIS_RESERVED 11
-#define BM_UARTDBGMIS_RESERVED 0x0000F800
-#define BF_UARTDBGMIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGMIS_RESERVED)
-#define BM_UARTDBGMIS_OEMIS 0x00000400
-#define BM_UARTDBGMIS_BEMIS 0x00000200
-#define BM_UARTDBGMIS_PEMIS 0x00000100
-#define BM_UARTDBGMIS_FEMIS 0x00000080
-#define BM_UARTDBGMIS_RTMIS 0x00000040
-#define BM_UARTDBGMIS_TXMIS 0x00000020
-#define BM_UARTDBGMIS_RXMIS 0x00000010
-#define BM_UARTDBGMIS_DSRMMIS 0x00000008
-#define BM_UARTDBGMIS_DCDMMIS 0x00000004
-#define BM_UARTDBGMIS_CTSMMIS 0x00000002
-#define BM_UARTDBGMIS_RIMMIS 0x00000001
-#define HW_UARTDBGICR 0x00000044
-#define BP_UARTDBGICR_UNAVAILABLE 16
-#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGICR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
-#define BP_UARTDBGICR_RESERVED 11
-#define BM_UARTDBGICR_RESERVED 0x0000F800
-#define BF_UARTDBGICR_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGICR_RESERVED)
-#define BM_UARTDBGICR_OEIC 0x00000400
-#define BM_UARTDBGICR_BEIC 0x00000200
-#define BM_UARTDBGICR_PEIC 0x00000100
-#define BM_UARTDBGICR_FEIC 0x00000080
-#define BM_UARTDBGICR_RTIC 0x00000040
-#define BM_UARTDBGICR_TXIC 0x00000020
-#define BM_UARTDBGICR_RXIC 0x00000010
-#define BM_UARTDBGICR_DSRMIC 0x00000008
-#define BM_UARTDBGICR_DCDMIC 0x00000004
-#define BM_UARTDBGICR_CTSMIC 0x00000002
-#define BM_UARTDBGICR_RIMIC 0x00000001
-#define HW_UARTDBGDMACR 0x00000048
-#define BP_UARTDBGDMACR_UNAVAILABLE 16
-#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
-#define BP_UARTDBGDMACR_RESERVED 3
-#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
-#define BF_UARTDBGDMACR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
-#define BM_UARTDBGDMACR_DMAONERR 0x00000004
-#define BM_UARTDBGDMACR_TXDMAE 0x00000002
-#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * stmp378x: UARTDBG register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
-#define REGS_UARTDBG_PHYS 0x80070000
-#define REGS_UARTDBG_SIZE 0x2000
-
-#define HW_UARTDBGDR 0x00000000
-#define BP_UARTDBGDR_UNAVAILABLE 16
-#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
-#define BP_UARTDBGDR_RESERVED 12
-#define BM_UARTDBGDR_RESERVED 0x0000F000
-#define BF_UARTDBGDR_RESERVED(v) \
- (((v) << 12) & BM_UARTDBGDR_RESERVED)
-#define BM_UARTDBGDR_OE 0x00000800
-#define BM_UARTDBGDR_BE 0x00000400
-#define BM_UARTDBGDR_PE 0x00000200
-#define BM_UARTDBGDR_FE 0x00000100
-#define BP_UARTDBGDR_DATA 0
-#define BM_UARTDBGDR_DATA 0x000000FF
-#define BF_UARTDBGDR_DATA(v) \
- (((v) << 0) & BM_UARTDBGDR_DATA)
-#define HW_UARTDBGRSR_ECR 0x00000004
-#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
-#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
-#define BP_UARTDBGRSR_ECR_EC 4
-#define BM_UARTDBGRSR_ECR_EC 0x000000F0
-#define BF_UARTDBGRSR_ECR_EC(v) \
- (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
-#define BM_UARTDBGRSR_ECR_OE 0x00000008
-#define BM_UARTDBGRSR_ECR_BE 0x00000004
-#define BM_UARTDBGRSR_ECR_PE 0x00000002
-#define BM_UARTDBGRSR_ECR_FE 0x00000001
-#define HW_UARTDBGFR 0x00000018
-#define BP_UARTDBGFR_UNAVAILABLE 16
-#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGFR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
-#define BP_UARTDBGFR_RESERVED 9
-#define BM_UARTDBGFR_RESERVED 0x0000FE00
-#define BF_UARTDBGFR_RESERVED(v) \
- (((v) << 9) & BM_UARTDBGFR_RESERVED)
-#define BM_UARTDBGFR_RI 0x00000100
-#define BM_UARTDBGFR_TXFE 0x00000080
-#define BM_UARTDBGFR_RXFF 0x00000040
-#define BM_UARTDBGFR_TXFF 0x00000020
-#define BM_UARTDBGFR_RXFE 0x00000010
-#define BM_UARTDBGFR_BUSY 0x00000008
-#define BM_UARTDBGFR_DCD 0x00000004
-#define BM_UARTDBGFR_DSR 0x00000002
-#define BM_UARTDBGFR_CTS 0x00000001
-#define HW_UARTDBGILPR 0x00000020
-#define BP_UARTDBGILPR_UNAVAILABLE 8
-#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGILPR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
-#define BP_UARTDBGILPR_ILPDVSR 0
-#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
-#define BF_UARTDBGILPR_ILPDVSR(v) \
- (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
-#define HW_UARTDBGIBRD 0x00000024
-#define BP_UARTDBGIBRD_UNAVAILABLE 16
-#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
-#define BP_UARTDBGIBRD_BAUD_DIVINT 0
-#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
-#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
- (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
-#define HW_UARTDBGFBRD 0x00000028
-#define BP_UARTDBGFBRD_UNAVAILABLE 8
-#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
-#define BP_UARTDBGFBRD_RESERVED 6
-#define BM_UARTDBGFBRD_RESERVED 0x000000C0
-#define BF_UARTDBGFBRD_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
-#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
-#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
-#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
- (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
-#define HW_UARTDBGLCR_H 0x0000002c
-#define BP_UARTDBGLCR_H_UNAVAILABLE 16
-#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
-#define BP_UARTDBGLCR_H_RESERVED 8
-#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
-#define BF_UARTDBGLCR_H_RESERVED(v) \
- (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
-#define BM_UARTDBGLCR_H_SPS 0x00000080
-#define BP_UARTDBGLCR_H_WLEN 5
-#define BM_UARTDBGLCR_H_WLEN 0x00000060
-#define BF_UARTDBGLCR_H_WLEN(v) \
- (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
-#define BM_UARTDBGLCR_H_FEN 0x00000010
-#define BM_UARTDBGLCR_H_STP2 0x00000008
-#define BM_UARTDBGLCR_H_EPS 0x00000004
-#define BM_UARTDBGLCR_H_PEN 0x00000002
-#define BM_UARTDBGLCR_H_BRK 0x00000001
-#define HW_UARTDBGCR 0x00000030
-#define BP_UARTDBGCR_UNAVAILABLE 16
-#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGCR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
-#define BM_UARTDBGCR_CTSEN 0x00008000
-#define BM_UARTDBGCR_RTSEN 0x00004000
-#define BM_UARTDBGCR_OUT2 0x00002000
-#define BM_UARTDBGCR_OUT1 0x00001000
-#define BM_UARTDBGCR_RTS 0x00000800
-#define BM_UARTDBGCR_DTR 0x00000400
-#define BM_UARTDBGCR_RXE 0x00000200
-#define BM_UARTDBGCR_TXE 0x00000100
-#define BM_UARTDBGCR_LBE 0x00000080
-#define BP_UARTDBGCR_RESERVED 3
-#define BM_UARTDBGCR_RESERVED 0x00000078
-#define BF_UARTDBGCR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGCR_RESERVED)
-#define BM_UARTDBGCR_SIRLP 0x00000004
-#define BM_UARTDBGCR_SIREN 0x00000002
-#define BM_UARTDBGCR_UARTEN 0x00000001
-#define HW_UARTDBGIFLS 0x00000034
-#define BP_UARTDBGIFLS_UNAVAILABLE 16
-#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
-#define BP_UARTDBGIFLS_RESERVED 6
-#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
-#define BF_UARTDBGIFLS_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
-#define BP_UARTDBGIFLS_RXIFLSEL 3
-#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
-#define BF_UARTDBGIFLS_RXIFLSEL(v) \
- (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
-#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
-#define BP_UARTDBGIFLS_TXIFLSEL 0
-#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
-#define BF_UARTDBGIFLS_TXIFLSEL(v) \
- (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
-#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
-#define HW_UARTDBGIMSC 0x00000038
-#define BP_UARTDBGIMSC_UNAVAILABLE 16
-#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
-#define BP_UARTDBGIMSC_RESERVED 11
-#define BM_UARTDBGIMSC_RESERVED 0x0000F800
-#define BF_UARTDBGIMSC_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
-#define BM_UARTDBGIMSC_OEIM 0x00000400
-#define BM_UARTDBGIMSC_BEIM 0x00000200
-#define BM_UARTDBGIMSC_PEIM 0x00000100
-#define BM_UARTDBGIMSC_FEIM 0x00000080
-#define BM_UARTDBGIMSC_RTIM 0x00000040
-#define BM_UARTDBGIMSC_TXIM 0x00000020
-#define BM_UARTDBGIMSC_RXIM 0x00000010
-#define BM_UARTDBGIMSC_DSRMIM 0x00000008
-#define BM_UARTDBGIMSC_DCDMIM 0x00000004
-#define BM_UARTDBGIMSC_CTSMIM 0x00000002
-#define BM_UARTDBGIMSC_RIMIM 0x00000001
-#define HW_UARTDBGRIS 0x0000003c
-#define BP_UARTDBGRIS_UNAVAILABLE 16
-#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGRIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
-#define BP_UARTDBGRIS_RESERVED 11
-#define BM_UARTDBGRIS_RESERVED 0x0000F800
-#define BF_UARTDBGRIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGRIS_RESERVED)
-#define BM_UARTDBGRIS_OERIS 0x00000400
-#define BM_UARTDBGRIS_BERIS 0x00000200
-#define BM_UARTDBGRIS_PERIS 0x00000100
-#define BM_UARTDBGRIS_FERIS 0x00000080
-#define BM_UARTDBGRIS_RTRIS 0x00000040
-#define BM_UARTDBGRIS_TXRIS 0x00000020
-#define BM_UARTDBGRIS_RXRIS 0x00000010
-#define BM_UARTDBGRIS_DSRRMIS 0x00000008
-#define BM_UARTDBGRIS_DCDRMIS 0x00000004
-#define BM_UARTDBGRIS_CTSRMIS 0x00000002
-#define BM_UARTDBGRIS_RIRMIS 0x00000001
-#define HW_UARTDBGMIS 0x00000040
-#define BP_UARTDBGMIS_UNAVAILABLE 16
-#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGMIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
-#define BP_UARTDBGMIS_RESERVED 11
-#define BM_UARTDBGMIS_RESERVED 0x0000F800
-#define BF_UARTDBGMIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGMIS_RESERVED)
-#define BM_UARTDBGMIS_OEMIS 0x00000400
-#define BM_UARTDBGMIS_BEMIS 0x00000200
-#define BM_UARTDBGMIS_PEMIS 0x00000100
-#define BM_UARTDBGMIS_FEMIS 0x00000080
-#define BM_UARTDBGMIS_RTMIS 0x00000040
-#define BM_UARTDBGMIS_TXMIS 0x00000020
-#define BM_UARTDBGMIS_RXMIS 0x00000010
-#define BM_UARTDBGMIS_DSRMMIS 0x00000008
-#define BM_UARTDBGMIS_DCDMMIS 0x00000004
-#define BM_UARTDBGMIS_CTSMMIS 0x00000002
-#define BM_UARTDBGMIS_RIMMIS 0x00000001
-#define HW_UARTDBGICR 0x00000044
-#define BP_UARTDBGICR_UNAVAILABLE 16
-#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGICR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
-#define BP_UARTDBGICR_RESERVED 11
-#define BM_UARTDBGICR_RESERVED 0x0000F800
-#define BF_UARTDBGICR_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGICR_RESERVED)
-#define BM_UARTDBGICR_OEIC 0x00000400
-#define BM_UARTDBGICR_BEIC 0x00000200
-#define BM_UARTDBGICR_PEIC 0x00000100
-#define BM_UARTDBGICR_FEIC 0x00000080
-#define BM_UARTDBGICR_RTIC 0x00000040
-#define BM_UARTDBGICR_TXIC 0x00000020
-#define BM_UARTDBGICR_RXIC 0x00000010
-#define BM_UARTDBGICR_DSRMIC 0x00000008
-#define BM_UARTDBGICR_DCDMIC 0x00000004
-#define BM_UARTDBGICR_CTSMIC 0x00000002
-#define BM_UARTDBGICR_RIMIC 0x00000001
-#define HW_UARTDBGDMACR 0x00000048
-#define BP_UARTDBGDMACR_UNAVAILABLE 16
-#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
-#define BP_UARTDBGDMACR_RESERVED 3
-#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
-#define BF_UARTDBGDMACR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
-#define BM_UARTDBGDMACR_DMAONERR 0x00000004
-#define BM_UARTDBGDMACR_TXDMAE 0x00000002
-#define BM_UARTDBGDMACR_RXDMAE 0x00000001
--
1.7.2.3
^ permalink raw reply related
* [PATCHv8 00/12] Contiguous Memory Allocator
From: Johan MOSSBERG @ 2011-01-04 16:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20101223100642.GD3636@n2100.arm.linux.org.uk>
Russell King wrote:
> Has anyone addressed my issue with it that this is wide-open for
> abuse by allocating large chunks of memory, and then remapping
> them in some way with different attributes, thereby violating the
> ARM architecture specification?
I seem to have missed the previous discussion about this issue.
Where in the specification (preferably ARMv7) can I find
information about this? Is the problem that it is simply
forbidden to map an address multiple times with different cache
setting and if this is done the hardware might start failing? Or
is the problem that having an address mapped cached means that
speculative pre-fetch can read it into the cache at any time,
possibly causing problems if an un-cached mapping exists? In my
opinion option number two can be handled and I've made an attempt
at doing that in hwmem (posted on linux-mm a while ago), look in
cache_handler.c. Hwmem currently does not use cma but the next
version probably will.
/Johan Mossberg
^ permalink raw reply
* [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
From: Ming Lei @ 2011-01-04 15:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294152988.1822.12.camel@eowin>
Hi,
2011/1/4 Felipe Balbi <me@felipebalbi.com>:
> Hi,
>
> On Tue, 2011-01-04 at 22:40 +0800, Ming Lei wrote:
>> > The end goal is just to drop all these ad-hoc "APIs" for accessing DMA
>> > on musb code.
>>
>> If this kind of DMA controllers are only used by MUSB, seems not
>> necessary to convert to dmaengine API. ?Any benefit we can get
>> from the convert? ? MUSB is cross-platform already after all.
>
> <irony>
> correct, OMAP GPIO controller is only used on OMAPs, so why do we even
> bother having gpiolib, right ?
OMAP GPIOs have many usages or use cases, so we can use gpiolib
to simplify access to GPIOs. If GPIOs has only one usage or use case,
it is not necessary to access GPIOs by gpiolib.
Now this kind of DMA controllers are only used by MUSB or only for
MUSB, so it doesn't matter to access them by dmaengine or not.
thanks,
--
Lei Ming
^ permalink raw reply
* [PATCH 2/5 v3] omap2plus: prm: Trvial build break fix for
From: Santosh Shilimkar @ 2011-01-04 15:10 UTC (permalink / raw)
To: linux-arm-kernel
undefined reference to 'omap2_prm_read_mod_reg'
omap2plus_defocnfig build breaks when customised with only ARCH_OMAP4
selected. This is because common files make references to the functions
which are defined only for omap2xxx and omap3xxx.
LD .tmp_vmlinux1
arch/arm/mach-omap2/built-in.o: In function `pm_dbg_regset_store':
arch/arm/mach-omap2/pm-debug.c:335: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap2_pm_dump':
arch/arm/mach-omap2/pm-debug.c:121: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:123: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:124: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/pm-debug.c:125: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap_prcm_arch_reset':
arch/arm/mach-omap2/prcm.c:106: undefined reference to
`omap2_prm_set_mod_reg_bits'
arch/arm/mach-omap2/prcm.c:108: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `omap_prcm_get_reset_sources':
arch/arm/mach-omap2/prcm.c:53: undefined reference to
`omap2_prm_read_mod_reg'
arch/arm/mach-omap2/built-in.o: In function `clkdm_clear_all_wkdeps':
arch/arm/mach-omap2/clockdomain.c:545: undefined reference to
`omap2_prm_clear_mod_reg_bits'
arch/arm/mach-omap2/built-in.o: In function `clkdm_del_wkdep':
arch/arm/mach-omap2/clockdomain.c:475: undefined reference to
`omap2_prm_clear_mod_reg_bits'
arch/arm/mach-omap2/built-in.o: In function `clkdm_read_wkdep':
arch/arm/mach-omap2/clockdomain.c:511: undefined reference to
`omap2_prm_read_mod_bits_shift'
arch/arm/mach-omap2/built-in.o: In function `clkdm_add_wkdep':
arch/arm/mach-omap2/clockdomain.c:440: undefined reference to
`omap2_prm_set_mod_reg_bits'
make: *** [.tmp_vmlinux1] Error 1
This patch adds stubs for these functions so that build continues to work.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
---
arch/arm/mach-omap2/prm2xxx_3xxx.h | 63
+++++++++++++++++++++++++++++++++++-
1 files changed, 62 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h
b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 53d44f6..49654c8 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -228,7 +228,67 @@
#ifndef __ASSEMBLER__
-
+/*
+ * Stub omap2xxx/omap3xxx functions so that common files
+ * continue to build when custom builds are used
+ */
+#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
+ defined(CONFIG_ARCH_OMAP3))
+static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+}
+static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
+ s16 module, s16 idx)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16
idx)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16
idx)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32
mask)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
+{
+ WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+ "not suppose to be used on omap4\n");
+ return 0;
+}
+#else
/* Power/reset management domain register get/set */
extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
@@ -242,6 +302,7 @@ extern int omap2_prm_is_hardreset_asserted(s16
prm_mod, u8 shift);
extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
+#endif /* CONFIG_ARCH_OMAP4 */
#endif
/*
--
1.6.0.4
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--001636c598db7c3e2704993fb7a1--
^ permalink raw reply related
* [PATCH/RFC 3/3] ARM: S5PV210: Add a platform helper for MIPI DSIM/CSIS setup
From: Sylwester Nawrocki @ 2011-01-04 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294153764-25006-1-git-send-email-s.nawrocki@samsung.com>
This platform callback allows the MIPI DSIM and CSIS drivers
to control their corresponding PHYs without conflicts.
This patch also enables the MIPI setup code on Aquila board.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/mach-s5pv210/Kconfig | 6 +++
arch/arm/mach-s5pv210/Makefile | 1 +
arch/arm/mach-s5pv210/include/mach/regs-clock.h | 4 ++
arch/arm/mach-s5pv210/setup-mipi.c | 52 +++++++++++++++++++++++
4 files changed, 63 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5pv210/setup-mipi.c
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 53aabef..b93ea37 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -37,6 +37,11 @@ config S5PV210_SETUP_FB_24BPP
help
Common setup code for S5PV210 with an 24bpp RGB display helper.
+config S5PV210_SETUP_MIPI
+ bool
+ help
+ Common setup code for S5PV210 MIPI DSIM/CSIS configuration.
+
config S5PV210_SETUP_KEYPAD
bool
help
@@ -62,6 +67,7 @@ config MACH_AQUILA
select S5P_DEV_FIMC0
select S5P_DEV_FIMC1
select S5P_DEV_FIMC2
+ select S5PV210_SETUP_MIPI
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index ff1a0db..fd01315 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,6 +31,7 @@ obj-y += dev-audio.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
+obj-$(CONFIG_S5PV210_SETUP_MIPI) += setup-mipi.o
obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 4c45b74..89b88eb 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -162,6 +162,10 @@
#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814)
+#define S5P_MIPI_DPHY_ENABLE (1 << 0)
+#define S5P_MIPI_DPHY_SRESETN (1 << 1)
+#define S5P_MIPI_DPHY_MRESETN (1 << 2)
+
#define S5P_IDLE_CFG_TL_MASK (3 << 30)
#define S5P_IDLE_CFG_TM_MASK (3 << 28)
diff --git a/arch/arm/mach-s5pv210/setup-mipi.c b/arch/arm/mach-s5pv210/setup-mipi.c
new file mode 100644
index 0000000..f644e8c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-mipi.c
@@ -0,0 +1,52 @@
+/* linux/arch/arm/mach-s5pv210/setup-mipi.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd
+ *
+ * S5PV210 - Helper functions for MIPI CSIS/DSIM PHY control
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <mach/regs-clock.h>
+
+/* Global MIPI CSIS or DSIM PHY enable and reset control. */
+int s5p_mipi_phy_control(struct platform_device *pdev, bool on, u32 rst)
+{
+ static DEFINE_SPINLOCK(lock);
+ unsigned long flags;
+ u32 cfg;
+
+ spin_lock_irqsave(&lock, flags);
+
+ cfg = __raw_readl(S5P_MIPI_DPHY_CONTROL) & ~rst;
+ if (on)
+ cfg |= rst;
+ __raw_writel(cfg, S5P_MIPI_DPHY_CONTROL);
+
+ if (on)
+ cfg |= S5P_MIPI_DPHY_ENABLE;
+ else if (!(cfg & (S5P_MIPI_DPHY_SRESETN | S5P_MIPI_DPHY_MRESETN) & ~rst))
+ cfg &= ~S5P_MIPI_DPHY_ENABLE;
+
+ __raw_writel(cfg, S5P_MIPI_DPHY_CONTROL);
+
+ spin_unlock_irqrestore(&lock, flags);
+
+ return 0;
+}
+
+int s5p_csis_phy_control(struct platform_device *pdev, bool on)
+{
+ return s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_SRESETN);
+}
+
+int s5p_dsim_phy_control(struct platform_device *pdev, bool on)
+{
+ return s5p_mipi_phy_control(pdev, on, S5P_MIPI_DPHY_MRESETN);
+}
--
1.7.3.4
^ permalink raw reply related
* [PATCH/RFC 2/3] ARM: S5PV310: Add a platform helper for MIPI DSIM/CSIS setup
From: Sylwester Nawrocki @ 2011-01-04 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294153764-25006-1-git-send-email-s.nawrocki@samsung.com>
MIPI_PHYn_CONTROL registers are shared between MIPI DSIM
and MIPI CSIS drivers so a spinlock is used to protect multiple
access to these registers. Also a proper state of a common
PHY enable bit is maintained in order to avoid a DSIM
and CSIS driver conflict.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/mach-s5pv310/Kconfig | 6 ++
arch/arm/mach-s5pv310/Makefile | 2 +
arch/arm/mach-s5pv310/include/mach/map.h | 7 +--
arch/arm/mach-s5pv310/include/mach/regs-pmu.h | 6 ++
arch/arm/mach-s5pv310/setup-mipi.c | 62 +++++++++++++++++++++++++
5 files changed, 79 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-s5pv310/setup-mipi.c
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index b7aa3cd..2420076 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -15,6 +15,11 @@ config CPU_S5PV310
help
Enable S5PV310 CPU support
+config S5PV310_SETUP_MIPI
+ bool
+ help
+ Common setup code for MIPI CSIS/DSIM channels 0 and 1.
+
config S5PV310_DEV_PD
bool
help
@@ -96,6 +101,7 @@ config MACH_UNIVERSAL_C210
select S3C_DEV_HSMMC3
select S5PV310_SETUP_SDHCI
select S3C_DEV_I2C1
+ select S5PV310_SETUP_MIPI
select S5PV310_SETUP_I2C1
help
Machine support for Samsung Mobile Universal S5PC210 Reference
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 651f193..7f1b89b 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -29,6 +29,8 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
# device support
obj-y += dev-audio.o
+
+obj-$(CONFIG_S5PV310_SETUP_MIPI) += setup-mipi.o
obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 33bcff2..6635287 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -65,8 +65,7 @@
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
-#define S5PV310_PA_MIPI_CSIS0 0x11880000
-#define S5PV310_PA_MIPI_CSIS1 0x11890000
+#define S5PV310_PA_MIPI_CSIS(x) (0x11880000 + ((x) * 0x10000))
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
@@ -124,7 +123,7 @@
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
#define S3C_PA_RTC S5PV310_PA_RTC
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
-#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
+#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS(0)
+#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS(1)
#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
index fb333d0..bef8102 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
@@ -27,4 +27,10 @@
#define S5P_INT_LOCAL_PWR_EN 0x7
+#define S5P_MIPI_PHY0_CONTROL S5P_PMUREG(0x0710)
+#define S5P_MIPI_PHY1_CONTROL S5P_PMUREG(0x0714)
+#define S5P_MIPI_PHY_ENABLE (1 << 0)
+#define S5P_MIPI_PHY_SRESETN (1 << 1)
+#define S5P_MIPI_PHY_MRESETN (1 << 2)
+
#endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-s5pv310/setup-mipi.c b/arch/arm/mach-s5pv310/setup-mipi.c
new file mode 100644
index 0000000..fc91a29
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-mipi.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/mach-s5pv310/setup-mipi.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd
+ *
+ * S5PV310 - Helper functions for MIPI CSIS/DSIM PHY control
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <mach/regs-pmu.h>
+
+/* Global MIPI CSIS or DSIM PHY enable and reset control. */
+static int s5p_mipi_phy_control(struct platform_device *pdev, bool on, u32 rst)
+{
+ static DEFINE_SPINLOCK(lock);
+ void __iomem *addr;
+ unsigned long flags;
+ int pid;
+ u32 cfg;
+
+ if (pdev == NULL)
+ return -EINVAL;
+
+ pid = pdev->id;
+ if (pid != 0 && pid != 1)
+ return -EINVAL;
+
+ addr = pid ? S5P_MIPI_PHY1_CONTROL : S5P_MIPI_PHY0_CONTROL;
+
+ spin_lock_irqsave(&lock, flags);
+
+ cfg = __raw_readl(addr) & ~rst;
+ if (on)
+ cfg |= rst;
+ __raw_writel(cfg, addr);
+
+ if (on)
+ cfg |= S5P_MIPI_PHY_ENABLE;
+ else if (!(cfg & (S5P_MIPI_PHY_SRESETN | S5P_MIPI_PHY_MRESETN) & ~rst))
+ cfg &= ~S5P_MIPI_PHY_ENABLE;
+
+ __raw_writel(cfg, addr);
+
+ spin_unlock_irqrestore(&lock, flags);
+ return 0;
+}
+
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on)
+{
+ return s5p_mipi_phy_control(pdev, on, S5P_MIPI_PHY_SRESETN);
+}
+
+int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
+{
+ return s5p_mipi_phy_control(pdev, on, S5P_MIPI_PHY_MRESETN);
+}
--
1.7.3.4
^ permalink raw reply related
* [PATCH/RFC 1/3] ARM: S5P: Add a platform callback for MIPI CSIS PHY control
From: Sylwester Nawrocki @ 2011-01-04 15:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294153764-25006-1-git-send-email-s.nawrocki@samsung.com>
The phy_enable callback in struct s5p_platform_mipi_csis is added
to allow the CSIS driver to control its PHY enable and reset signals.
This allows to use same MIPI CSIS driver across various SoCs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
arch/arm/plat-s5p/dev-csis0.c | 2 +-
arch/arm/plat-s5p/dev-csis1.c | 2 +-
arch/arm/plat-s5p/include/plat/csis.h | 28 --------------------
arch/arm/plat-s5p/include/plat/mipi_csis.h | 39 ++++++++++++++++++++++++++++
4 files changed, 41 insertions(+), 30 deletions(-)
delete mode 100644 arch/arm/plat-s5p/include/plat/csis.h
create mode 100644 arch/arm/plat-s5p/include/plat/mipi_csis.h
diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c
index dfab1c8..57efe9c 100644
--- a/arch/arm/plat-s5p/dev-csis0.c
+++ b/arch/arm/plat-s5p/dev-csis0.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Samsung Electronics
+ * Copyright (C) 2010 Samsung Electronics Co., Ltd
*
* S5P series device definition for MIPI-CSIS channel 0
*
diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c
index e3053f2..c61b46b 100644
--- a/arch/arm/plat-s5p/dev-csis1.c
+++ b/arch/arm/plat-s5p/dev-csis1.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Samsung Electronics
+ * Copyright (C) 2010 Samsung Electronics Co., Ltd
*
* S5P series device definition for MIPI-CSIS channel 1
*
diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h
deleted file mode 100644
index 51e308c..0000000
--- a/arch/arm/plat-s5p/include/plat/csis.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics
- *
- * S5P series MIPI CSI slave device support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef PLAT_S5P_CSIS_H_
-#define PLAT_S5P_CSIS_H_ __FILE__
-
-/**
- * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
- * @clk_rate: bus clock frequency
- * @lanes: number of data lanes used
- * @alignment: data alignment in bits
- * @hs_settle: HS-RX settle time
- */
-struct s5p_platform_mipi_csis {
- unsigned long clk_rate;
- u8 lanes;
- u8 alignment;
- u8 hs_settle;
-};
-
-#endif /* PLAT_S5P_CSIS_H_ */
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-s5p/include/plat/mipi_csis.h
new file mode 100644
index 0000000..0b22065
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mipi_csis.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics, Co. Ltd
+ *
+ * S5P series MIPI CSI slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_MIPI_CSIS_H_
+#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
+
+struct platform_device;
+
+/**
+ * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS
+ * @clk_rate: bus clock frequency
+ * @lanes: number of data lanes used
+ * @alignment: data alignment in bits
+ * @hs_settle: HS-RX settle time
+ */
+struct s5p_platform_mipi_csis {
+ unsigned long clk_rate;
+ u8 lanes;
+ u8 alignment;
+ u8 hs_settle;
+ int (*phy_enable)(struct platform_device *pdev, bool on);
+};
+
+/**
+ * struct s5p_csis_phy_control - global MIPI-CSIS PHY control
+ * @pdev: platform device the mipi phy state is to be changed for
+ * @on: true to enable CSIS PHY and assert its reset,
+ * false will disable the PHY and put into reset state
+ */
+int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
+
+#endif /* PLAT_S5P_MIPI_CSIS_H_ */
--
1.7.3.4
^ permalink raw reply related
* [PATCH/RFC 0/3] ARM: S5P: Add a common platform setup code for MIPI CSIS/DSIM
From: Sylwester Nawrocki @ 2011-01-04 15:09 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
the following patch series adds the common platform code for configuration
of the MIPI CSIS and MIPI DSIM PHYs on S5PV210 and S5PV310 SoCs.
The spinlock is used to avoid races while the common PHY control register
is accessed from within MIPI DSIM and MIPI CSIS drivers.
The common PHY enable bit is cleared only when both CSIS and DSIM devices
are not in use.
The patch series contains:
[PATCH/RFC 1/3] ARM: S5P: Add a platform callback for MIPI CSIS PHY control
[PATCH/RFC 2/3] ARM: S5PV310: Add a platform helper for MIPI DSIM/CSIS setup
[PATCH/RFC 3/3] ARM: S5PV210: Add a platform helper for MIPI DSIM/CSIS setup
Rebased onto kgene-for-next branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
Regards,
Sylwester
--
Sylwester Nawrocki
Samsung Poland R&D Center
^ permalink raw reply
* [PATCH v2 05/10] net/fec: add dual fec support for mx28
From: Baruch Siach @ 2011-01-04 15:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104141259.GA21274@freescale.com>
Hi Shawn,
On Tue, Jan 04, 2011 at 10:13:09PM +0800, Shawn Guo wrote:
> On Tue, Jan 04, 2011 at 11:59:16AM +0200, Baruch Siach wrote:
> > On Tue, Jan 04, 2011 at 05:24:11PM +0800, Shawn Guo wrote:
[snip]
> > > -#ifdef CONFIG_ARCH_MXC
> > > -#include <mach/hardware.h>
> >
> > Since you now remove mach/hardware.h for ARCH_MXC, does this build for all
> > i.MX variants?
> >
> Did the test build for mx25, mx27, mx3 and mx51.
This is surprising. It means that this include was not needed in the first
place. git blame says this was added in 196719ec (fec: Add support for
Freescale MX27) by Sascha.
> > > +#ifdef CONFIG_SOC_IMX28
> > > +/*
> > > + * mx28 does not have MIIGSK registers
> > > + */
> > > +#undef FEC_MIIGSK_ENR
> > > +#include <mach/mxs.h>
> > > +#else
> > > +#define cpu_is_mx28() (0)
> > > +#endif
> >
> > This breaks kernels for multiple archs (e.g. i.MX28 and i.MX25). Please use
> > run-time detection of CPU type, and do the MII/RMII etc. configuration
> > accordingly.
> >
> I do not find a good way to detect cpu type. Neither adding a new
> platform data field nor using __machine_arch_type to enumerate all
> mx28 based machine (though there is only one currently) seems to be
> good for me.
How about:
#ifdef CONFIG_SOC_IMX28
#include <mach/mxs.h>
#else
#define cpu_is_mx28() (0)
#endif
if (cpu_is_mx28() {
/* Do i.MX28 stuff */
} else {
/* Do other i.MX stuff */
}
Note that the '#ifdef FEC_MIIGSK_ENR' section in fec_restart() is there only
to allow build for M5272 which does not have this define in fec.h. Physically,
i.MX27 does not have this register either.
> I will try to manipulate some mx28 unique register to identify mx28
> from other i.mx variants. Hopefully, it will work.
>
> Thanks for the comments.
baruch
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
From: Felipe Balbi @ 2011-01-04 14:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=JyoQuP-OQtV1yO0WR1GCM1LieHUj5Sn=ZfVim@mail.gmail.com>
Hi,
On Tue, 2011-01-04 at 22:40 +0800, Ming Lei wrote:
> > The end goal is just to drop all these ad-hoc "APIs" for accessing DMA
> > on musb code.
>
> If this kind of DMA controllers are only used by MUSB, seems not
> necessary to convert to dmaengine API. Any benefit we can get
> from the convert? MUSB is cross-platform already after all.
<irony>
correct, OMAP GPIO controller is only used on OMAPs, so why do we even
bother having gpiolib, right ?
</irony>
--
balbi
^ permalink raw reply
* [PATCH v3 1/2] ARM i.MX53: Some bug fix about MX53 MSL code
From: Yong Shen @ 2011-01-04 14:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294122176-26450-2-git-send-email-yong.shen@freescale.com>
Hi there,
Are there any more comments?
Because of the time difference, the review process is longer than it
should be. If no more comments, I am going to ask for merge, so more
works can be carry on based on this.
Thanks for understanding.
Yong
On 1/4/11, yong.shen at freescale.com <yong.shen@freescale.com> wrote:
> From: Yong Shen <yong.shen@linaro.org>
>
> 1. pll_base address should return right value
> 2. uart parent clk is from pll3
>
> Signed-off-by: Yong Shen <yong.shen@linaro.org>
> ---
> arch/arm/mach-mx5/clock-mx51-mx53.c | 25 ++++++++++++++++++++++++-
> arch/arm/mach-mx5/crm_regs.h | 4 ++++
> 2 files changed, 28 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c
> b/arch/arm/mach-mx5/clock-mx51-mx53.c
> index 2f9eae2..b290f3f 100644
> --- a/arch/arm/mach-mx5/clock-mx51-mx53.c
> +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
> @@ -124,7 +124,7 @@ static inline u32 _get_mux(struct clk *parent, struct
> clk *m0,
> return -EINVAL;
> }
>
> -static inline void __iomem *_get_pll_base(struct clk *pll)
> +static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
> {
> if (pll == &pll1_main_clk)
> return MX51_DPLL1_BASE;
> @@ -132,6 +132,20 @@ static inline void __iomem *_get_pll_base(struct clk
> *pll)
> return MX51_DPLL2_BASE;
> else if (pll == &pll3_sw_clk)
> return MX51_DPLL3_BASE;
> + else
> + BUG();
> +
> + return NULL;
> +}
> +
> +static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
> +{
> + if (pll == &pll1_main_clk)
> + return MX53_DPLL1_BASE;
> + else if (pll == &pll2_sw_clk)
> + return MX53_DPLL2_BASE;
> + else if (pll == &pll3_sw_clk)
> + return MX53_DPLL3_BASE;
> else if (pll == &mx53_pll4_sw_clk)
> return MX53_DPLL4_BASE;
> else
> @@ -140,6 +154,14 @@ static inline void __iomem *_get_pll_base(struct clk
> *pll)
> return NULL;
> }
>
> +static inline void __iomem *_get_pll_base(struct clk *pll)
> +{
> + if (cpu_is_mx51())
> + return _mx51_get_pll_base(pll);
> + else
> + return _mx53_get_pll_base(pll);
> +}
> +
> static unsigned long clk_pll_get_rate(struct clk *clk)
> {
> long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
> @@ -1243,6 +1265,7 @@ int __init mx53_clocks_init(unsigned long ckil,
> unsigned long osc,
>
> clk_tree_init();
>
> + clk_set_parent(&uart_root_clk, &pll3_sw_clk);
> clk_enable(&cpu_clk);
> clk_enable(&main_bus_clk);
>
> diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
> index 51ff9bb..b462c22 100644
> --- a/arch/arm/mach-mx5/crm_regs.h
> +++ b/arch/arm/mach-mx5/crm_regs.h
> @@ -19,6 +19,10 @@
> #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
>
> /*MX53*/
> +#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
> +#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
> +#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
> +#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
> #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
>
> /* PLL Register Offsets */
> --
> 1.7.0.4
>
>
>
^ permalink raw reply
* [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
From: Ming Lei @ 2011-01-04 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294149984.1822.9.camel@eowin>
Hi,
2011/1/4 Felipe Balbi <me@felipebalbi.com>:
> The end goal is just to drop all these ad-hoc "APIs" for accessing DMA
> on musb code.
If this kind of DMA controllers are only used by MUSB, seems not
necessary to convert to dmaengine API. Any benefit we can get
from the convert? MUSB is cross-platform already after all.
thanks,
--
Lei Ming
^ permalink raw reply
* [PATCH 0/4] variable PHYS_OFFSET support
From: Nicolas Pitre @ 2011-01-04 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104104112.GB16671@n2100.arm.linux.org.uk>
On Tue, 4 Jan 2011, Russell King - ARM Linux wrote:
> So, I don't think it's ready for this coming merge window.
OK, agreed.
We could also take the time to make the kdump kernel benefit from this
feature at the same time, removing the need from a special build of the
kernel for this purpose, which would be a direct application.
Nicolas
^ permalink raw reply
* [PATCH 1/4] ARM: runtime patching of __virt_to_phys() and __phys_to_virt()
From: Nicolas Pitre @ 2011-01-04 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104084517.GA9791@n2100.arm.linux.org.uk>
On Tue, 4 Jan 2011, Russell King - ARM Linux wrote:
> This is basically my patch with a few blank lines removed, a couple
> of \n's also removed, a #error if __virt_to_phys is defined by a platform,
> a minor tweak to the assembly and it being only usable on PXA.
>
> I much prefer my patch over this as anyone can use it. That's one of
> the reasons why I arranged the code testing for __virt_to_phys as I
> did, so the config option could be offered without having a big long
> dependency list attached to it.
I don't think offering the option that people can turn on and not having
the code effectively perform as expected is a good idea. People might
be expecting the feature to be there while in practice it is ignored
which would lead to confusion. Better to offer it so it can be selected
as needed in combination with other features, such as
CONFIG_AUTO_ZRELADDR (which in my opinion would be better hidden from
user selection as well).
As to the authorship, since I drafted the original design, Eric Miao did
the first implementation to validate the concept, and the code surviving
is mostly yours, I didn't know who to singularly attribute the patch to
in the author field. I can put yourself there if you feel this is more
appropriate.
Nicolas
^ permalink raw reply
* [PATCH v2 06/10] ARM: mx28: update clocks for dual fec support
From: Shawn Guo @ 2011-01-04 14:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104135818.GD25121@pengutronix.de>
Hi Uwe,
On Tue, Jan 04, 2011 at 02:58:18PM +0100, Uwe Kleine-K?nig wrote:
> Hello Shawn,
>
> On Tue, Jan 04, 2011 at 05:24:12PM +0800, Shawn Guo wrote:
> > Register clocks fec.0 and fec.1 for dual fec support.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > ---
> > Changes for v2:
> > - Rebase the patch against patch below which gets fundamental
> > clocks explicitly called in clk_enable.
> > [PATCH v4] ARM: mxs: Change duart device to use amba-pl011
> > - Register clocks fec.0 and fec.1 respectively than use wildcard
> > NULL for both instances.
> >
> > arch/arm/mach-mxs/clock-mx28.c | 1 +
> > 1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> > index f20b254..f79587b 100644
> > --- a/arch/arm/mach-mxs/clock-mx28.c
> > +++ b/arch/arm/mach-mxs/clock-mx28.c
> > @@ -607,6 +607,7 @@ static struct clk_lookup lookups[] = {
> > /* for amba-pl011 driver */
> > _REGISTER_CLOCK("duart", NULL, uart_clk)
> > _REGISTER_CLOCK("fec.0", NULL, fec_clk)
> > + _REGISTER_CLOCK("fec.1", NULL, fec_clk)
> Did you verify this works as intended? I didn't and consider it
> possible that after
>
> clk_enable("fec.0");
> clk_enable("fec.1");
> clk_disable("fec.1");
>
> the clk is off. Probably it just works, just want to prevent hard to
> find bugs ...
>
The clk should not be off. Looking at _REGISTER_CLOCK below, we are
registering both fec.0 and fec.1 on the same one fec_clk. IOW, the
usecount of the clk is working to control the on/off of the clk.
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
--
Regards,
Shawn
^ permalink raw reply
* [PATCH v2 05/10] net/fec: add dual fec support for mx28
From: Shawn Guo @ 2011-01-04 14:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104095916.GE2987@jasper.tkos.co.il>
Hi Baruch,
On Tue, Jan 04, 2011 at 11:59:16AM +0200, Baruch Siach wrote:
> Hi Shawn,
>
> On Tue, Jan 04, 2011 at 05:24:11PM +0800, Shawn Guo wrote:
> > This patch is to add mx28 dual fec support. Here are some key notes
> > for mx28 fec controller.
> >
> > - mx28 fec design made an assumption that it runs on a
> > big-endian system, which is incorrect. As the result, the
> > driver has to swap every frame going to and coming from
> > the controller.
> > - external phys can only be configured by fec0, which means
> > fec1 can not work independently and both phys need to be
> > configured by mii_bus attached on fec0.
> > - mx28 fec reset will get mac address registers reset too.
> > - MII/RMII mode and 10M/100M speed are configured differently
> > from i.mx/mxs fec controller.
> > - ETHER_EN bit must be set to get interrupt work.
> >
> > Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> > ---
> > Changes for v2:
> > - Use module parameter fec.macaddr over new kernel command line
> > fec_mac to pass mac address
>
> Since you introduce this new kernel command line parameter in patch #3 of this
> series, why not just make it right in the first place? This should make both
> patches smaller and easier for review.
>
> > - Update comment in fec_get_mac() to stop using confusing word
> > "default"
> > - Fix copyright breakage in fec.h
>
> Ditto.
>
Sorry for rushing to send the patch set out. All these updates
should happen on patch #3 than #5. This is a serious problem,
and I will fix it soon and resend as v3.
> > drivers/net/Kconfig | 7 ++-
> > drivers/net/fec.c | 139 ++++++++++++++++++++++++++++++++++++++++----------
> > drivers/net/fec.h | 5 +-
> > include/linux/fec.h | 3 +-
> > 4 files changed, 120 insertions(+), 34 deletions(-)
>
> [snip]
>
> > diff --git a/drivers/net/fec.c b/drivers/net/fec.c
> > index f147508..b2b3e37 100644
> > --- a/drivers/net/fec.c
> > +++ b/drivers/net/fec.c
> > @@ -17,6 +17,8 @@
> > *
> > * Bug fixes and cleanup by Philippe De Muyter (phdm at macqel.be)
> > * Copyright (c) 2004-2006 Macq Electronique SA.
> > + *
> > + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> > */
> >
> > #include <linux/module.h>
> > @@ -45,21 +47,34 @@
> >
> > #include <asm/cacheflush.h>
> >
> > -#ifndef CONFIG_ARCH_MXC
> > +#if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_SOC_IMX28)
> > #include <asm/coldfire.h>
> > #include <asm/mcfsim.h>
> > #endif
> >
> > #include "fec.h"
> >
> > -#ifdef CONFIG_ARCH_MXC
> > -#include <mach/hardware.h>
>
> Since you now remove mach/hardware.h for ARCH_MXC, does this build for all
> i.MX variants?
>
Did the test build for mx25, mx27, mx3 and mx51.
> > +#ifdef CONFIG_SOC_IMX28
> > +/*
> > + * mx28 does not have MIIGSK registers
> > + */
> > +#undef FEC_MIIGSK_ENR
> > +#include <mach/mxs.h>
> > +#else
> > +#define cpu_is_mx28() (0)
> > +#endif
>
> This breaks kernels for multiple archs (e.g. i.MX28 and i.MX25). Please use
> run-time detection of CPU type, and do the MII/RMII etc. configuration
> accordingly.
>
I do not find a good way to detect cpu type. Neither adding a new
platform data field nor using __machine_arch_type to enumerate all
mx28 based machine (though there is only one currently) seems to be
good for me.
I will try to manipulate some mx28 unique register to identify mx28
from other i.mx variants. Hopefully, it will work.
Thanks for the comments.
--
Regards,
Shawn
^ permalink raw reply
* [PATCH 1/2] serial: Provide capability to disable modem status interrupts in 8250 driver
From: Michael Williamson @ 2011-01-04 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104135621.56a4770e@lxorguk.ukuu.org.uk>
On 1/4/2011 8:56 AM, Alan Cox wrote:
>> This patch was tested using a MityDSP-L138F platform having a UART CTS pin
>> connected to a clock signal (and configured, via pinmux, as a clock input
>> for another peripheral function).
>
> Please hide such horrors in your platform code. We are trying todrive all
> the quirks stuff we can out of the core code.
>
> Instead provide your own I/O methods when registering the port and mask
> the appropriate bogus bits in the register.
>
Got it. Thanks for the guidance.
-Mike
^ permalink raw reply
* [PATCH 2/4] arm: Kconfig: remove duplicated GENERIC_HARDIRQS entry
From: Felipe Balbi @ 2011-01-04 14:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110104140031.GE25121@pengutronix.de>
On Tue, 2011-01-04 at 15:00 +0100, Uwe Kleine-K?nig wrote:
> On Tue, Jan 04, 2011 at 02:02:55PM +0200, Felipe Balbi wrote:
> > GENERIC_HARDIRQS is defined under kernel/irq/Kconfig,
> > so it's safe to drop the duplicated entry and simply
> > select HAVE_GENERIC_HARDIRQS.
> >
> > Signed-off-by: Felipe Balbi <balbi@ti.com>
> > ---
> > arch/arm/Kconfig | 8 +-------
> > 1 files changed, 1 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index d56d21c0..e6f0f8b 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -15,6 +15,7 @@ config ARM
> > select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
> > select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
> > select HAVE_GENERIC_DMA_COHERENT
> > + select HAVE_GENERIC_HARDIRQS
> > select HAVE_KERNEL_GZIP
> > select HAVE_KERNEL_LZO
> > select HAVE_KERNEL_LZMA
> > @@ -88,10 +89,6 @@ config MCA
> > <file:Documentation/mca.txt> (and especially the web page given
> > there) before attempting to build an MCA bus kernel.
> >
> > -config GENERIC_HARDIRQS
> > - bool
> > - default y
> > -
> > config STACKTRACE_SUPPORT
> > bool
> > default y
> > @@ -171,9 +168,6 @@ config FIQ
> > config ARCH_MTD_XIP
> > bool
> >
> > -config GENERIC_HARDIRQS_NO__DO_IRQ
> > - def_bool y
> > -
> You didn't mention this change in the commit log. Is this duplicated,
> too or did it just slip through?
Yes it is. My bad. Do I need to update the patch ? I can do it tomorrow.
--
balbi
^ permalink raw reply
* [PATCH v5 1/3] ARM: add CPPI 4.1 DMA support
From: Felipe Balbi @ 2011-01-04 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D231B5F.7030607@mvista.com>
Hi,
(using personal email, left the office)
On Tue, 2011-01-04 at 16:06 +0300, Sergei Shtylyov wrote:
> >> I think we will get more clarity once we start on this activity.
>
> > I agree, but I personally don't see that many limiting factors.
> > dmaengine is just a generic API for doing DMA transfers. If it's not
> > enough for us currently, we extend it.
>
> Putting MUSB DMA enignes into drivers/dma/ is the same as taking *any*
> chip capable of bus-mastering DMA, "separating" its bus mastering related code
> from its driver and putting this code into drivers/dma/. This doesn't make
> sense, in my opinion. drivers/dma/ is for the dedicated DMA controllers (which
> can *optionally* serve the slave devices).
Do I really have to spell it out ? Really ?
You don't need to physically move the part of the code to drivers/dma,
but it has to use the API. The mentor DMA is internal to MUSB.
tusb6010_omap.c isn't.
Where it makes sense to move the code under drivers/dma, it will be
done, where it doesn't, it won't be done, but it will use the same API.
That's all.
The end goal is just to drop all these ad-hoc "APIs" for accessing DMA
on musb code.
--
balbi
^ permalink raw reply
* [PATCH 2/4] arm: Kconfig: remove duplicated GENERIC_HARDIRQS entry
From: Uwe Kleine-König @ 2011-01-04 14:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294142577-28772-3-git-send-email-balbi@ti.com>
On Tue, Jan 04, 2011 at 02:02:55PM +0200, Felipe Balbi wrote:
> GENERIC_HARDIRQS is defined under kernel/irq/Kconfig,
> so it's safe to drop the duplicated entry and simply
> select HAVE_GENERIC_HARDIRQS.
>
> Signed-off-by: Felipe Balbi <balbi@ti.com>
> ---
> arch/arm/Kconfig | 8 +-------
> 1 files changed, 1 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d56d21c0..e6f0f8b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -15,6 +15,7 @@ config ARM
> select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
> select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
> select HAVE_GENERIC_DMA_COHERENT
> + select HAVE_GENERIC_HARDIRQS
> select HAVE_KERNEL_GZIP
> select HAVE_KERNEL_LZO
> select HAVE_KERNEL_LZMA
> @@ -88,10 +89,6 @@ config MCA
> <file:Documentation/mca.txt> (and especially the web page given
> there) before attempting to build an MCA bus kernel.
>
> -config GENERIC_HARDIRQS
> - bool
> - default y
> -
> config STACKTRACE_SUPPORT
> bool
> default y
> @@ -171,9 +168,6 @@ config FIQ
> config ARCH_MTD_XIP
> bool
>
> -config GENERIC_HARDIRQS_NO__DO_IRQ
> - def_bool y
> -
You didn't mention this change in the commit log. Is this duplicated,
too or did it just slip through?
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v2 06/10] ARM: mx28: update clocks for dual fec support
From: Uwe Kleine-König @ 2011-01-04 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294133056-21195-7-git-send-email-shawn.guo@freescale.com>
Hello Shawn,
On Tue, Jan 04, 2011 at 05:24:12PM +0800, Shawn Guo wrote:
> Register clocks fec.0 and fec.1 for dual fec support.
>
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> ---
> Changes for v2:
> - Rebase the patch against patch below which gets fundamental
> clocks explicitly called in clk_enable.
> [PATCH v4] ARM: mxs: Change duart device to use amba-pl011
> - Register clocks fec.0 and fec.1 respectively than use wildcard
> NULL for both instances.
>
> arch/arm/mach-mxs/clock-mx28.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> index f20b254..f79587b 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -607,6 +607,7 @@ static struct clk_lookup lookups[] = {
> /* for amba-pl011 driver */
> _REGISTER_CLOCK("duart", NULL, uart_clk)
> _REGISTER_CLOCK("fec.0", NULL, fec_clk)
> + _REGISTER_CLOCK("fec.1", NULL, fec_clk)
Did you verify this works as intended? I didn't and consider it
possible that after
clk_enable("fec.0");
clk_enable("fec.1");
clk_disable("fec.1");
the clk is off. Probably it just works, just want to prevent hard to
find bugs ...
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH 1/2] serial: Provide capability to disable modem status interrupts in 8250 driver
From: Alan Cox @ 2011-01-04 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294149062-31173-1-git-send-email-michael.williamson@criticallink.com>
> This patch was tested using a MityDSP-L138F platform having a UART CTS pin
> connected to a clock signal (and configured, via pinmux, as a clock input
> for another peripheral function).
Please hide such horrors in your platform code. We are trying todrive all
the quirks stuff we can out of the core code.
Instead provide your own I/O methods when registering the port and mask
the appropriate bogus bits in the register.
^ permalink raw reply
* [PATCH 2/2] davinci: Disable modem status (CTS) interrupts on UART1
From: Michael Williamson @ 2011-01-04 13:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1294149062-31173-1-git-send-email-michael.williamson@criticallink.com>
All supported configurations of the MityDSP-L138 and MityARM-1808 platforms do
not use the CTS pin associated with UART1 as a CTS function. Instead, this
pin is typically configured as AHCLKX for the McASP or as the USB reference clock.
Disable the modem status interrupts that may be generated by this pin toggling.
Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
---
arch/arm/mach-davinci/board-mityomapl138.c | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0bb5f0c..87ffe06 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -17,6 +17,7 @@
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/etherdevice.h>
+#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -352,6 +353,16 @@ static struct platform_device da850_pm_device = {
.id = -1,
};
+static void __init mityomapl138_init_serial(void)
+{
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+ struct device *dev = &soc_info->serial_dev->dev;
+ struct plat_serial8250_port *p = dev->platform_data;
+
+ p[1].flags |= UPF_NO_MSR;
+ davinci_serial_init(&mityomapl138_uart_config);
+}
+
static void __init mityomapl138_init(void)
{
int ret;
@@ -365,7 +376,7 @@ static void __init mityomapl138_init(void)
if (ret)
pr_warning("watchdog registration failed: %d\n", ret);
- davinci_serial_init(&mityomapl138_uart_config);
+ mityomapl138_init_serial();
ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
if (ret)
--
1.7.0.4
^ permalink raw reply related
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