* [PATCH 2/2] ARM: remove the 4x expansion presumption while decompressing the kernel
From: Nicolas Pitre @ 2011-02-17 20:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217185223.GA30606@n2100.arm.linux.org.uk>
On Thu, 17 Feb 2011, Russell King - ARM Linux wrote:
> On Thu, Feb 17, 2011 at 10:51:56AM -0700, Grant Likely wrote:
> > As for knowing where it can relocate to, we already know (actually
> > current code just makes an assumption) about how long the kernel
> > proper image is and where it wants to live in the zImage's head.S.
> > Assuming enough ram, if r6 reflects the size of the zImage + the size
> > of the appended data then it should be good.
>
> That isn't a valid argument. Just because "the decompressor already
> does it" does not mean that it'll work with ramdisks. We've been
> lucky so far that it has worked with the kernel - and that's exactly
> what it is - luck.
Two things here:
1) It is possible to know the length of an ATAG or DT block. The size
of a ramdisk image is not known without external information.
2) If the size of a ramdisk was discoverable by the zImage code, and if
the ramdisk image was simply appended to zImage itself, then there
would be no guessing as to where to allocate and load things as
separate blobs.
Let's suppose zImage is 1MB in size, the appended ramdisk image is 16MB,
and the decompressed kernel is 3MB. And for simplicity let's ignore
TEXT_OFFSET for the moment.
If zImage is loaded at 3MB from start of physical memory (or above) then
nothing needs to be relocated. It will simply decompress the kernel
from 0MB up to 3MB from start of physical memory. If a ramdisk is
appended to zImage then that location can be passed straight to the
kernel. We only need to make sure the kernel .bss is not larger than
1MB in that case which should be the norm. No guessing, no reliance on
luck. The only limitation is that you need at least 20MB of RAM here,
and there is no way around it whatever the booting method. (Actually you
could save 1MB by not using zImage but a straight Image, but if you're
so tight in RAM you shouldn't use a ramdisk to start with.)
If zImage is loaded at 0MB (typical) then it has to move things around.
Currently the code decompress the kernel and store it from the 1MB
address up to the 4MB address, and then move the kernel back down to 0MB
(a 3MB copy). What my patch does is to have zImage copy itself (1MB
large) to the 3MB address and then decompress the kernel from 0MB to
3MB.
Now if there is a ramdisk image appended to zImage, the zImage
relocation becomes a 17MB copy. And to be 100% safe, we might consider
the end of the kernel .bss to determine the relocation address for
zImage. But still, the final situation is the same as the case where no
relocation is needed. The ramdisk image is relocated along with zImage
to the optimal location i.e. from 4MB upwards. Again, no guessing, no
reliance on luck, no risk of overwriting a separately loaded ramdisk.
Of course this doesn't work on targets with segmented memory such as on
SA1100. For those the conventional method of loading the kernel in one
segment and the ramdisk in another must be preserved.
But with modern ARM machines, it would be far simpler to just
cat zImage ramdisk.gz > boot_image
and load that boot_image anywhere in memory and no bother with guesses
as to where to separately load the ramdisk and hope it won't get
overwritten at some point by the kernel decompressor.
But we're not there with initrd yet. I believe the rework of the
decompressor code has great value on its own. And then the
concatenation trick could be used for DTB which can be easily be self
sized. Doing that with a ramdisk image would require some information
header in between. But one step at a time.
Nicolas
^ permalink raw reply
* [patch-v2.6.39 6/7] OMAP4430: hwmod data: Adding USBOTG
From: Tony Lindgren @ 2011-02-17 21:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217190809.GM14574@legolas.emea.dhcp.ti.com>
* Felipe Balbi <balbi@ti.com> [110217 11:06]:
> On Thu, Feb 17, 2011 at 10:18:49AM -0800, Tony Lindgren wrote:
> > * Cousson, Benoit <b-cousson@ti.com> [110217 09:45]:
> > >
> > > Done, boot tested, and that does remove the warning about the
> > > missing opt clock you had with the previous data.
> > >
> > > git://gitorious.org/omap-pm/linux.git for_2.6.39/omap4_hwmod_data
> > >
> > > Just let me know if it does break anything else.
> >
> > Pulled into omap-for-linus. Also now merged are the devel-hwspinlock
> > and devel-mcspi branches.
>
> Ok good. Tomorrow I'll send you a proper pull request for my part, will
> leave testusb running over night.
OK sounds good to me.
Tony
^ permalink raw reply
* [PATCH V3 3/4] ARM: Xilinx: base header files and assembly macros
From: Stephen Boyd @ 2011-02-17 21:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217100126.GD22961@pulham.picochip.com>
On 02/17/2011 02:01 AM, Jamie Iles wrote:
>> +
>> +static void putc(char ch)
>> +{
>> + /*
>> + * Wait for room in the FIFO, then write the char into the FIFO
>> + */
>> + while (UART_STATUS(LL_UART_PADDR) & UART_SR_TXFULL)
>> + ;
>
> It might be worth adding a barrier() call to these loops to be explicit
> about the volatility.
I think you want cpu_relax() then.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH 5/5] OMAP3EVM: Set TSC wakeup option in pad config
From: Tony Lindgren @ 2011-02-17 22:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87k4hqnq6l.fsf@ti.com>
* Kevin Hilman <khilman@ti.com> [110127 10:41]:
> Vaibhav Hiremath <hvaibhav@ti.com> writes:
>
> > Set OMAP_PIN_OFF_WAKEUPENABLE to enable the wake-up
> > functionality from touchscreen controller.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> > arch/arm/mach-omap2/board-omap3evm.c | 6 ++++--
> > 1 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
> > index 2a2efa9..5eddf93 100644
> > --- a/arch/arm/mach-omap2/board-omap3evm.c
> > +++ b/arch/arm/mach-omap2/board-omap3evm.c
> > @@ -716,7 +716,8 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
> > OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
> > OMAP_PIN_OFF_WAKEUPENABLE),
> > OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
> > - OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
> > + OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
> > + OMAP_PIN_OFF_WAKEUPENABLE),
>
> This hunk doesn't apply because the code below (SYS_BOOT5, etc.) doesn't
> exist in upstream code.
Looks like this applies on top of current omap-for-linus with the mcspi changes
in. So I've applied all the omap3evm related patches.
I had to resolve few changes manually with wl12xx changes, can you guys please
check that everything is working? Pushing them into the devel-board branch.
Regards,
Tony
^ permalink raw reply
* [PATCHv3] mx31: add support for the bugbase 1.3 from buglabs
From: Uwe Kleine-König @ 2011-02-17 22:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297956221.2675.1.camel@gnutoo-laptop>
On Thu, Feb 17, 2011 at 04:23:41PM +0100, Denis 'GNUtoo' Carikli wrote:
> > And I wonder there is no copyright statement by you in
> > arch/arm/mach-mx3/mach-bug.c, maybe because you consider your changes
> > too minor to be relevant? (INAL and I don't know who to value your
> > contribution.)
> Here is the thread:
> http://thread.gmane.org/gmane.linux.ports.arm.msm/122
read that, too.
>
> What should I do? can I add my own name too?
I don't care much. These machine files are more or less trivial, and as
I said, INAL. But I would be surprised if you would be kicked in a
similar way for adding a copyright to "your" machine file. I think its
is quite usual to add one's own copyright.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH 5/6] ARM: pm: convert samsung platforms to generic suspend/resume support
From: Kukjin Kim @ 2011-02-17 23:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217140621.GC24989@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
>
> On Thu, Feb 17, 2011 at 09:09:02PM +0900, Kukjin Kim wrote:
> > Hi Russell,
> >
> > I tested on SMDKV210(S5PV210) and SMDKC110(S5PC110).
>
> Thanks for testing. It looks like I'm missing a load for r3 in the
> s5pv210 code. The replacement patch below should resolve this.
>
Hooray, it works fine ;)
Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Good night.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
> arch/arm/mach-s3c64xx/sleep.S | 63 +-----------------
> arch/arm/mach-s5pv210/sleep.S | 105
+----------------------------
> -
> arch/arm/plat-s3c24xx/sleep.S | 57 +----------------
> arch/arm/plat-samsung/include/plat/pm.h | 12 +---
> arch/arm/plat-samsung/pm.c | 16 +-----
> 5 files changed, 14 insertions(+), 239 deletions(-)
>
> diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
> index b2ef443..afe5a76 100644
> --- a/arch/arm/mach-s3c64xx/sleep.S
> +++ b/arch/arm/mach-s3c64xx/sleep.S
> @@ -32,25 +32,13 @@
> * code after resume.
> *
> * entry:
> - * r0 = pointer to the save block
> + * r1 = v:p offset
> */
>
> ENTRY(s3c_cpu_save)
> stmfd sp!, { r4 - r12, lr }
> -
> - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
> - mrc p15, 0, r5, c3, c0, 0 @ Domain ID
> - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
> - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
> - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
> - mrc p15, 0, r9, c1, c0, 0 @ Control register
> - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
> - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
> -
> - stmia r0, { r4 - r13 } @ Save CP registers and SP
> -
> - @@ save our state to ram
> - bl s3c_pm_cb_flushcache
> + ldr r3, =resume_with_mmu
> + bl cpu_suspend
>
> @@ call final suspend code
> ldr r0, =pm_cpu_sleep
> @@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save)
> resume_with_mmu:
> ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
>
> - .data
> -
> - /* the next bit is code, but it requires easy access to the
> - * s3c_sleep_save_phys data before the MMU is switched on, so
> - * we store the code that needs this variable in the .data where
> - * the value can be written to (the .text segment is RO).
> - */
> -
> - .global s3c_sleep_save_phys
> -s3c_sleep_save_phys:
> - .word 0
> -
> /* Sleep magic, the word before the resume entry point so that the
> * bootloader can check for a resumeable image. */
>
> @@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume)
> orr r0, r0, #1 << 15 @ GPN15
> str r0, [ r3, #S3C64XX_GPNDAT ]
> #endif
> -
> - /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
> - * are thoroughly cleaned just in case the bootloader didn't do it
> - * for us. */
> - mov r0, #0
> - mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
> - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
> - mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
> - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
> - @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
> - @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
> -
> - ldr r0, s3c_sleep_save_phys
> - ldmia r0, { r4 - r13 }
> -
> - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
> - mcr p15, 0, r5, c3, c0, 0 @ Domain ID
> - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
> - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
> - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
> - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
> -
> - mov r0, #0 @ restore copro access controls
> - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
> - mcr p15, 0, r0, c7, c5, 4
> -
> - ldr r2, =resume_with_mmu
> - mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
> - nop
> - mov pc, r2 /* jump back */
> -
> - .end
> + b cpu_resume
> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
> index d4d222b..a3d6494 100644
> --- a/arch/arm/mach-s5pv210/sleep.S
> +++ b/arch/arm/mach-s5pv210/sleep.S
> @@ -35,50 +35,24 @@
> /* s3c_cpu_save
> *
> * entry:
> - * r0 = save address (virtual addr of s3c_sleep_save_phys)
> + * r1 = v:p offset
> */
>
> ENTRY(s3c_cpu_save)
>
> stmfd sp!, { r3 - r12, lr }
> -
> - mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
> - mrc p15, 0, r5, c3, c0, 0 @ Domain ID
> - mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
> - mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
> - mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
> - mrc p15, 0, r9, c1, c0, 0 @ Control register
> - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
> - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
> - mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
> - mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
> -
> - stmia r0, { r3 - r13 }
> -
> - bl s3c_pm_cb_flushcache
> + ldr r3, =resume_with_mmu
> + bl cpu_suspend
>
> ldr r0, =pm_cpu_sleep
> ldr r0, [ r0 ]
> mov pc, r0
>
> resume_with_mmu:
> - /*
> - * After MMU is turned on, restore the previous MMU table.
> - */
> - ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
> - add r4, r4, r9
> - str r12, [r4]
> -
> ldmfd sp!, { r3 - r12, pc }
>
> .ltorg
>
> - .data
> -
> - .global s3c_sleep_save_phys
> -s3c_sleep_save_phys:
> - .word 0
> -
> /* sleep magic, to allow the bootloader to check for an valid
> * image to resume to. Must be the first word before the
> * s3c_cpu_resume entry.
> @@ -96,75 +70,4 @@ s3c_sleep_save_phys:
> */
>
> ENTRY(s3c_cpu_resume)
> - mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
> - msr cpsr_c, r0
> -
> - mov r1, #0
> - mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
> - mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
> -
> - ldr r0, s3c_sleep_save_phys @ address of restore
> block
> - ldmia r0, { r3 - r13 }
> -
> - mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
> - mcr p15, 0, r5, c3, c0, 0 @ Domain ID
> -
> - mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
> - mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
> - mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
> -
> - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
> -
> - mov r0, #0
> - mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
> -
> - mov r0, #0 @ restore copro access
> - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
> - mcr p15, 0, r0, c7, c5, 4
> -
> - mcr p15, 0, r12, c10, c2, 0 @ write PRRR
> - mcr p15, 0, r3, c10, c2, 1 @ write NMRR
> -
> - /*
> - * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
> - * And there are no valid entries in the MMU table at this point.
> - * So before turning on the MMU, the MMU entry for the DRAM address
> - * range is added. After the MMU is turned on, the other entries
> - * in the MMU table will be restored.
> - */
> -
> - /* r6 = Translation Table BASE0 */
> - mov r4, r6
> - mov r4, r4, LSR #14
> - mov r4, r4, LSL #14
> -
> - /* Load address for adding to MMU table list */
> - ldr r11, =0xE010F000 @ INFORM0 reg.
> - ldr r10, [r11, #0]
> - mov r10, r10, LSR #18
> - bic r10, r10, #0x3
> - orr r4, r4, r10
> -
> - /* Calculate MMU table entry */
> - mov r10, r10, LSL #18
> - ldr r5, =0x40E
> - orr r10, r10, r5
> -
> - /* Back up originally data */
> - ldr r12, [r4]
> -
> - /* Add calculated MMU table entry into MMU table list */
> - str r10, [r4]
> -
> - ldr r2, =resume_with_mmu
> - mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
> -
> - nop
> - nop
> - nop
> - nop
> - nop @ second-to-last before mmu
> -
> - mov pc, r2 @ go back to virtual address
> -
> - .ltorg
> + b cpu_resume
> diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
> index e73e3b6..fd7032f 100644
> --- a/arch/arm/plat-s3c24xx/sleep.S
> +++ b/arch/arm/plat-s3c24xx/sleep.S
> @@ -44,23 +44,13 @@
> /* s3c_cpu_save
> *
> * entry:
> - * r0 = save address (virtual addr of s3c_sleep_save_phys)
> + * r1 = v:p offset
> */
>
> ENTRY(s3c_cpu_save)
> stmfd sp!, { r4 - r12, lr }
> -
> - @@ store co-processor registers
> -
> - mrc p15, 0, r4, c13, c0, 0 @ PID
> - mrc p15, 0, r5, c3, c0, 0 @ Domain ID
> - mrc p15, 0, r6, c2, c0, 0 @ translation table base address
> - mrc p15, 0, r7, c1, c0, 0 @ control register
> -
> - stmia r0, { r4 - r13 }
> -
> - @@ write our state back to RAM
> - bl s3c_pm_cb_flushcache
> + ldr r3, =resume_with_mmu
> + bl cpu_suspend
>
> @@ jump to final code to send system to sleep
> ldr r0, =pm_cpu_sleep
> @@ -76,20 +66,6 @@ resume_with_mmu:
>
> .ltorg
>
> - @@ the next bits sit in the .data segment, even though they
> - @@ happen to be code... the s3c_sleep_save_phys needs to be
> - @@ accessed by the resume code before it can restore the MMU.
> - @@ This means that the variable has to be close enough for the
> - @@ code to read it... since the .text segment needs to be RO,
> - @@ the data segment can be the only place to put this code.
> -
> - .data
> -
> - .global s3c_sleep_save_phys
> -s3c_sleep_save_phys:
> - .word 0
> -
> -
> /* sleep magic, to allow the bootloader to check for an valid
> * image to resume to. Must be the first word before the
> * s3c_cpu_resume entry.
> @@ -100,10 +76,6 @@ s3c_sleep_save_phys:
> /* s3c_cpu_resume
> *
> * resume code entry for bootloader to call
> - *
> - * we must put this code here in the data segment as we have no
> - * other way of restoring the stack pointer after sleep, and we
> - * must not write to the code segment (code is read-only)
> */
>
> ENTRY(s3c_cpu_resume)
> @@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume)
> beq 1001b
> #endif /* CONFIG_DEBUG_RESUME */
>
> - mov r1, #0
> - mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
> - mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
> -
> - ldr r0, s3c_sleep_save_phys @ address of restore
> block
> - ldmia r0, { r4 - r13 }
> -
> - mcr p15, 0, r4, c13, c0, 0 @ PID
> - mcr p15, 0, r5, c3, c0, 0 @ Domain ID
> - mcr p15, 0, r6, c2, c0, 0 @ translation table base
> -
> -#ifdef CONFIG_DEBUG_RESUME
> - mov r3, #'R'
> - strb r3, [ r2, #S3C2410_UTXH ]
> -#endif
> -
> - ldr r2, =resume_with_mmu
> - mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc
> - nop @ second-to-last before mmu
> - mov pc, r2 @ go back to virtual address
> -
> - .ltorg
> + b cpu_resume
> diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-
> samsung/include/plat/pm.h
> index d9025e3..4aa697d 100644
> --- a/arch/arm/plat-samsung/include/plat/pm.h
> +++ b/arch/arm/plat-samsung/include/plat/pm.h
> @@ -50,13 +50,11 @@ extern unsigned char pm_uart_udivslot; /* true to
save
> UART UDIVSLOT */
>
> /* from sleep.S */
>
> -extern int s3c_cpu_save(unsigned long *saveblk);
> +extern int s3c_cpu_save(unsigned long *saveblk, long);
> extern void s3c_cpu_resume(void);
>
> extern void s3c2410_cpu_suspend(void);
>
> -extern unsigned long s3c_sleep_save_phys;
> -
> /* sleep save info */
>
> /**
> @@ -179,13 +177,5 @@ extern void s3c_pm_restore_gpios(void);
> */
> extern void s3c_pm_save_gpios(void);
>
> -/**
> - * s3c_pm_cb_flushcache - callback for assembly code
> - *
> - * Callback to issue flush_cache_all() as this call is
> - * not a directly callable object.
> - */
> -extern void s3c_pm_cb_flushcache(void);
> -
> extern void s3c_pm_save_core(void);
> extern void s3c_pm_restore_core(void);
> diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
> index 02d531f..d5b58d3 100644
> --- a/arch/arm/plat-samsung/pm.c
> +++ b/arch/arm/plat-samsung/pm.c
> @@ -241,8 +241,6 @@ void (*pm_cpu_sleep)(void);
>
> static int s3c_pm_enter(suspend_state_t state)
> {
> - static unsigned long regs_save[16];
> -
> /* ensure the debug is initialised (if enabled) */
>
> s3c_pm_debug_init();
> @@ -266,12 +264,6 @@ static int s3c_pm_enter(suspend_state_t state)
> return -EINVAL;
> }
>
> - /* store the physical address of the register recovery block */
> -
> - s3c_sleep_save_phys = virt_to_phys(regs_save);
> -
> - S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
> -
> /* save all necessary core registers not covered by the drivers */
>
> s3c_pm_save_gpios();
> @@ -305,7 +297,7 @@ static int s3c_pm_enter(suspend_state_t state)
> * we resume as it saves its own register state and restores it
> * during the resume. */
>
> - s3c_cpu_save(regs_save);
> + s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
>
> /* restore the cpu state using the kernel's cpu init code. */
>
> @@ -336,12 +328,6 @@ static int s3c_pm_enter(suspend_state_t state)
> return 0;
> }
>
> -/* callback from assembly code */
> -void s3c_pm_cb_flushcache(void)
> -{
> - flush_cache_all();
> -}
> -
> static int s3c_pm_prepare(void)
> {
> /* prepare check area if configured */
^ permalink raw reply
* compiling 2.6.37 kernel in THUMB2 mode
From: vb at vsbe.com @ 2011-02-17 23:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTik1FY=K1Wuo=vnh5xuq6aS1x2d2Km=ByrCSufJC@mail.gmail.com>
On Thu, Feb 17, 2011 at 9:30 AM, <vb@vsbe.com> wrote:
>
> It looks like certain files need to be compiled in ARM mode even when
> THUMB2_KERNEL is enabled, but I don't see this happening in 2.6.37, I
> was wondering how this is done in your tree.
>
ah, I think I figured this part - there is an assembler directive .arm
which overrides the command line specified mode (ARM vs THUMB)
cheers,
/v
^ permalink raw reply
* [PATCH 5/6] ARM: pm: convert samsung platforms to generic suspend/resume support
From: Russell King - ARM Linux @ 2011-02-17 23:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <01b001cbcef7$3e7f5f90$bb7e1eb0$%kim@samsung.com>
On Fri, Feb 18, 2011 at 08:05:57AM +0900, Kukjin Kim wrote:
> Russell King - ARM Linux wrote:
> >
> > On Thu, Feb 17, 2011 at 09:09:02PM +0900, Kukjin Kim wrote:
> > > Hi Russell,
> > >
> > > I tested on SMDKV210(S5PV210) and SMDKC110(S5PC110).
> >
> > Thanks for testing. It looks like I'm missing a load for r3 in the
> > s5pv210 code. The replacement patch below should resolve this.
> >
>
> Hooray, it works fine ;)
>
> Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Thanks. I'm assuming that applies to:
"ARM: pm: add generic CPU suspend/resume support"
too as you can't test this without that patch.
^ permalink raw reply
* [PATCH v9 0/7] nand prefetch-irq support and ecc layout chanage
From: Tony Lindgren @ 2011-02-17 23:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2A3DCF3DA181AD40BDE86A3150B27B6B036AB6B036@dbde02.ent.ti.com>
* Ghorai, Sukumar <s-ghorai@ti.com> [110203 11:35]:
>
> In this version I have addressed all inputs on previous versions.
> Please check if it's possible to push all theses in any of your testing
> branch!
Thanks, queuing for the upcoming merge window.
Regards,
Tony
^ permalink raw reply
* [PATCH 2/6] ARM: pm: add generic CPU suspend/resume support
From: Russell King - ARM Linux @ 2011-02-17 23:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTincWLyqdtAoS4gxvhGZGRdzRAiQ41Pn8QSG-id=@mail.gmail.com>
On Thu, Feb 17, 2011 at 12:05:59PM -0800, Colin Cross wrote:
> On Thu, Feb 17, 2011 at 2:41 AM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
> > I think that on resume you invalidate L1 in the reset vector before
> > jumping to cpu_resume, correct ?
>
> I manually invalidate the L1 Dcache, but not the Icache.
Well...
ARMv5 and older invalidates the L1 Dcache.
ARMv6 cleans and invalidates the L1 Dcache.
ARMv7 does nothing with the L1 Dcache.
That's rather inconsistent, but that's what people are doing with their
current suspend/resume paths. We really ought to have this well-defined.
I don't see any reason why there should be any dirty data in the Dcache,
so I think the safe thing we should be doing in every case is a L1 Dcache
invalidate on resume.
That's a separate change though.
^ permalink raw reply
* [PATCH 00/10] Fix CLCD framebuffer formats and consolidate ARM platform CLCD support
From: Russell King - ARM Linux @ 2011-02-17 23:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110127125714.GD25968@n2100.arm.linux.org.uk>
Any comments on this patch set?
On Thu, Jan 27, 2011 at 12:57:14PM +0000, Russell King - ARM Linux wrote:
> This patch series fixes the framebuffer formatting for the various
> CLCD colour modes - including those which the CLCD doesn't actually
> support.
>
> PL110 in TFT mode only supports 888 and 5551 connectivity. Some ARM
> platforms have additional muxing on their outputs which rewire this
> to allow the 5551 output to be used in 565 mode:
>
> FBMEM bit (RGB) 5551 565
> 0 R0 R0
> 1 R1 R1
> 2 R2 R2
> 3 R3 R3
> 4 R4 R4
> 5 G0 G0
> 6 G1 G1
> 7 G2 G2
> 8 G3 G3
> 9 G4 G4
> 10 B0 G5
> 11 B1 B0
> 12 B2 B1
> 13 B3 B2
> 14 B4 B3
> 15 I B4
>
> This means that when BGR mode is selected, it in green mapping to bits
> 0, 9, 8, 7, 6, 5 in the framebuffer, which is not sane. There appears
> to be no external MUX selection for this format.
>
> PL111 on the other hand supports 888, 5551, 565 and 444 natively, so it
> can support RGB and BGR pixel formats directly.
>
> Introduce a set of capabilities one bit for each format (RGB888, BGR888,
> RGB5551, BGR5551 etc) describing what formats the panel itself can support,
> and also what the board can support. These are combined, and from that
> we select the appropriate 16bpp pixel format which the panel and board can
> support. Where a panel and board combination supports multiple 16bpp
> formats, pick the closest format to the requested format.
>
> Implementations which do not supply the capabilities fall back to the old
> way of doing things, which is based on the cntl register to indicate
> whether we should be using RGB or BGR mode.
>
> This then allows us to unify the CLCD support across Integrator, Versatile,
> Realview and Versatile Express. This has been successfully tested on:
>
> Integrator/CP - RGB565, RGB5551, BGR5551.
> Versatile PB926 - RGB565, BGR565, RGB5551, BGR5551.
> Realview EB ARM11MPcore - RGB565, BGR565, RGB5551, BGR5551, RGB444, BGR444.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ARM: gic: use handle_fasteoi_irq for SPIs
From: Abhijeet Dharmapurikar @ 2011-02-17 23:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1102171831520.2701@localhost6.localdomain6>
>> Right, so to get back to the original discussion about how to handle
>> chained handlers if the high-level flow type of the IRQ chip is altered
>> it seems that there are two options:
>>
>> 1.) Update all of the chained handlers to use the new flow-control
>> 2.) Retain backwards compatibility if a chained handler decides to
>> use the old method of flow control (specifically, leave an ack
>> implementation in the GIC code after moving to fasteoi).
>>
>> Obviously, I'd rather go with option (2) and let platforms migrate
>> over time if they choose to. Now, given that the ack function is really
>> not something you want to do in a virtualised environment (because it
>> pokes the distributor), is it worth sticking a
>> WARN_ON_ONCE(cpu_has_virtualisation()); in the ack code?
>
> #2 is less painful and just works. The fasteoi stuff does not use ack
> IIRC so it wont hurt.
On an MSM we use handle_percpu_irq for PPIs, if we have ack and eoi we
will end up EOI ing the interrupt twice so #2 wont work. Also all the
cascaded handlers would have assumed that the ack function masks the
interrupt, it is best we fix all of them to use eoi at the end (just
like handle_fasteoi_irq). Please tell me how you guys locate such
cascaded handlers?
Sorry for my earlier patch - didnt realize that the chaging the ack will
break the chained handler. My board doesnt have cascaded gics. The only
chained handler I knew was gpio-v2.c and it does the correct thing of
calling an desc->chip->ack at the end.
BTW, I am all in favor of using handle_fasteoi_irq for shared PPIs , It
will fix a problem I pointed out here.
http://kerneltrap.org/mailarchive/linux-kernel/2010/12/30/4664338
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply
* [PATCH v5 3/5] OMAP4: hwmod data: add mailbox data
From: Tony Lindgren @ 2011-02-17 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTi=yj2_bS1h87u0hhUUpA=RPZe-A=PiNSf_q_66r@mail.gmail.com>
* Ramirez Luna, Omar <omar.ramirez@ti.com> [110215 16:11]:
>
> > If you have to do several platform_get_irq_byname to get this one, I'd
> > prefer to get rid of that name for OMAP4. It will make mailbox irq
> > consistent with the other hwmods.
>
> I was thinking to standardize the names to be mbox0..mboxN across all
> the platforms, reason being that the mailbox also has capabilities to
> be used not only by dsp or iva, by using a polling method.
>
> So even if the mailbox in OMAP3 is called "dsp", it has 4 more queues
> apart from the 2 used for messaging between arm and dsp, that could be
> used even if tidspbridge wasn't there.
So what's the status of this series? Can the rest of the patches
now be applied on top of the current omap-for-linus or do the names
still need fixing?
Tony
^ permalink raw reply
* [PATCH 4/4] mtd: OneNAND: OMAP2: increase multiblock erase verify timeout
From: Tony Lindgren @ 2011-02-17 23:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297068421-14430-5-git-send-email-adrian.hunter@nokia.com>
* Adrian Hunter <adrian.hunter@nokia.com> [110207 00:45]:
> From: Roman Tereshonkov <roman.tereshonkov@nokia.com>
>
> The current multiblock erase verify read timeout 100us is the maximum
> for none-error case. If errors happen during multibock erase then
> the specification recommends to run multiblock erase verify command
> with maximum timeout 10ms (see specs. for KFM4G16Q2A and KFN8G16Q2A).
>
> For the most common non-error case we wait 100us in udelay polling
> loop. In case of timeout the interrupt mode is used to wait for the
> command end.
>
> Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
I'll queue this series. Anybody from MTD list care to ack this patch?
Regards,
Tony
> ---
> drivers/mtd/onenand/omap2.c | 8 +++-----
> 1 files changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
> index 3e1bb95..ec26399 100644
> --- a/drivers/mtd/onenand/omap2.c
> +++ b/drivers/mtd/onenand/omap2.c
> @@ -148,11 +148,9 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
> wait_err("controller error", state, ctrl, intr);
> return -EIO;
> }
> - if ((intr & intr_flags) != intr_flags) {
> - wait_err("timeout", state, ctrl, intr);
> - return -EIO;
> - }
> - return 0;
> + if ((intr & intr_flags) == intr_flags)
> + return 0;
> + /* Continue in wait for interrupt branch */
> }
>
> if (state != FL_READING) {
> --
> 1.7.0.4
>
^ permalink raw reply
* [PATCH 5/6] ARM: pm: convert samsung platforms to generic suspend/resume support
From: Kukjin Kim @ 2011-02-17 23:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217232947.GA4110@n2100.arm.linux.org.uk>
Russell King - ARM Linux wrote:
>
> On Fri, Feb 18, 2011 at 08:05:57AM +0900, Kukjin Kim wrote:
> > Russell King - ARM Linux wrote:
> > >
> > > On Thu, Feb 17, 2011 at 09:09:02PM +0900, Kukjin Kim wrote:
> > > > Hi Russell,
> > > >
> > > > I tested on SMDKV210(S5PV210) and SMDKC110(S5PC110).
> > >
> > > Thanks for testing. It looks like I'm missing a load for r3 in the
> > > s5pv210 code. The replacement patch below should resolve this.
> > >
> >
> > Hooray, it works fine ;)
> >
> > Tested-by: Kukjin Kim <kgene.kim@samsung.com>
>
> Thanks. I'm assuming that applies to:
>
> "ARM: pm: add generic CPU suspend/resume support"
>
> too as you can't test this without that patch.
Yeah, it's ok to me :)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply
* [PATCH v2] OMAP: IOMMU: add missing function declaration
From: Tony Lindgren @ 2011-02-17 23:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110215.150904.31489671848521371.Hiroshi.DOYU@nokia.com>
* Hiroshi DOYU <Hiroshi.DOYU@nokia.com> [110215 05:07]:
> From: David Cohen <dacohen@gmail.com>
> Subject: [PATCH v2] OMAP: IOMMU: add missing function declaration
> Date: Tue, 15 Feb 2011 13:31:13 +0200
>
> > Declaration of exported function 'iopgtable_lookup_entry' is missing from
> > header file. Currently we have a sparse warning as it's not being used
> > externally. Adding its declaration to avoid such warning and allow its usage
> > in future.
> >
> > Signed-off-by: David Cohen <dacohen@gmail.com>
> > ---
> > arch/arm/plat-omap/include/plat/iommu.h | 2 ++
> > 1 files changed, 2 insertions(+), 0 deletions(-)
>
> Thanks. Tony, Please put this into your queue.
Adding to devel-cleanup for the upcoming merge window.
Tony
^ permalink raw reply
* [PATCH v2 0/2] Fix/Clean regulator consumer mapping for 3430sdp
From: Tony Lindgren @ 2011-02-17 23:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1296737122-20765-1-git-send-email-rnayak@ti.com>
* Rajendra Nayak <rnayak@ti.com> [110203 04:44]:
> This is a short series to fix some, and clean the
> existing regulator consumer supply mappings for
> the OMAP3430sdp board.
>
> The series is boot tested on the 3430sdp board
> and applies on 2.6.38-rc3.
Adding these to devel-board for the upcoming merge window.
Tony
^ permalink raw reply
* [PATCH] OMAP2: add regulator for MMC1
From: Tony Lindgren @ 2011-02-17 23:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AANLkTinGOQ6-FmVG=LbQHjYPZ_tm3yDtVdDLx7EqhHpw@mail.gmail.com>
* Kishore Kadiyala <kishorek.kadiyala@gmail.com> [110208 12:55]:
> On Mon, Feb 7, 2011 at 9:38 PM, Balaji T K <balajitk@ti.com> wrote:
> > Add regulator VMMC1 used by SD/MMC card slot1 in 2430sdp.
> >
> > Signed-off-by: Balaji T K <balajitk@ti.com>
>
> Tested-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Thanks adding.
Tony
^ permalink raw reply
* [PATCH] omap iommu: print module name on error messages
From: Tony Lindgren @ 2011-02-17 23:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110214.154130.1019130951550611673.Hiroshi.DOYU@nokia.com>
* Hiroshi DOYU <Hiroshi.DOYU@nokia.com> [110214 05:39]:
> From: ext David Cohen <dacohen@gmail.com>
> Subject: [PATCH] omap iommu: print module name on error messages
> Date: Sat, 12 Feb 2011 12:02:29 +0200
>
> > OMAP IOMMU generic layer doesn't need ot print function name during
> > error messages. Print module name instead which is more useful.
>
> Agree. This makes more sense.
Applying to devel-iommu-mailbox for the upcoming merge window.
Tony
^ permalink raw reply
* SAMSUNG: any example code for soc_camera, tv output, etc...?
From: Nick Pelling @ 2011-02-17 23:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <01b001cbcef7$3e7f5f90$bb7e1eb0$%kim@samsung.com>
Hi everyone,
I've just gone through a lot of Samsung platform setup files in
arch/arm/ , but haven't yet found any Samsung-SoC-based boards
pre-plumbed into V4L2, nor any that connect up to a TV out (rather
than to an LCD screen). Is there a repository out there containing
Samsung Linux source code for these kinds of useful things, or even
brief documentation on how to do this kind of basic video plumbing?
Even though I'm working on the S5PC100, information about hooking
sensors into other Samsung SoC platforms would probably be
sufficient. Alternatively, please say if you know which specific
file(s) I should be asking Samsung tech support for under NDA (via my
distributor's tech support).
Thanks, ....Nick Pelling.... // Nanodome Ltd
^ permalink raw reply
* [PATCH 0/2] omap3: minor clean-up in flash related code
From: Tony Lindgren @ 2011-02-17 23:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297767452-22554-1-git-send-email-premi@ti.com>
* Sanjeev Premi <premi@ti.com> [110215 02:56]:
> Changes include:
> - fixing typos
> - using pr_err() instead of printk
Thanks, applying to devel-cleanup for the upcoming merge window.
Tony
^ permalink raw reply
* [RESEND][PATCH] ARM: OMAP: Add chip id recognition for OMAP4 ES2.1 and ES2.2
From: Tony Lindgren @ 2011-02-18 0:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110214230750.GR20795@atomide.com>
* Tony Lindgren <tony@atomide.com> [110214 15:06]:
> * Nishant Kamat <nskamat@ti.com> [110214 07:53]:
> > Hi Tony,
> >
> > There have been no comments on this patch but an Ack from Santosh.
> > Would you please accept/merge this, or do you have any comments?
>
> Thanks will queue. Next time, please also Cc linux-arm-kernel mailing
> list for your arch/arm/*omap*/ related patches.
Here's repost of this with linux-arm-kernel Cc'd.
Regards,
Tony
From: Nishant Kamat <nskamat@ti.com>
Date: Thu, 17 Feb 2011 09:55:03 -0800
Subject: [PATCH] omap: Add chip id recognition for OMAP4 ES2.1 and ES2.2
Allow OMAP4 ES2.1 and ES2.2 revisions to be recognized in the
omap4_check_revision() function.
Mainly, ES2.1 has fixes that allow LPDDR to be used at 100% OPP (400MHz).
ES2.2 additionally has a couple of power management fixes (to reduce
leakage), an I2C1 SDA line state fix, and a floating point write
corruption fix (cortex erratum).
Even though the current mainline support doesn't need to distinguish
between ES2.X versions, it's still useful to know the correct silicon
rev when issues are reported. Moreover, these id checks can be used by
power management code that selects suitable OPPs considering the
memory speed limitation on ES2.0.
For details about the silicon errata on OMAP4430, refer
http://focus.ti.com/pdfs/wtbu/SWPZ009A_OMAP4430_Errata_Public_vA.pdf
Signed-off-by: Nishant Kamat <nskamat@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5c25f1b..3168b17 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-11 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
- rev = (idcode >> 28) & 0xff;
+ rev = (idcode >> 28) & 0xf;
/*
* Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP4430ES1;
break;
case 1:
+ default:
omap_revision = OMAP4430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+ }
+ break;
+ case 0xb95c:
+ switch (rev) {
+ case 3:
+ omap_revision = OMAP4430_REV_ES2_1;
+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
break;
+ case 4:
default:
- omap_revision = OMAP4430_REV_ES2_0;
- omap_chip.oc |= CHIP_IS_OMAP4430ES2;
- }
- break;
+ omap_revision = OMAP4430_REV_ES2_2;
+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
+ }
+ break;
default:
- /* Unknown default to latest silicon rev as default*/
- omap_revision = OMAP4430_REV_ES2_0;
- omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+ /* Unknown default to latest silicon rev as default */
+ omap_revision = OMAP4430_REV_ES2_2;
+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
- pr_info("OMAP%04x ES%d.0\n",
- omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
+ pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
+ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
}
#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index be99438..8198bb6 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
*
* Copyright (C) 2004, 2008 Nokia Corporation
*
- * Copyright (C) 2009 Texas Instruments.
+ * Copyright (C) 2009-11 Texas Instruments.
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
@@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517)
#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
#define OMAP443X_CLASS 0x44300044
-#define OMAP4430_REV_ES1_0 OMAP443X_CLASS
-#define OMAP4430_REV_ES2_0 0x44301044
+#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
/*
* omap_chip bits
@@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
#define CHIP_IS_OMAP4430ES2 (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
#define CHIP_IS_TI816X (1 << 14)
#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
- CHIP_IS_OMAP4430ES2)
+#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
+ CHIP_IS_OMAP4430ES2 | \
+ CHIP_IS_OMAP4430ES2_1 | \
+ CHIP_IS_OMAP4430ES2_2)
/*
* "GE" here represents "greater than or equal to" in terms of ES
^ permalink raw reply related
* [PATCH v5 3/5] OMAP4: hwmod data: add mailbox data
From: Ramirez Luna, Omar @ 2011-02-18 0:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20110217233908.GG20795@atomide.com>
Hi Tony,
On Thu, Feb 17, 2011 at 5:39 PM, Tony Lindgren <tony@atomide.com> wrote:
> * Ramirez Luna, Omar <omar.ramirez@ti.com> [110215 16:11]:
>>
>> > If you have to do several platform_get_irq_byname to get this one, I'd
>> > prefer to get rid of that name for OMAP4. It will make mailbox irq
>> > consistent with the other hwmods.
>>
>> I was thinking to standardize the names to be mbox0..mboxN across all
>> the platforms, reason being that the mailbox also has capabilities to
>> be used not only by dsp or iva, by using a polling method.
>>
>> So even if the mailbox in OMAP3 is called "dsp", it has 4 more queues
>> apart from the 2 used for messaging between arm and dsp, that could be
>> used even if tidspbridge wasn't there.
>
> So what's the status of this series? Can the rest of the patches
> now be applied on top of the current omap-for-linus or do the names
> still need fixing?
I'm going to remove the names for the hwmods with a single irq. And
change the interface clock to be the main_clk, so it can be disabled
when runtime pm is disabled.
I won't resend the patch for OMAP4 hwmod data, as this was send
earlier by Benoit.
Regards,
Omar
^ permalink raw reply
* [PATCH] msm: add single-wire serial bus interface (SSBI) driver
From: Kenneth Heitke @ 2011-02-18 0:34 UTC (permalink / raw)
To: linux-arm-kernel
SSBI is the Qualcomm single-wire serial bus interface used to connect
the MSM devices to the PMIC and other devices.
Since SSBI only supports a single slave, the driver gets the name of the
slave device passed in from the board file through the master device's
platform data.
SSBI registers pretty early (postcore), so that the PMIC can come up
before the board init. This is useful if the board init requires the
use of gpios that are connected through the PMIC.
Based on a patch by Dima Zavin <dima@android.com> that can be found at:
http://android.git.kernel.org/?p=kernel/msm.git;a=commitdiff;h=eb060bac4
This patch adds PMIC Arbiter support for the MSM8660. The PMIC Arbiter
is a hardware wrapper around the SSBI 2.0 controller that is designed to
overcome concurrency issues and security limitations. A controller_type
field is added to the platform data to specify the type of the SSBI
controller (1.0, 2.0, or PMIC Arbiter).
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
---
arch/arm/mach-msm/Kconfig | 16 ++
arch/arm/mach-msm/Makefile | 1 +
arch/arm/mach-msm/include/mach/msm_ssbi.h | 38 +++
arch/arm/mach-msm/ssbi.c | 376 +++++++++++++++++++++++++++++
4 files changed, 431 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-msm/include/mach/msm_ssbi.h
create mode 100644 arch/arm/mach-msm/ssbi.c
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 997c5bd..f35c3d9 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -24,6 +24,7 @@ config ARCH_MSM7X30
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
+ select HAS_MSM_SSBI
config ARCH_QSD8X50
bool "QSD8X50"
@@ -46,6 +47,7 @@ config ARCH_MSM8X60
select MSM_V2_TLMM
select MSM_GPIOMUX
select MSM_SCM if SMP
+ select HAS_MSM_SSBI
config ARCH_MSM8960
bool "MSM8960"
@@ -56,6 +58,7 @@ config ARCH_MSM8960
select MSM_V2_TLMM
select MSM_GPIOMUX
select MSM_SCM if SMP
+ select HAS_MSM_SSBI
endchoice
@@ -190,6 +193,16 @@ choice
endchoice
endif
+config MSM_SSBI
+ bool "Qualcomm Single-wire Serial Bus Interface (SSBI)"
+ depends on HAS_MSM_SSBI
+ help
+ If you say yes to this option, support will be included for the
+ built-in SSBI interface on Qualcomm MSM family processors.
+
+ This is required for communicating with Qualcomm PMICs and
+ other devices that have the SSBI interface.
+
config MSM_SMD_PKG3
bool
@@ -210,4 +223,7 @@ config IOMMU_API
config MSM_SCM
bool
+
+config HAS_MSM_SSBI
+ bool
endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 2099c97..94d46ff 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+obj-$(CONFIG_MSM_SSBI) += ssbi.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
diff --git a/arch/arm/mach-msm/include/mach/msm_ssbi.h b/arch/arm/mach-msm/include/mach/msm_ssbi.h
new file mode 100644
index 0000000..d0ed277
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_ssbi.h
@@ -0,0 +1,38 @@
+/* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ * Author: Dima Zavin <dima@android.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_MSM_SSBI_H
+#define __ARCH_ARM_MACH_MSM_SSBI_H
+
+#include <linux/types.h>
+
+struct msm_ssbi_slave_info {
+ const char *name;
+ void *platform_data;
+};
+
+enum msm_ssbi_controller_type {
+ MSM_SBI_CTRL_SSBI = 0,
+ MSM_SBI_CTRL_SSBI2,
+ MSM_SBI_CTRL_PMIC_ARBITER,
+};
+
+struct msm_ssbi_platform_data {
+ struct msm_ssbi_slave_info slave;
+ enum msm_ssbi_controller_type controller_type;
+};
+
+int msm_ssbi_write(struct device *dev, u16 addr, u8 *buf, int len);
+int msm_ssbi_read(struct device *dev, u16 addr, u8 *buf, int len);
+#endif
diff --git a/arch/arm/mach-msm/ssbi.c b/arch/arm/mach-msm/ssbi.c
new file mode 100644
index 0000000..1de4faf
--- /dev/null
+++ b/arch/arm/mach-msm/ssbi.c
@@ -0,0 +1,376 @@
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010, Google Inc.
+ *
+ * Original authors: Code Aurura Forum
+ *
+ * Author: Dima Zavin <dima@android.com>
+ * - Largely rewritten from original to not be an i2c driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <mach/msm_ssbi.h>
+
+/* SSBI 2.0 controller registers */
+#define SSBI2_CMD 0x0008
+#define SSBI2_RD 0x0010
+#define SSBI2_STATUS 0x0014
+#define SSBI2_MODE2 0x001C
+
+/* SSBI_CMD fields */
+#define SSBI_CMD_RDWRN (1 << 24)
+
+/* SSBI_STATUS fields */
+#define SSBI_STATUS_RD_READY (1 << 2)
+#define SSBI_STATUS_READY (1 << 1)
+#define SSBI_STATUS_MCHN_BUSY (1 << 0)
+
+/* SSBI_MODE2 fields */
+#define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
+#define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
+
+#define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
+ (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
+ SSBI_MODE2_REG_ADDR_15_8_MASK))
+
+/* SSBI PMIC Arbiter command registers */
+#define SSBI_PA_CMD 0x0000
+#define SSBI_PA_RD_STATUS 0x0004
+
+/* SSBI_PA_CMD fields */
+#define SSBI_PA_CMD_RDWRN (1 << 24)
+
+/* SSBI_PA_RD_STATUS fields */
+#define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
+#define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
+
+#define SSBI_TIMEOUT_US 100
+
+struct msm_ssbi {
+ struct device *dev;
+ struct device *slave;
+ void __iomem *base;
+ spinlock_t lock;
+ enum msm_ssbi_controller_type controller_type;
+ int (*read)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
+ int (*write)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
+};
+
+#define to_msm_ssbi(dev) platform_get_drvdata(to_platform_device(dev))
+
+static inline u32 ssbi_readl(struct msm_ssbi *ssbi, u32 reg)
+{
+ return readl(ssbi->base + reg);
+}
+
+static inline void ssbi_writel(struct msm_ssbi *ssbi, u32 val, u32 reg)
+{
+ writel(val, ssbi->base + reg);
+}
+
+static int ssbi_wait_mask(struct msm_ssbi *ssbi, u32 set_mask, u32 clr_mask)
+{
+ u32 timeout = SSBI_TIMEOUT_US;
+ u32 val;
+
+ while (timeout--) {
+ val = ssbi_readl(ssbi, SSBI2_STATUS);
+ if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
+ return 0;
+ udelay(1);
+ }
+
+ dev_err(ssbi->dev, "%s: timeout (status %x set_mask %x clr_mask %x)\n",
+ __func__, ssbi_readl(ssbi, SSBI2_STATUS), set_mask, clr_mask);
+ return -ETIMEDOUT;
+}
+
+static int
+msm_ssbi_read_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
+{
+ u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
+ int ret = 0;
+
+ if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
+ u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
+ mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
+ ssbi_writel(ssbi, mode2, SSBI2_MODE2);
+ }
+
+ while (len) {
+ ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
+ if (ret)
+ goto err;
+
+ ssbi_writel(ssbi, cmd, SSBI2_CMD);
+ ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
+ if (ret)
+ goto err;
+ *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
+ len--;
+ }
+
+err:
+ return ret;
+}
+
+static int
+msm_ssbi_write_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
+{
+ int ret = 0;
+
+ if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
+ u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
+ mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
+ ssbi_writel(ssbi, mode2, SSBI2_MODE2);
+ }
+
+ while (len) {
+ ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
+ if (ret)
+ goto err;
+
+ ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
+ ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
+ if (ret)
+ goto err;
+ buf++;
+ len--;
+ }
+
+err:
+ return ret;
+}
+
+static inline int
+msm_ssbi_pa_transfer(struct msm_ssbi *ssbi, u32 cmd, u8 *data)
+{
+ u32 timeout = SSBI_TIMEOUT_US;
+ u32 rd_status;
+
+ ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
+
+ while (timeout--) {
+ rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
+
+ if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED) {
+ dev_err(ssbi->dev, "%s: transaction denied (0x%x)\n",
+ __func__, rd_status);
+ return -EPERM;
+ }
+
+ if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
+ if (data)
+ *data = rd_status & 0xff;
+ return 0;
+ }
+ udelay(1);
+ }
+
+ dev_err(ssbi->dev, "%s: timeout, status 0x%x\n", __func__, rd_status);
+ return -ETIMEDOUT;
+}
+
+static int
+msm_ssbi_pa_read_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
+{
+ u32 cmd;
+ int ret = 0;
+
+ cmd = SSBI_PA_CMD_RDWRN | (addr & 0x3fff) << 8;
+
+ while (len) {
+ ret = msm_ssbi_pa_transfer(ssbi, cmd, buf);
+ if (ret)
+ goto err;
+ buf++;
+ len--;
+ }
+
+err:
+ return ret;
+}
+
+static int
+msm_ssbi_pa_write_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
+{
+ u32 cmd;
+ int ret = 0;
+
+ while (len) {
+ cmd = (addr & 0x3fff) << 8 | *buf;
+ ret = msm_ssbi_pa_transfer(ssbi, cmd, NULL);
+ if (ret)
+ goto err;
+ buf++;
+ len--;
+ }
+
+err:
+ return ret;
+}
+
+int msm_ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
+{
+ struct msm_ssbi *ssbi = to_msm_ssbi(dev);
+ unsigned long flags;
+ int ret;
+
+ BUG_ON(ssbi->dev != dev);
+
+ spin_lock_irqsave(&ssbi->lock, flags);
+ ret = ssbi->read(ssbi, addr, buf, len);
+ spin_unlock_irqrestore(&ssbi->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(msm_ssbi_read);
+
+int msm_ssbi_write(struct device *dev, u16 addr, u8 *buf, int len)
+{
+ struct msm_ssbi *ssbi = to_msm_ssbi(dev);
+ unsigned long flags;
+ int ret;
+
+ BUG_ON(ssbi->dev != dev);
+
+ spin_lock_irqsave(&ssbi->lock, flags);
+ ret = ssbi->write(ssbi, addr, buf, len);
+ spin_unlock_irqrestore(&ssbi->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(msm_ssbi_write);
+
+static int __init msm_ssbi_add_slave(struct msm_ssbi *ssbi,
+ const struct msm_ssbi_slave_info *slave)
+{
+ struct platform_device *slave_pdev;
+ int ret;
+
+ if (ssbi->slave) {
+ pr_err("%s: slave already attached??\n", __func__);
+ return -EBUSY;
+ }
+
+ slave_pdev = platform_device_alloc(slave->name, -1);
+ if (!slave_pdev) {
+ pr_err("%s: cannot allocate pdev for slave '%s'", __func__,
+ slave->name);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ slave_pdev->dev.parent = ssbi->dev;
+ slave_pdev->dev.platform_data = slave->platform_data;
+
+ ret = platform_device_add(slave_pdev);
+ if (ret) {
+ pr_err("%s: cannot add slave platform device for '%s'\n",
+ __func__, slave->name);
+ goto err;
+ }
+
+ ssbi->slave = &slave_pdev->dev;
+ return 0;
+
+err:
+ if (slave_pdev)
+ platform_device_put(slave_pdev);
+ return ret;
+}
+
+static int __init msm_ssbi_probe(struct platform_device *pdev)
+{
+ const struct msm_ssbi_platform_data *pdata = pdev->dev.platform_data;
+ struct resource *mem_res;
+ struct msm_ssbi *ssbi;
+ int ret = 0;
+
+ printk(KERN_INFO "%s: %s\n", __func__, pdata->slave.name);
+
+ if (!pdata) {
+ pr_err("%s: missing platform data\n", __func__);
+ return -EINVAL;
+ }
+
+ ssbi = kzalloc(sizeof(struct msm_ssbi), GFP_KERNEL);
+ if (!ssbi) {
+ pr_err("%s: cannot allocate ssbi_data\n", __func__);
+ return -ENOMEM;
+ }
+
+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem_res) {
+ pr_err("%s: missing mem resource\n", __func__);
+ ret = -EINVAL;
+ goto err_get_mem_res;
+ }
+
+ ssbi->base = ioremap(mem_res->start, resource_size(mem_res));
+ if (!ssbi->base) {
+ pr_err("%s: ioremap of 0x%p failed\n", __func__,
+ (void *)mem_res->start);
+ ret = -EINVAL;
+ goto err_ioremap;
+ }
+ ssbi->dev = &pdev->dev;
+ platform_set_drvdata(pdev, ssbi);
+
+ ssbi->controller_type = pdata->controller_type;
+ if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
+ ssbi->read = msm_ssbi_pa_read_bytes;
+ ssbi->write = msm_ssbi_pa_write_bytes;
+ } else {
+ ssbi->read = msm_ssbi_read_bytes;
+ ssbi->write = msm_ssbi_write_bytes;
+ }
+
+ spin_lock_init(&ssbi->lock);
+
+ ret = msm_ssbi_add_slave(ssbi, &pdata->slave);
+ if (ret)
+ goto err_ssbi_add_slave;
+
+ return 0;
+
+err_ssbi_add_slave:
+ platform_set_drvdata(pdev, NULL);
+ iounmap(ssbi->base);
+err_ioremap:
+err_get_mem_res:
+ kfree(ssbi);
+ return ret;
+}
+
+static struct platform_driver msm_ssbi_driver = {
+ .probe = msm_ssbi_probe,
+ .driver = {
+ .name = "msm_ssbi",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init msm_ssbi_init(void)
+{
+ return platform_driver_register(&msm_ssbi_driver);
+}
+postcore_initcall(msm_ssbi_init);
+
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:msm_ssbi");
+MODULE_AUTHOR("Dima Zavin <dima@android.com>");
--
1.7.3.3
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related
* [PATCH] msm: add single-wire serial bus interface (SSBI) driver
From: Daniel Walker @ 2011-02-18 0:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1297989299-27320-1-git-send-email-kheitke@codeaurora.org>
On Thu, 2011-02-17 at 17:34 -0700, Kenneth Heitke wrote:
> SSBI is the Qualcomm single-wire serial bus interface used to connect
> the MSM devices to the PMIC and other devices.
>
> Since SSBI only supports a single slave, the driver gets the name of the
> slave device passed in from the board file through the master device's
> platform data.
>
> SSBI registers pretty early (postcore), so that the PMIC can come up
> before the board init. This is useful if the board init requires the
> use of gpios that are connected through the PMIC.
>
> Based on a patch by Dima Zavin <dima@android.com> that can be found at:
> http://android.git.kernel.org/?p=kernel/msm.git;a=commitdiff;h=eb060bac4
>
> This patch adds PMIC Arbiter support for the MSM8660. The PMIC Arbiter
> is a hardware wrapper around the SSBI 2.0 controller that is designed to
> overcome concurrency issues and security limitations. A controller_type
> field is added to the platform data to specify the type of the SSBI
> controller (1.0, 2.0, or PMIC Arbiter).
>
> Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
> ---
> arch/arm/mach-msm/Kconfig | 16 ++
> arch/arm/mach-msm/Makefile | 1 +
> arch/arm/mach-msm/include/mach/msm_ssbi.h | 38 +++
> arch/arm/mach-msm/ssbi.c | 376 +++++++++++++++++++++++++++++
> 4 files changed, 431 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-msm/include/mach/msm_ssbi.h
> create mode 100644 arch/arm/mach-msm/ssbi.c
>
> diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
> index 997c5bd..f35c3d9 100644
> --- a/arch/arm/mach-msm/Kconfig
> +++ b/arch/arm/mach-msm/Kconfig
> @@ -24,6 +24,7 @@ config ARCH_MSM7X30
> select MSM_GPIOMUX
> select MSM_PROC_COMM
> select HAS_MSM_DEBUG_UART_PHYS
> + select HAS_MSM_SSBI
>
> config ARCH_QSD8X50
> bool "QSD8X50"
> @@ -46,6 +47,7 @@ config ARCH_MSM8X60
> select MSM_V2_TLMM
> select MSM_GPIOMUX
> select MSM_SCM if SMP
> + select HAS_MSM_SSBI
>
> config ARCH_MSM8960
> bool "MSM8960"
> @@ -56,6 +58,7 @@ config ARCH_MSM8960
> select MSM_V2_TLMM
> select MSM_GPIOMUX
> select MSM_SCM if SMP
> + select HAS_MSM_SSBI
>
> endchoice
>
> @@ -190,6 +193,16 @@ choice
> endchoice
> endif
>
> +config MSM_SSBI
> + bool "Qualcomm Single-wire Serial Bus Interface (SSBI)"
> + depends on HAS_MSM_SSBI
> + help
> + If you say yes to this option, support will be included for the
> + built-in SSBI interface on Qualcomm MSM family processors.
> +
> + This is required for communicating with Qualcomm PMICs and
> + other devices that have the SSBI interface.
> +
Can you put this in drivers/ this doesn't looks like it need to be here.
Daniel
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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