* [PATCH 1/7] ARM: tegra: cpuidle: separate cpuidle driver for different chips
From: Joseph Lo @ 2012-10-11 6:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5074A3C3.1080006@wwwdotorg.org>
On Wed, 2012-10-10 at 06:22 +0800, Stephen Warren wrote:
> On 10/08/2012 04:26 AM, Joseph Lo wrote:
> > The different Tegra chips may have different CPU idle states and data.
> > Individual CPU idle driver make it more easy to maintain.
>
> > diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
> > similarity index 72%
> > copy from arch/arm/mach-tegra/cpuidle.c
> > copy to arch/arm/mach-tegra/cpuidle-tegra20.c
> > index 4e0b07c..e2fc26a 100644
> > --- a/arch/arm/mach-tegra/cpuidle.c
> > +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
> > @@ -1,24 +1,22 @@
> > /*
> > - * arch/arm/mach-tegra/cpuidle.c
> > + * CPU idle driver for Tegra20 CPUs
> > *
> > - * CPU idle driver for Tegra CPUs
> > - *
> > - * Copyright (c) 2010-2012, NVIDIA Corporation.
> > + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
> > * Copyright (c) 2011 Google, Inc.
> > * Author: Colin Cross <ccross@android.com>
> > * Gary King <gking@nvidia.com>
> > *
> > - * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
> > - *
> > - * This program is free software; you can redistribute it and/or modify
> > - * it under the terms of the GNU General Public License as published by
> > - * the Free Software Foundation; either version 2 of the License, or
> > - * (at your option) any later version.
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2, as published by the Free Software Foundation.
> > *
> > * This program is distributed in the hope that it will be useful, but WITHOUT
> > * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> > * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> > */
>
> While that is the correct (c) header for new work submitted upstream,
> given this file is existing, just renamed and tweaked a bit, I don't
> believe you want to be changing the (c) header at all. Same for
> cpuidle-tegra30.c.
OK. I would just remove this line.
- * arch/arm/mach-tegra/cpuidle.c
Thanks,
Joseph
^ permalink raw reply
* [PATCH 2/6] ARM: EXYNOS5: DT Support for SATA and SATA PHY
From: Vasanth Ananthan @ 2012-10-11 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121010163127.GA19433@quad.lixom.net>
Hi,
On Wed, Oct 10, 2012 at 10:01 PM, Olof Johansson <olof@lixom.net> wrote:
> Hi,
>
> On Wed, Oct 10, 2012 at 02:08:31PM +0530, Vasanth Ananthan wrote:
>
>> > > +
>> > > + sataphy at 70 {
>> >
>> > sata-phy would be a more conventional name.
>> >
>> > > + compatible = "samsung,i2c-phy";
>> >
>> > i2c-phy? Seems like an odd choice of name. What is this device?
>> >
>>
>> The SATA physical layer controller is both a platform device and a i2c
>> slave device.
>> This compatible string is for the i2c client driver. Hence I have used
>> i2c-phy here.
>
> Ok, but samsung,i2c-phy is much too generic. Maybe something like
> samsung,exynos5-sata-phy (and rename the MMIO-controlled phy controls
> to ...sata-phy-controller below).
>
I'll do so..
>
>> > > + };
>> > > +
>> > > + sata-phy at 12170000 {
>> > > + compatible = "samsung,exynos-sata-phy";
>> > > + reg = <0x12170000 0x1ff>;
>> > > + };
>> >
>> > Should have binding too. How does this relate to the i2c device above.
>> >
>>
>> As mentioned earlier SATA physical layer controller is both a platform
>> device and also an i2c slave device.
>> This Node is for the SATA physical layer platform device, the previous node
>> is for i2c slave device.
>> Certain initialization settings done directly and other settings has to be
>> done through i2c.
>
> Wow, that's quite awkward. What needs to be done over i2c? I think I have
> seen use of SATA without touching the i2c side but it might have been for
> a simple setup.
40 bit Interface setting is done through i2c. Internal setting address
0x3A and data 0x0B.
>
>> > > +
>> > > i2c at 12C60000 {
>> > > compatible = "samsung,s3c2440-i2c";
>> > > reg = <0x12C60000 0x100>;
>> > > @@ -152,6 +164,13 @@
>> > > #size-cells = <0>;
>> > > };
>> > >
>> > > + i2c at 121D0000 {
>> > > + compatible = "samsung,s3c2440-sataphy-i2c";
>> >
>> > Is this a unique i2c controller, or is it just another one like the others
>> > on
>> > the chip? If it's the latter, it should use the regular compatible string.
>> >
>>
>> Yes, its a unique i2c controller which lacks an interrupt line while others
>> are interrupt driven.
>> Hence I have used a distinct compatible string for the driver to
>> distinguish the controller.
>
> It would be better to just make the i2c bus driver handle the case where there
> is no interrupt specifier and just use polling in those cases, especially if
> the rest of the device is identical and doesn't need special handling.
>
> As a matter of fact, if that had been done for the hdmi phy, then you could
> have done this patch without modifying the driver at all, just device tree
> contents. And the same would go for the next time down the road when
> a "special" i2c bus is added.
>
Yes, It is the i2c bus driver thats handles this case. There is a
subsequent patch
that provides the polling support to the driver. As far as I know, the
i2c controller for
HDMI PHY is also interrupt driven.
>
> -Olof
--
Regards,
Vasanth K A
^ permalink raw reply
* [RESEND PATCH 2/2] mmc: mmci: Switching off HWFC for SDIO depends on MCLK
From: Johan Rudholm @ 2012-10-11 6:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbWVLJKroUgX_kSO4Mwgxfhe3gZO9701xmpDuQJKx7sOQ@mail.gmail.com>
2012/10/10 Linus Walleij <linus.walleij@linaro.org>:
> On Wed, Oct 10, 2012 at 6:03 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
>
>> From: Ulf Hansson <ulf.hansson@linaro.org>
>>
>> For writes, HWFC shall be switched off when transfer size <= 8
>> bytes and when MCLK rate is above 50 MHz. For 50MHz and below
>> it shall be switched off when transfer size < 8 bytes.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Johan Rudholm <johan.rudholm@stericsson.com>
^ permalink raw reply
* [RESEND PATCH 1/2] mmc: mmci: Fix incorrect handling of HW flow control for SDIO
From: Johan Rudholm @ 2012-10-11 6:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYarGEzYoJwHggQh2O=hw_wyhP9KQ2GRruWh64SwnH=VA@mail.gmail.com>
2012/10/10 Linus Walleij <linus.walleij@linaro.org>:
> On Wed, Oct 10, 2012 at 6:03 PM, Ulf Hansson <ulf.hansson@stericsson.com> wrote:
>
>> From: Ulf Hansson <ulf.hansson@linaro.org>
>>
>> For data writes <= 8 bytes, HW flow control was disabled but
>> never re-enabled when the transfer was completed. This meant
>> that a following read request would give buffer overrun errors.
>>
>> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> Looks correct to me:
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Johan Rudholm <johan.rudholm@stericsson.com>
^ permalink raw reply
* [PATCH 2/7] ARM: tegra: cpuidle: add LP2 resume function
From: Joseph Lo @ 2012-10-11 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5074A559.8030206@wwwdotorg.org>
On Wed, 2012-10-10 at 06:29 +0800, Stephen Warren wrote:
> On 10/08/2012 04:26 AM, Joseph Lo wrote:
> > LP2 is one of the Tegra low power states that supports power gating both
> > CPU cores and GICs. Adding a resume function for taking care the CPUs that
> > resume from LP2. This function was been hooked to reset handler. We take
> > care everything here before go into kernel.
>
> > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
>
> > +ENTRY(tegra_resume)
> ...
> > + /* Are we on Tegra20? */
> > + mov32 r6, TEGRA_APB_MISC_BASE
> > + ldr r0, [r6, #APB_MISC_GP_HIDREV]
> > + and r0, r0, #0xff00
> > + cmp r0, #(0x20 << 8)
> > + beq 1f
> > +#ifdef CONFIG_ARCH_TEGRA_3x_SOC
> > + /* Clear the flow controller flags for this CPU. */
> > + mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR
> > + ldr r1, [r2]
> > + /* Clear event & intr flag */
> > + orr r1, r1, \
> > + #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
> > + movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps
> > + bic r1, r1, r0
> > + str r1, [r2]
> > +#endif
> > +1:
>
> couldn't that entire quoted chunk go inside the ifdef; all of reading
> the HIDREV register and the 1: label?
Ah. Yes, it's OK. Will do.
Thanks,
Joseph
^ permalink raw reply
* [RFC PATCH] ARM: vt8500: Convert arch-vt8500 to multiplatform
From: Tony Prisk @ 2012-10-11 7:17 UTC (permalink / raw)
To: linux-arm-kernel
This patch completes the conversion to ARCH_MULTI_V5 for arch-vt8500.
Removed /mach/include/ and remaining unneeded files.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
arch/arm/Kconfig | 18 ++----------
arch/arm/mach-vt8500/include/mach/debug-macro.S | 31 -------------------
arch/arm/mach-vt8500/include/mach/timex.h | 26 ----------------
arch/arm/mach-vt8500/include/mach/uncompress.h | 36 -----------------------
4 files changed, 2 insertions(+), 109 deletions(-)
delete mode 100644 arch/arm/mach-vt8500/include/mach/debug-macro.S
delete mode 100644 arch/arm/mach-vt8500/include/mach/timex.h
delete mode 100644 arch/arm/mach-vt8500/include/mach/uncompress.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 32b62ac..e71ad2c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -938,22 +938,6 @@ config PLAT_SPEAR
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-config ARCH_VT8500
- bool "VIA/WonderMedia 85xx"
- select CPU_ARM926T
- select GENERIC_GPIO
- select ARCH_HAS_CPUFREQ
- select GENERIC_CLOCKEVENTS
- select ARCH_REQUIRE_GPIOLIB
- select USE_OF
- select COMMON_CLK
- select HAVE_CLK
- select CLKDEV_LOOKUP
- select MULTI_IRQ_HANDLER
- select SPARSE_IRQ
- help
- Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
-
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform"
select CPU_V7
@@ -1125,6 +1109,8 @@ source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
+source "arch/arm/mach-vt8500/Kconfig"
+
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/mach-vt8500/include/mach/debug-macro.S
deleted file mode 100644
index ca292f2..0000000
--- a/arch/arm/mach-vt8500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/debug-macro.S
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Debugging macro include header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
- .macro addruart, rp, rv, tmp
- mov \rp, #0x00200000
- orr \rv, \rp, #0xf8000000
- orr \rp, \rp, #0xd8000000
- .endm
-
- .macro senduart,rd,rx
- strb \rd, [\rx, #0]
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x1c]
- ands \rd, \rd, #0x2
- bne 1001b
- .endm
-
- .macro waituart,rd,rx
- .endm
diff --git a/arch/arm/mach-vt8500/include/mach/timex.h b/arch/arm/mach-vt8500/include/mach/timex.h
deleted file mode 100644
index 8487e4c..0000000
--- a/arch/arm/mach-vt8500/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/timex.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef MACH_TIMEX_H
-#define MACH_TIMEX_H
-
-#define CLOCK_TICK_RATE (3000000)
-
-#endif /* MACH_TIMEX_H */
diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h
deleted file mode 100644
index a9b6cae..0000000
--- a/arch/arm/mach-vt8500/include/mach/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-vt8500/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Based on arch/arm/mach-dove/include/mach/uncompress.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#define UART0_PHYS 0xd8200000
-#define UART0_ADDR(x) *(volatile unsigned char *)(UART0_PHYS + x)
-
-static void putc(const char c)
-{
- while (UART0_ADDR(0x1c) & 0x2)
- /* Tx busy, wait and poll */;
-
- UART0_ADDR(0) = c;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
--
1.7.9.5
^ permalink raw reply related
* ARM_ATAG_DTB_COMPAT fails on fdt_ro.c compiling
From: Shawn Guo @ 2012-10-11 7:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5BgJ0eSPvhnjCx_DVAUdLKpEhp-amJQw-8NZDX9AfCDeA@mail.gmail.com>
On Tue, Oct 09, 2012 at 01:21:02PM -0300, Fabio Estevam wrote:
> On Tue, Oct 9, 2012 at 1:15 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>
> >>> I just tried building mainline now. It is at commit f5a246eab9.
> >>>
> >> The build still fails for me at this commit.
> >
> > I can't reproduce this.
>
> Same here. It builds fine for me.
>
Thanks all for confirming it works.
I just figured it out on my end. Here is how it gets broken for me.
- Before commit cd29672 (dtc: import latest upstream dtc) gets in,
I did a build without O=<output_dir>. It results in a copy of those
libfdt files in arch/arm/boot/compressed.
- After the commit gets in, I start a build with O=imx parameter. When
compiling imx/arch/arm/boot/compressed/fdt_ro.c, the #include <libfdt.h>
in fdt_ro.c seems to match the one left in arch/arm/boot/compressed/
from last build rather than imx/arch/arm/boot/compressed/libfdt.h.
Cleaning the libfdt copies in arch/arm/boot/compressed fixes the
problem. Not sure why it's not "libfdt.h" but <libfdt.h> is used as
the inclusion though, since the .h and .c are in the same folder.
Shawn
^ permalink raw reply
* [RFC PATCH] ARM: vt8500: Convert arch-vt8500 to multiplatform
From: Alexey Charkov @ 2012-10-11 7:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349939831-12939-1-git-send-email-linux@prisktech.co.nz>
2012/10/11 Tony Prisk <linux@prisktech.co.nz>:
> This patch completes the conversion to ARCH_MULTI_V5 for arch-vt8500.
> Removed /mach/include/ and remaining unneeded files.
>
> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
> ---
> arch/arm/Kconfig | 18 ++----------
> arch/arm/mach-vt8500/include/mach/debug-macro.S | 31 -------------------
> arch/arm/mach-vt8500/include/mach/timex.h | 26 ----------------
> arch/arm/mach-vt8500/include/mach/uncompress.h | 36 -----------------------
> 4 files changed, 2 insertions(+), 109 deletions(-)
> delete mode 100644 arch/arm/mach-vt8500/include/mach/debug-macro.S
> delete mode 100644 arch/arm/mach-vt8500/include/mach/timex.h
> delete mode 100644 arch/arm/mach-vt8500/include/mach/uncompress.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 32b62ac..e71ad2c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -938,22 +938,6 @@ config PLAT_SPEAR
> help
> Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
>
> -config ARCH_VT8500
> - bool "VIA/WonderMedia 85xx"
> - select CPU_ARM926T
> - select GENERIC_GPIO
> - select ARCH_HAS_CPUFREQ
> - select GENERIC_CLOCKEVENTS
> - select ARCH_REQUIRE_GPIOLIB
> - select USE_OF
> - select COMMON_CLK
> - select HAVE_CLK
> - select CLKDEV_LOOKUP
> - select MULTI_IRQ_HANDLER
> - select SPARSE_IRQ
> - help
> - Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
> -
> config ARCH_ZYNQ
> bool "Xilinx Zynq ARM Cortex A9 Platform"
> select CPU_V7
> @@ -1125,6 +1109,8 @@ source "arch/arm/mach-versatile/Kconfig"
> source "arch/arm/mach-vexpress/Kconfig"
> source "arch/arm/plat-versatile/Kconfig"
>
> +source "arch/arm/mach-vt8500/Kconfig"
> +
> source "arch/arm/mach-w90x900/Kconfig"
>
> # Definitions to make life easier
> diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/mach-vt8500/include/mach/debug-macro.S
> deleted file mode 100644
> index ca292f2..0000000
> --- a/arch/arm/mach-vt8500/include/mach/debug-macro.S
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/*
> - * arch/arm/mach-vt8500/include/mach/debug-macro.S
> - *
> - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
> - *
> - * Debugging macro include header
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - *
> -*/
> -
> - .macro addruart, rp, rv, tmp
> - mov \rp, #0x00200000
> - orr \rv, \rp, #0xf8000000
> - orr \rp, \rp, #0xd8000000
> - .endm
> -
> - .macro senduart,rd,rx
> - strb \rd, [\rx, #0]
> - .endm
> -
> - .macro busyuart,rd,rx
> -1001: ldr \rd, [\rx, #0x1c]
> - ands \rd, \rd, #0x2
> - bne 1001b
> - .endm
> -
> - .macro waituart,rd,rx
> - .endm
Does this imply that early printk won't be supported any longer, or am
I missing something?
Thanks,
Alexey
^ permalink raw reply
* [PATCH 5/6] ARM: ux500: Enable SDI4 port on the u9540 when booting with Device Tree
From: Lee Jones @ 2012-10-11 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121010190437.GU12801@game.jcrosoft.org>
On Wed, 10 Oct 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:18 Wed 10 Oct , Lee Jones wrote:
> > Here we add the device node for the SDI4 (MMC) port to the u9540
> > Device Tree source file. This will allow successful probing of
> > the internal MMC storage device when booting with DT enabled.
> >
> > Acked-by: Linus Walleij <linus.walleij@linaro.org>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > arch/arm/boot/dts/u9540.dts | 12 +++++++++++-
> > 1 file changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
> > index 28efe20..2dade76 100644
> > --- a/arch/arm/boot/dts/u9540.dts
> > +++ b/arch/arm/boot/dts/u9540.dts
> > @@ -21,7 +21,6 @@
> > };
> >
> > soc-u9500 {
> > -
> why?
My OCD shining though. It's either this or I create a seperate patch
for it. I think sneaking it in here is better.
> > uart at 80120000 {
> > status = "okay";
> > };
> > @@ -33,5 +32,16 @@
> > uart at 80007000 {
> > status = "okay";
> > };
> > +
> > + // On-board eMMC
> no c++ comment
Single line comments are perfectly valid in DTS(I) files.
See: Documentation/devicetree/booting-without-of.txt
> > + sdi4_per2 at 80114000 {
> > + arm,primecell-periphid = <0x10480180>;
> > + max-frequency = <50000000>;
> > + bus-width = <8>;
> > + mmc-cap-mmc-highspeed;
> > + vmmc-supply = <&ab8500_ldo_aux2_reg>;
> you need add the pinctrl here
Pinctrl will come in time. We have a priority list.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 4/6] ARM: ux500: Add UART support to the u9540 Device Tree
From: Lee Jones @ 2012-10-11 7:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121010190325.GT12801@game.jcrosoft.org>
On Wed, 10 Oct 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:18 Wed 10 Oct , Lee Jones wrote:
> > Add the 3 UART nodes required to enable serial ports on the u9540.
> >
> > Acked-by: Linus Walleij <linus.walleij@linaro.org>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > arch/arm/boot/dts/u9540.dts | 13 ++++++++++++-
> dts? it's dtsi
No it's not.
> it's the soc not the board
This is the board file, not the SoC.
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
> > index 0a66f34..28efe20 100644
> > --- a/arch/arm/boot/dts/u9540.dts
> > +++ b/arch/arm/boot/dts/u9540.dts
> > @@ -21,6 +21,17 @@
> > };
> >
> > soc-u9500 {
> > - };
> >
> > + uart at 80120000 {
> > + status = "okay";
> > + };
> > +
> > + uart at 80121000 {
> > + status = "okay";
> > + };
> > +
> > + uart at 80007000 {
> > + status = "okay";
> > + };
> do not enable device by default in the soc
See above.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 3/6] ARM: ux500: Add support for ST-Ericsson's u9540 SoC
From: Lee Jones @ 2012-10-11 7:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121010190144.GS12801@game.jcrosoft.org>
On Wed, 10 Oct 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:18 Wed 10 Oct , Lee Jones wrote:
> > First level board support for the u9540.
> >
> > Acked-by: Linus Walleij <linus.walleij@linaro.org>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > arch/arm/mach-ux500/cpu-db8500.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
> > index 3d8e321..6b7f970 100644
> > --- a/arch/arm/mach-ux500/cpu-db8500.c
> > +++ b/arch/arm/mach-ux500/cpu-db8500.c
> > @@ -17,6 +17,7 @@
> > #include <linux/platform_device.h>
> > #include <linux/io.h>
> > #include <linux/mfd/abx500/ab8500.h>
> > +#include <linux/mfd/dbx500-prcmu.h>
> > #include <linux/of.h>
> > #include <linux/of_platform.h>
> > #include <linux/regulator/machine.h>
> > @@ -319,6 +320,8 @@ static void __init u8500_init_machine(void)
> > snowball_pinmaps_init();
> > else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
> > hrefv60_pinmaps_init();
> > + else if (of_machine_is_compatible("st-ericsson,u9540")) {}
> > + /* TODO: Add u9540 pinmaps. */
> do you via DT no here
We don't support pinctrl yet. It will come, it's just not available yet.
> > /* TODO: Export SoC, USB, cpu-freq and DMA40 */
> > parent = u8500_of_init_devices();
> > @@ -331,6 +334,7 @@ static const char * u8500_dt_board_compat[] = {
> > "calaosystems,snowball-a9500",
> > "st-ericsson,hrefv60+",
> > "st-ericsson,mop500",
> > + "st-ericsson,u9540",
> stop to add more compatible sue a more generic one
Not entirely sure what you mean here.
These are the only four boards we officially support.
There are other uXXXX boards that we do not.
> > NULL,
> > };
> >
> > @@ -345,4 +349,14 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
> > .dt_compat = u8500_dt_board_compat,
> > MACHINE_END
> >
> > +DT_MACHINE_START(U9540_DT, "ST-Ericsson 9540 platform (Device Tree Support)")
> > + .map_io = u8500_map_io,
> > + .init_irq = ux500_init_irq,
> > + .timer = &ux500_timer,
> > + .handle_irq = gic_handle_irq,
> > + .init_machine = u8500_init_machine,
> > + .init_late = NULL,
> > + .dt_compat = u8500_dt_board_compat,
> > +MACHINE_END
> really?
> no need drop it for a more generic on
This may look the same as the previous MACHINE_START now, but
it will have differences in the future as more u9540 support is
upstreamed. I think it should stick around as a separate entity
for the time being. If we can consolidate the init functions at
a later date, believe me I will make sure it happens.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Multiplatform Kconfig options
From: Arnd Bergmann @ 2012-10-11 7:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349931799.7978.3.camel@gitbox>
On Thursday 11 October 2012, Tony Prisk wrote:
> What is the preference for multiplatform-enabled arch/Kconfig's?
>
> Should we be specifying options that are already enabled by
> multiplatform or can we assume they will always be enabled?
>
> It 'feels' safer to explicitly enable them to catch problems later when
> things are changed and people forget :)
>
> Examples: MULTI_IRQ_HANDLER, SPARSE_IRQ, USE_OF, COMMON_CLK...
They won't just go away from CONFIG_MULTIPLATFORM, no need to enable
them yourself. We also have a lot of options that are unconditionally
enabled for all ARM platforms.
Arnd
^ permalink raw reply
* [RFC PATCH] ARM: vt8500: Convert arch-vt8500 to multiplatform
From: Arnd Bergmann @ 2012-10-11 7:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CABjd4YzdwXmAeTrULWOGdFBg8xKXK4FN7fGJegjFZYmmxhrP2A@mail.gmail.com>
On Thursday 11 October 2012, Alexey Charkov wrote:
> Does this imply that early printk won't be supported any longer, or am
> I missing something?
You are correct. However, there is work under way to bring it back.
If you want to keep it around in the meantime, you could let the user
enable VT8500 either in MULTIPLATFORM or standalone using some Kconfig
logic like:
choice "Platform selection"
...
config VT8500_SINGLE
bool "Via/Wondermedia VT8500 / WM8505 / WM8650"
...
endchoice
...
config VT8500
bool "Via/Wondermedia VT8500 / WM8505 / WM8650" if ARCH_MULTIPLATFORM
default VT8500_SINGLE
Arnd
^ permalink raw reply
* [PATCH] ARM: dts: mxs: add the "clock-names" for gpmi-nand
From: Shawn Guo @ 2012-10-11 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349864829-19565-1-git-send-email-b32955@freescale.com>
On Wed, Oct 10, 2012 at 06:27:09PM +0800, Huang Shijie wrote:
> The current DT nodes for mx23/mx28 miss the `clocks-names` item for gpmi-nand.
> So the gpmi-nand driver could not find the proper clock.
>
> This patch fixes this issue.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
Applied, thanks.
Shawn
^ permalink raw reply
* [RFC PATCHv2] ARM: vt8500: Convert arch-vt8500 to multiplatform
From: Tony Prisk @ 2012-10-11 7:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch completes the conversion to ARCH_MULTI_V5 for arch-vt8500.
Removed /mach/include/ and remaining unneeded files.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
---
v2 Added the missing arch/arm/mach-vt8500/Kconfig
arch/arm/Kconfig | 18 ++----------
arch/arm/mach-vt8500/Kconfig | 11 +++++++
arch/arm/mach-vt8500/include/mach/debug-macro.S | 31 -------------------
arch/arm/mach-vt8500/include/mach/timex.h | 26 ----------------
arch/arm/mach-vt8500/include/mach/uncompress.h | 36 -----------------------
5 files changed, 13 insertions(+), 109 deletions(-)
create mode 100644 arch/arm/mach-vt8500/Kconfig
delete mode 100644 arch/arm/mach-vt8500/include/mach/debug-macro.S
delete mode 100644 arch/arm/mach-vt8500/include/mach/timex.h
delete mode 100644 arch/arm/mach-vt8500/include/mach/uncompress.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 32b62ac..e71ad2c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -938,22 +938,6 @@ config PLAT_SPEAR
help
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-config ARCH_VT8500
- bool "VIA/WonderMedia 85xx"
- select CPU_ARM926T
- select GENERIC_GPIO
- select ARCH_HAS_CPUFREQ
- select GENERIC_CLOCKEVENTS
- select ARCH_REQUIRE_GPIOLIB
- select USE_OF
- select COMMON_CLK
- select HAVE_CLK
- select CLKDEV_LOOKUP
- select MULTI_IRQ_HANDLER
- select SPARSE_IRQ
- help
- Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
-
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform"
select CPU_V7
@@ -1125,6 +1109,8 @@ source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/plat-versatile/Kconfig"
+source "arch/arm/mach-vt8500/Kconfig"
+
source "arch/arm/mach-w90x900/Kconfig"
# Definitions to make life easier
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
new file mode 100644
index 0000000..fa0c9fa
--- /dev/null
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -0,0 +1,11 @@
+config ARCH_VT8500
+ bool "VIA/WonderMedia 85xx" if ARCH_MULTI_V5
+ select ARCH_HAS_CPUFREQ
+ select ARCH_REQUIRE_GPIOLIB
+ select CLKDEV_LOOKUP
+ select CPU_ARM926T
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_GPIO
+ select HAVE_CLK
+ help
+ Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/mach-vt8500/include/mach/debug-macro.S
deleted file mode 100644
index ca292f2..0000000
--- a/arch/arm/mach-vt8500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/debug-macro.S
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Debugging macro include header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
- .macro addruart, rp, rv, tmp
- mov \rp, #0x00200000
- orr \rv, \rp, #0xf8000000
- orr \rp, \rp, #0xd8000000
- .endm
-
- .macro senduart,rd,rx
- strb \rd, [\rx, #0]
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x1c]
- ands \rd, \rd, #0x2
- bne 1001b
- .endm
-
- .macro waituart,rd,rx
- .endm
diff --git a/arch/arm/mach-vt8500/include/mach/timex.h b/arch/arm/mach-vt8500/include/mach/timex.h
deleted file mode 100644
index 8487e4c..0000000
--- a/arch/arm/mach-vt8500/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/timex.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef MACH_TIMEX_H
-#define MACH_TIMEX_H
-
-#define CLOCK_TICK_RATE (3000000)
-
-#endif /* MACH_TIMEX_H */
diff --git a/arch/arm/mach-vt8500/include/mach/uncompress.h b/arch/arm/mach-vt8500/include/mach/uncompress.h
deleted file mode 100644
index a9b6cae..0000000
--- a/arch/arm/mach-vt8500/include/mach/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-vt8500/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * Based on arch/arm/mach-dove/include/mach/uncompress.h
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#define UART0_PHYS 0xd8200000
-#define UART0_ADDR(x) *(volatile unsigned char *)(UART0_PHYS + x)
-
-static void putc(const char c)
-{
- while (UART0_ADDR(0x1c) & 0x2)
- /* Tx busy, wait and poll */;
-
- UART0_ADDR(0) = c;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
--
1.7.9.5
^ permalink raw reply related
* [PATCH 07/10] input: Enable STMPE keypad driver for Device Tree
From: Lee Jones @ 2012-10-11 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121010165004.GE19335@core.coreip.homeip.net>
On Wed, 10 Oct 2012, Dmitry Torokhov wrote:
> Hi Lee,
>
> On Fri, Oct 05, 2012 at 04:31:43PM +0100, Lee Jones wrote:
> > This patch allows the STMPE driver to be successfully probed and
> > initialised when Device Tree support is enabled. Besides the usual
> > platform data changes, we also separate the process of filling in
> > the 'in use' pin bitmap, as we have to extract the information from
> > Device Tree in the DT boot case.
>
>
> This generally looks OK although I wonder if we could not unify DT and
> non-DT case by doing:
>
> for (row = 0; row < STMPE_KEYPAD_MAX_ROWS; row++) {
> if (col = 0; col < STMPE_KEYPAD_MAX_COLS; col++) {
> int code = MATRIX_SCAN_CODE(row, col,
> STMPE_KEYPAD_ROW_SHIFT);
> if (keypad->keymap[code] != KEY_RESERVED) {
> keypad->rows |= 1 << row;
> keypad->cols |= 1 << col;
> }
> }
> }
Looks like it could work. I have a quite a long TODO list at the
moment, but I will add testing this to it.
> BTW, am I supposed to merge it or ack it?
If you Ack it, I can carry it for you no problem.
> > Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
> > Cc: linux-input at vger.kernel.org
> > Acked-by: Linus Walleij <linus.walleij@linaro.org>
> > Signed-off-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > drivers/input/keyboard/stmpe-keypad.c | 67 ++++++++++++++++++++++++++++-----
> > drivers/mfd/stmpe.c | 1 +
> > 2 files changed, 59 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/input/keyboard/stmpe-keypad.c b/drivers/input/keyboard/stmpe-keypad.c
> > index 470a877..c722d23 100644
> > --- a/drivers/input/keyboard/stmpe-keypad.c
> > +++ b/drivers/input/keyboard/stmpe-keypad.c
> > @@ -257,19 +257,73 @@ static int __devinit stmpe_keypad_chip_init(struct stmpe_keypad *keypad)
> > (plat->debounce_ms << 1));
> > }
> >
> > +static int stmpe_keypad_fill_used_pins(struct platform_device *pdev,
> > + struct stmpe_keypad *keypad,
> > + struct stmpe_keypad_platform_data *plat)
> > +{
> > + struct device_node *np = pdev->dev.of_node;
> > + unsigned int proplen;
> > + const __be32 *prop;
> > + int i;
> > +
> > + if (np) {
> > + prop = of_get_property(np, "linux,keymap", &proplen);
> > + if (!prop) {
> > + dev_err(&pdev->dev,
> > + "linux,keymap property not defined\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < proplen / sizeof(u32); i++) {
> > + unsigned int key = be32_to_cpup(prop + i);
> > +
> > + keypad->cols |= 1 << KEY_COL(key);
> > + keypad->rows |= 1 << KEY_ROW(key);
> > + }
> > + } else {
> > + for (i = 0; i < plat->keymap_data->keymap_size; i++) {
> > + unsigned int key = plat->keymap_data->keymap[i];
> > +
> > + keypad->cols |= 1 << KEY_COL(key);
> > + keypad->rows |= 1 << KEY_ROW(key);
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void __devinit stmpe_keypad_of_probe(struct device_node *np,
> > + struct stmpe_keypad_platform_data *plat)
> > +{
> > + of_property_read_u32(np, "debounce-interval", &plat->debounce_ms);
> > + of_property_read_u32(np, "stericsson,scan-count", &plat->scan_count);
> > +
> > + if (of_get_property(np, "stericsson,no-autorepeat", NULL))
> > + plat->no_autorepeat = true;
> > +}
> > +
> > static int __devinit stmpe_keypad_probe(struct platform_device *pdev)
> > {
> > struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
> > struct stmpe_keypad_platform_data *plat;
> > + struct device_node *np = pdev->dev.of_node;
> > struct stmpe_keypad *keypad;
> > struct input_dev *input;
> > int ret;
> > int irq;
> > - int i;
> >
> > plat = stmpe->pdata->keypad;
> > - if (!plat)
> > - return -ENODEV;
> > + if (!plat) {
> > + if (np) {
> > + plat = devm_kzalloc(&pdev->dev,
> > + sizeof(*plat), GFP_KERNEL);
> > + if (!plat)
> > + return -ENOMEM;
> > +
> > + stmpe_keypad_of_probe(np, plat);
> > + } else
> > + return -ENODEV;
> > + }
> >
> > irq = platform_get_irq(pdev, 0);
> > if (irq < 0)
> > @@ -300,12 +354,7 @@ static int __devinit stmpe_keypad_probe(struct platform_device *pdev)
> > if (!plat->no_autorepeat)
> > __set_bit(EV_REP, input->evbit);
> >
> > - for (i = 0; i < plat->keymap_data->keymap_size; i++) {
> > - unsigned int key = plat->keymap_data->keymap[i];
> > -
> > - keypad->cols |= 1 << KEY_COL(key);
> > - keypad->rows |= 1 << KEY_ROW(key);
> > - }
> > + stmpe_keypad_fill_used_pins(pdev, keypad, plat);
> >
> > keypad->stmpe = stmpe;
> > keypad->plat = plat;
> > diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
> > index ba157d4..b03cc64 100644
> > --- a/drivers/mfd/stmpe.c
> > +++ b/drivers/mfd/stmpe.c
> > @@ -321,6 +321,7 @@ static struct resource stmpe_keypad_resources[] = {
> >
> > static struct mfd_cell stmpe_keypad_cell = {
> > .name = "stmpe-keypad",
> > + .of_compatible = "st,stmpe-keypad",
> > .resources = stmpe_keypad_resources,
> > .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
> > };
> > --
> > 1.7.9.5
> >
>
> --
> Dmitry
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2 00/15] pinctrl: samsung: Usability and extensibiltiy improvements
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch series is a work on improving usability and extensibiltiy of
the pinctrl-samsung driver. It consists of three main parts:
- improving flexibility of SoC-specific data specification
- converting the driver to one GPIO chip and IRQ domain per pin bank
- improving wake-up IRQ setup and handling
1) What the first part does, in addition to various related fixes, is
removing any unnecessary static data from pinctrl-exynos driver.
This is achieved mostly thanks to assigning pin numbers dynamically,
with help of only pin counts of particular banks. It also simplifies
adding next SoC variants, since much less static data needs to be
specified.
2) The second part attempts to simplify usage of the driver and fix several
problems of current implementation, in particular:
- Simplifies GPIO pin specification in device tree by using pin
namespace local to pin bank instead of local to pin controller, e.g.
gpios = <&gpj0 3 0>;
instead of
gpios = <&pinctrl0 115 0>;
- Simplifies GPIO interrupt specification in device tree by using
namespace local to pin bank (and equal to GPIO namespace), e.g.
interrupt-parent = <&gpj0>;
interrupts = <3 0>;
instead of
interrupt-parent = <&pinctrl0>;
interrupts = <115 0>;
- Simplifies internal GPIO pin to bank translation thanks to
correspondence of particular GPIO chips to pin banks. This allows
to remove the (costly in case of GPIO bit-banging drivers) lookup
over all banks to find the one that the pin is from.
3) Third part is focused on removing the hard-coded description of wake-up
interrupt layout.
It moves wake-up interrupt description to bank struct and device tree,
which allows to specify which pin banks support wake-up interrupts and
how they are handled (direct or multiplexed/chained).
See particular patches for more detailed descriptions and the last patch for
updated device tree bindings.
Changes since v1:
- dropped moving SoC-specific data to device tree
(might be added in further patches)
- dropped per-bank specification of configuration register offsets
(thus limiting scope of the driver to Exynos SoCs; will be added in
further patches)
Tomasz Figa (15):
pinctrl: samsung: Detect and handle unsupported configuration types
pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
pinctrl: samsung: Assing pin numbers dynamically
pinctrl: samsung: Remove static pin enumerations
pinctrl: samsung: Distinguish between pin group and bank nodes
ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
pinctrl: samsung: Match pin banks with their device nodes
pinctrl: samsung: Hold pointer to driver data in bank struct
pinctrl: samsung: Include bank-specific eint offset in bank struct
pinctrl: exynos: Use one IRQ domain per pin bank
pinctrl: samsung: Use one GPIO chip per pin bank
pinctrl: samsung: Use per-bank IRQ domain for wake-up interrupts
pinctrl: exynos: Set pin function to EINT in irq_set_type of wake-up
EINT
pinctrl: samsung: Add GPIO to IRQ translation
Documentation: Update samsung-pinctrl device tree bindings
documentation
.../bindings/pinctrl/samsung-pinctrl.txt | 118 +++++--
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 278 ++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 241 +-------------
drivers/pinctrl/pinctrl-exynos.c | 367 ++++++++++-----------
drivers/pinctrl/pinctrl-exynos.h | 170 ++--------
drivers/pinctrl/pinctrl-samsung.c | 203 ++++++++----
drivers/pinctrl/pinctrl-samsung.h | 29 +-
7 files changed, 741 insertions(+), 665 deletions(-)
--
1.7.12
^ permalink raw reply
* [PATCH 01/15] pinctrl: samsung: Detect and handle unsupported configuration types
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch modifies the pinctrl-samsung driver to detect when width of a
bit field is set to zero (which means that such configuraton type is not
supported) and return an error instead of trying to modify an inexistent
register.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-samsung.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index dd108a9..c660fa5 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -391,6 +391,9 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
}
+ if (!width)
+ return -EINVAL;
+
mask = (1 << width) - 1;
shift = pin_offset * width;
data = readl(reg_base + cfg_reg);
--
1.7.12
^ permalink raw reply related
* [PATCH 02/15] pinctrl: samsung: Do not pass gpio_chip to pin_to_reg_bank
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
The pointer to gpio_chip passed to pin_to_reg_bank utility function is
used only to retrieve a pointer to samsung_pinctrl_drv_data structure.
This patch modifies the function and its users to pass a pointer to
samsung_pinctrl_drv_data directly.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-samsung.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index c660fa5..aa42d54 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -250,14 +250,12 @@ static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
* given a pin number that is local to a pin controller, find out the pin bank
* and the register base of the pin bank.
*/
-static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
- void __iomem **reg, u32 *offset,
+static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
+ unsigned pin, void __iomem **reg, u32 *offset,
struct samsung_pin_bank **bank)
{
- struct samsung_pinctrl_drv_data *drvdata;
struct samsung_pin_bank *b;
- drvdata = dev_get_drvdata(gc->dev);
b = drvdata->ctrl->pin_banks;
while ((pin >= b->pin_base) &&
@@ -292,7 +290,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
* pin function number in the config register.
*/
for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++) {
- pin_to_reg_bank(drvdata->gc, pins[cnt] - drvdata->ctrl->base,
+ pin_to_reg_bank(drvdata, pins[cnt] - drvdata->ctrl->base,
®, &pin_offset, &bank);
mask = (1 << bank->func_width) - 1;
shift = pin_offset * bank->func_width;
@@ -329,10 +327,13 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct samsung_pin_bank *bank;
+ struct samsung_pinctrl_drv_data *drvdata;
void __iomem *reg;
u32 data, pin_offset, mask, shift;
- pin_to_reg_bank(range->gc, offset, ®, &pin_offset, &bank);
+ drvdata = pinctrl_dev_get_drvdata(pctldev);
+
+ pin_to_reg_bank(drvdata, offset, ®, &pin_offset, &bank);
mask = (1 << bank->func_width) - 1;
shift = pin_offset * bank->func_width;
@@ -366,7 +367,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
u32 cfg_value, cfg_reg;
drvdata = pinctrl_dev_get_drvdata(pctldev);
- pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, ®_base,
+ pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, ®_base,
&pin_offset, &bank);
switch (cfg_type) {
@@ -468,8 +469,11 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
void __iomem *reg;
u32 pin_offset, data;
+ struct samsung_pinctrl_drv_data *drvdata;
- pin_to_reg_bank(gc, offset, ®, &pin_offset, NULL);
+ drvdata = dev_get_drvdata(gc->dev);
+
+ pin_to_reg_bank(drvdata, offset, ®, &pin_offset, NULL);
data = readl(reg + DAT_REG);
data &= ~(1 << pin_offset);
if (value)
@@ -482,8 +486,11 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
{
void __iomem *reg;
u32 pin_offset, data;
+ struct samsung_pinctrl_drv_data *drvdata;
+
+ drvdata = dev_get_drvdata(gc->dev);
- pin_to_reg_bank(gc, offset, ®, &pin_offset, NULL);
+ pin_to_reg_bank(drvdata, offset, ®, &pin_offset, NULL);
data = readl(reg + DAT_REG);
data >>= pin_offset;
data &= 1;
--
1.7.12
^ permalink raw reply related
* [PATCH 03/15] pinctrl: samsung: Assing pin numbers dynamically
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch modifies the pinctrl-samsung driver to assign numbers to pins
dynamically instead of static enumerations.
Thanks to this change the amount of code requried to support a SoC can
be greatly reduced and the code made more readable.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-exynos.c | 83 +++++++++++++++++----------------------
drivers/pinctrl/pinctrl-exynos.h | 11 ++----
drivers/pinctrl/pinctrl-samsung.c | 22 ++++++++++-
3 files changed, 62 insertions(+), 54 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 21362f4..0ea2164 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -484,51 +484,51 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
/* pin banks of exynos4210 pin-controller 0 */
static struct samsung_pin_bank exynos4210_pin_banks0[] = {
- EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
- EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
- EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
- EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
- EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
- EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
- EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
- EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
- EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
- EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
- EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
- EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
- EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
- EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
- EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
- EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0"),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb"),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0"),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1"),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0"),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1"),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1"),
+ EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2"),
+ EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3"),
};
/* pin banks of exynos4210 pin-controller 1 */
static struct samsung_pin_bank exynos4210_pin_banks1[] = {
- EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
- EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
- EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
- EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
- EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
- EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
- EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
- EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
- EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
- EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
- EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
- EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
- EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
- EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
- EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
- EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
- EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
- EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
- EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
- EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0"),
+ EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1"),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0"),
+ EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1"),
+ EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2"),
+ EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0"),
+ EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1"),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2"),
+ EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
+ EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
+ EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
+ EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
+ EXYNOS_PIN_BANK_EINTN(8, 0xC00, "gpx0"),
+ EXYNOS_PIN_BANK_EINTN(8, 0xC20, "gpx1"),
+ EXYNOS_PIN_BANK_EINTN(8, 0xC40, "gpx2"),
+ EXYNOS_PIN_BANK_EINTN(8, 0xC60, "gpx3"),
};
/* pin banks of exynos4210 pin-controller 2 */
static struct samsung_pin_bank exynos4210_pin_banks2[] = {
- EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
+ EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
};
/*
@@ -540,9 +540,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 0 data */
.pin_banks = exynos4210_pin_banks0,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
- .base = EXYNOS4210_GPIO_A0_START,
- .nr_pins = EXYNOS4210_GPIOA_NR_PINS,
- .nr_gint = EXYNOS4210_GPIOA_NR_GINT,
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
@@ -553,9 +550,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 1 data */
.pin_banks = exynos4210_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
- .base = EXYNOS4210_GPIOA_NR_PINS,
- .nr_pins = EXYNOS4210_GPIOB_NR_PINS,
- .nr_gint = EXYNOS4210_GPIOB_NR_GINT,
.nr_wint = 32,
.geint_con = EXYNOS_GPIO_ECON_OFFSET,
.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
@@ -571,9 +565,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
/* pin-controller instance 2 data */
.pin_banks = exynos4210_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
- .base = EXYNOS4210_GPIOA_NR_PINS +
- EXYNOS4210_GPIOB_NR_PINS,
- .nr_pins = EXYNOS4210_GPIOC_NR_PINS,
.label = "exynos4210-gpio-ctrl2",
},
};
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 31d0a06..1788467 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -165,11 +165,10 @@ enum exynos4210_gpio_xc_start {
#define EXYNOS_EINT_MAX_PER_BANK 8
#define EXYNOS_EINT_NR_WKUP_EINT
-#define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \
+#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
{ \
.pctl_offset = reg, \
- .pin_base = (__gpio##_START), \
- .nr_pins = (__gpio##_NR), \
+ .nr_pins = pins, \
.func_width = 4, \
.pud_width = 2, \
.drv_width = 2, \
@@ -179,18 +178,16 @@ enum exynos4210_gpio_xc_start {
.name = id \
}
-#define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \
+#define EXYNOS_PIN_BANK_EINTG(pins, reg, id) \
{ \
.pctl_offset = reg, \
- .pin_base = (__gpio##_START), \
- .nr_pins = (__gpio##_NR), \
+ .nr_pins = pins, \
.func_width = 4, \
.pud_width = 2, \
.drv_width = 2, \
.conpdn_width = 2, \
.pudpdn_width = 2, \
.eint_type = EINT_TYPE_GPIO, \
- .irq_base = (__gpio##_IRQ), \
.name = id \
}
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index aa42d54..f219bb6 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -46,6 +46,8 @@ struct pin_config {
{ "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
};
+static unsigned int pin_base = 0;
+
/* check if the selector is a valid pin group selector */
static int samsung_get_group_count(struct pinctrl_dev *pctldev)
{
@@ -792,6 +794,9 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
int id;
const struct of_device_id *match;
const struct device_node *node = pdev->dev.of_node;
+ struct samsung_pin_ctrl *ctrl;
+ struct samsung_pin_bank *bank;
+ int i;
id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
if (id < 0) {
@@ -799,7 +804,22 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
return NULL;
}
match = of_match_node(samsung_pinctrl_dt_match, node);
- return (struct samsung_pin_ctrl *)match->data + id;
+ ctrl = (struct samsung_pin_ctrl *)match->data + id;
+
+ bank = ctrl->pin_banks;
+ for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+ bank->pin_base = ctrl->nr_pins;
+ ctrl->nr_pins += bank->nr_pins;
+ if (bank->eint_type == EINT_TYPE_GPIO) {
+ bank->irq_base = ctrl->nr_gint;
+ ctrl->nr_gint += bank->nr_pins;
+ }
+ }
+
+ ctrl->base = pin_base;
+ pin_base += ctrl->nr_pins;
+
+ return ctrl;
}
static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
--
1.7.12
^ permalink raw reply related
* [PATCH 04/15] pinctrl: samsung: Remove static pin enumerations
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
Since pin numbers are now assigned dynamically, those are not needed
anymore.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-exynos.h | 119 ---------------------------------------
1 file changed, 119 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 1788467..2de4a29 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -17,125 +17,6 @@
* (at your option) any later version.
*/
-#define EXYNOS_GPIO_START(__gpio) ((__gpio##_START) + (__gpio##_NR))
-
-#define EXYNOS4210_GPIO_A0_NR (8)
-#define EXYNOS4210_GPIO_A1_NR (6)
-#define EXYNOS4210_GPIO_B_NR (8)
-#define EXYNOS4210_GPIO_C0_NR (5)
-#define EXYNOS4210_GPIO_C1_NR (5)
-#define EXYNOS4210_GPIO_D0_NR (4)
-#define EXYNOS4210_GPIO_D1_NR (4)
-#define EXYNOS4210_GPIO_E0_NR (5)
-#define EXYNOS4210_GPIO_E1_NR (8)
-#define EXYNOS4210_GPIO_E2_NR (6)
-#define EXYNOS4210_GPIO_E3_NR (8)
-#define EXYNOS4210_GPIO_E4_NR (8)
-#define EXYNOS4210_GPIO_F0_NR (8)
-#define EXYNOS4210_GPIO_F1_NR (8)
-#define EXYNOS4210_GPIO_F2_NR (8)
-#define EXYNOS4210_GPIO_F3_NR (6)
-#define EXYNOS4210_GPIO_J0_NR (8)
-#define EXYNOS4210_GPIO_J1_NR (5)
-#define EXYNOS4210_GPIO_K0_NR (7)
-#define EXYNOS4210_GPIO_K1_NR (7)
-#define EXYNOS4210_GPIO_K2_NR (7)
-#define EXYNOS4210_GPIO_K3_NR (7)
-#define EXYNOS4210_GPIO_L0_NR (8)
-#define EXYNOS4210_GPIO_L1_NR (3)
-#define EXYNOS4210_GPIO_L2_NR (8)
-#define EXYNOS4210_GPIO_Y0_NR (6)
-#define EXYNOS4210_GPIO_Y1_NR (4)
-#define EXYNOS4210_GPIO_Y2_NR (6)
-#define EXYNOS4210_GPIO_Y3_NR (8)
-#define EXYNOS4210_GPIO_Y4_NR (8)
-#define EXYNOS4210_GPIO_Y5_NR (8)
-#define EXYNOS4210_GPIO_Y6_NR (8)
-#define EXYNOS4210_GPIO_X0_NR (8)
-#define EXYNOS4210_GPIO_X1_NR (8)
-#define EXYNOS4210_GPIO_X2_NR (8)
-#define EXYNOS4210_GPIO_X3_NR (8)
-#define EXYNOS4210_GPIO_Z_NR (7)
-
-enum exynos4210_gpio_xa_start {
- EXYNOS4210_GPIO_A0_START = 0,
- EXYNOS4210_GPIO_A1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0),
- EXYNOS4210_GPIO_B_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1),
- EXYNOS4210_GPIO_C0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_B),
- EXYNOS4210_GPIO_C1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0),
- EXYNOS4210_GPIO_D0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1),
- EXYNOS4210_GPIO_D1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0),
- EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1),
- EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0),
- EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1),
- EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2),
- EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3),
- EXYNOS4210_GPIO_F0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4),
- EXYNOS4210_GPIO_F1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0),
- EXYNOS4210_GPIO_F2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1),
- EXYNOS4210_GPIO_F3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2),
-};
-
-enum exynos4210_gpio_xb_start {
- EXYNOS4210_GPIO_J0_START = 0,
- EXYNOS4210_GPIO_J1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0),
- EXYNOS4210_GPIO_K0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1),
- EXYNOS4210_GPIO_K1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0),
- EXYNOS4210_GPIO_K2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1),
- EXYNOS4210_GPIO_K3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2),
- EXYNOS4210_GPIO_L0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3),
- EXYNOS4210_GPIO_L1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0),
- EXYNOS4210_GPIO_L2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1),
- EXYNOS4210_GPIO_Y0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2),
- EXYNOS4210_GPIO_Y1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0),
- EXYNOS4210_GPIO_Y2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1),
- EXYNOS4210_GPIO_Y3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2),
- EXYNOS4210_GPIO_Y4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3),
- EXYNOS4210_GPIO_Y5_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4),
- EXYNOS4210_GPIO_Y6_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5),
- EXYNOS4210_GPIO_X0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6),
- EXYNOS4210_GPIO_X1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0),
- EXYNOS4210_GPIO_X2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1),
- EXYNOS4210_GPIO_X3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2),
-};
-
-enum exynos4210_gpio_xc_start {
- EXYNOS4210_GPIO_Z_START = 0,
-};
-
-#define EXYNOS4210_GPIO_A0_IRQ EXYNOS4210_GPIO_A0_START
-#define EXYNOS4210_GPIO_A1_IRQ EXYNOS4210_GPIO_A1_START
-#define EXYNOS4210_GPIO_B_IRQ EXYNOS4210_GPIO_B_START
-#define EXYNOS4210_GPIO_C0_IRQ EXYNOS4210_GPIO_C0_START
-#define EXYNOS4210_GPIO_C1_IRQ EXYNOS4210_GPIO_C1_START
-#define EXYNOS4210_GPIO_D0_IRQ EXYNOS4210_GPIO_D0_START
-#define EXYNOS4210_GPIO_D1_IRQ EXYNOS4210_GPIO_D1_START
-#define EXYNOS4210_GPIO_E0_IRQ EXYNOS4210_GPIO_E0_START
-#define EXYNOS4210_GPIO_E1_IRQ EXYNOS4210_GPIO_E1_START
-#define EXYNOS4210_GPIO_E2_IRQ EXYNOS4210_GPIO_E2_START
-#define EXYNOS4210_GPIO_E3_IRQ EXYNOS4210_GPIO_E3_START
-#define EXYNOS4210_GPIO_E4_IRQ EXYNOS4210_GPIO_E4_START
-#define EXYNOS4210_GPIO_F0_IRQ EXYNOS4210_GPIO_F0_START
-#define EXYNOS4210_GPIO_F1_IRQ EXYNOS4210_GPIO_F1_START
-#define EXYNOS4210_GPIO_F2_IRQ EXYNOS4210_GPIO_F2_START
-#define EXYNOS4210_GPIO_F3_IRQ EXYNOS4210_GPIO_F3_START
-#define EXYNOS4210_GPIO_J0_IRQ EXYNOS4210_GPIO_J0_START
-#define EXYNOS4210_GPIO_J1_IRQ EXYNOS4210_GPIO_J1_START
-#define EXYNOS4210_GPIO_K0_IRQ EXYNOS4210_GPIO_K0_START
-#define EXYNOS4210_GPIO_K1_IRQ EXYNOS4210_GPIO_K1_START
-#define EXYNOS4210_GPIO_K2_IRQ EXYNOS4210_GPIO_K2_START
-#define EXYNOS4210_GPIO_K3_IRQ EXYNOS4210_GPIO_K3_START
-#define EXYNOS4210_GPIO_L0_IRQ EXYNOS4210_GPIO_L0_START
-#define EXYNOS4210_GPIO_L1_IRQ EXYNOS4210_GPIO_L1_START
-#define EXYNOS4210_GPIO_L2_IRQ EXYNOS4210_GPIO_L2_START
-#define EXYNOS4210_GPIO_Z_IRQ EXYNOS4210_GPIO_Z_START
-
-#define EXYNOS4210_GPIOA_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
-#define EXYNOS4210_GPIOA_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3)
-#define EXYNOS4210_GPIOB_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3)
-#define EXYNOS4210_GPIOB_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2)
-#define EXYNOS4210_GPIOC_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z)
-
/* External GPIO and wakeup interrupt related definitions */
#define EXYNOS_GPIO_ECON_OFFSET 0x700
#define EXYNOS_GPIO_EMASK_OFFSET 0x900
--
1.7.12
^ permalink raw reply related
* [PATCH 05/15] pinctrl: samsung: Distinguish between pin group and bank nodes
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch modifies the loop iterating over all child nodes and parsing
pin groups to check whether the node is really a pin group node by
checking for existence of samsung,pins property.
This is a prerequisite for further patches adding additional subnodes to
the pinctrl node, required for per bank GPIO and interrupt specifiers.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-samsung.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index f219bb6..94e1378 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -609,7 +609,7 @@ static int __init samsung_pinctrl_parse_dt(struct platform_device *pdev,
*/
for_each_child_of_node(dev_np, cfg_np) {
u32 function;
- if (of_find_property(cfg_np, "interrupt-controller", NULL))
+ if (!of_find_property(cfg_np, "samsung,pins", NULL))
continue;
ret = samsung_pinctrl_parse_dt_pins(pdev, cfg_np,
--
1.7.12
^ permalink raw reply related
* [PATCH 06/15] ARM: dts: exynos4210-pinctrl: Add nodes for pin banks
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch is a preparation for converting the pinctrl-samsung driver to
one GPIO chip and IRQ domain per bank. It allows particular banks to be
specified using their phandles.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 272 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos4210.dtsi | 229 -------------------------
2 files changed, 272 insertions(+), 229 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index b12cf27..f207d8d 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -16,6 +16,134 @@
/ {
pinctrl at 11400000 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb: gpb {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe0: gpe0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe1: gpe1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe2: gpe2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe3: gpe3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpe4: gpe4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <0x2>;
@@ -205,6 +333,145 @@
};
pinctrl at 11000000 {
+ gpj0: gpj0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpj1: gpj1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk0: gpk0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk1: gpk1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk2: gpk2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpk3: gpk3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl0: gpl0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl1: gpl1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpl2: gpl2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpy6: gpy6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sd0_clk: sd0-clk {
samsung,pins = "gpk0-0";
samsung,pin-function = <2>;
@@ -438,6 +705,11 @@
};
pinctrl at 03860000 {
+ gpz: gpz {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
i2s0_bus: i2s0-bus {
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
"gpz-4", "gpz-5", "gpz-6";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557..b768e9f 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -74,233 +74,4 @@
compatible = "samsung,pinctrl-exynos4210";
reg = <0x03860000 0x1000>;
};
-
- gpio-controllers {
- #address-cells = <1>;
- #size-cells = <1>;
- gpio-controller;
- ranges;
-
- gpa0: gpio-controller at 11400000 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400000 0x20>;
- #gpio-cells = <4>;
- };
-
- gpa1: gpio-controller at 11400020 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400020 0x20>;
- #gpio-cells = <4>;
- };
-
- gpb: gpio-controller at 11400040 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400040 0x20>;
- #gpio-cells = <4>;
- };
-
- gpc0: gpio-controller at 11400060 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400060 0x20>;
- #gpio-cells = <4>;
- };
-
- gpc1: gpio-controller at 11400080 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400080 0x20>;
- #gpio-cells = <4>;
- };
-
- gpd0: gpio-controller at 114000A0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114000A0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpd1: gpio-controller at 114000C0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114000C0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpe0: gpio-controller at 114000E0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114000E0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpe1: gpio-controller at 11400100 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400100 0x20>;
- #gpio-cells = <4>;
- };
-
- gpe2: gpio-controller at 11400120 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400120 0x20>;
- #gpio-cells = <4>;
- };
-
- gpe3: gpio-controller at 11400140 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400140 0x20>;
- #gpio-cells = <4>;
- };
-
- gpe4: gpio-controller at 11400160 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400160 0x20>;
- #gpio-cells = <4>;
- };
-
- gpf0: gpio-controller at 11400180 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11400180 0x20>;
- #gpio-cells = <4>;
- };
-
- gpf1: gpio-controller at 114001A0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114001A0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpf2: gpio-controller at 114001C0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114001C0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpf3: gpio-controller at 114001E0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x114001E0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpj0: gpio-controller at 11000000 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000000 0x20>;
- #gpio-cells = <4>;
- };
-
- gpj1: gpio-controller at 11000020 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000020 0x20>;
- #gpio-cells = <4>;
- };
-
- gpk0: gpio-controller at 11000040 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000040 0x20>;
- #gpio-cells = <4>;
- };
-
- gpk1: gpio-controller at 11000060 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000060 0x20>;
- #gpio-cells = <4>;
- };
-
- gpk2: gpio-controller at 11000080 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000080 0x20>;
- #gpio-cells = <4>;
- };
-
- gpk3: gpio-controller at 110000A0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110000A0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpl0: gpio-controller at 110000C0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110000C0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpl1: gpio-controller at 110000E0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110000E0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpl2: gpio-controller at 11000100 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000100 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy0: gpio-controller at 11000120 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000120 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy1: gpio-controller at 11000140 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000140 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy2: gpio-controller at 11000160 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000160 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy3: gpio-controller at 11000180 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000180 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy4: gpio-controller at 110001A0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110001A0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy5: gpio-controller at 110001C0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110001C0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpy6: gpio-controller at 110001E0 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x110001E0 0x20>;
- #gpio-cells = <4>;
- };
-
- gpx0: gpio-controller at 11000C00 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000C00 0x20>;
- #gpio-cells = <4>;
- };
-
- gpx1: gpio-controller at 11000C20 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000C20 0x20>;
- #gpio-cells = <4>;
- };
-
- gpx2: gpio-controller at 11000C40 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000C40 0x20>;
- #gpio-cells = <4>;
- };
-
- gpx3: gpio-controller at 11000C60 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x11000C60 0x20>;
- #gpio-cells = <4>;
- };
-
- gpz: gpio-controller at 03860000 {
- compatible = "samsung,exynos4-gpio";
- reg = <0x03860000 0x20>;
- #gpio-cells = <4>;
- };
- };
};
--
1.7.12
^ permalink raw reply related
* [PATCH 07/15] pinctrl: samsung: Match pin banks with their device nodes
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch is a preparation for converting the pinctrl-samsung driver to
one GPIO chip and IRQ domain per bank. It binds banks defined by
internal driver data with bank nodes in device tree.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-samsung.c | 13 +++++++++++++
drivers/pinctrl/pinctrl-samsung.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 94e1378..f266710 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -794,6 +794,7 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
int id;
const struct of_device_id *match;
const struct device_node *node = pdev->dev.of_node;
+ struct device_node *np;
struct samsung_pin_ctrl *ctrl;
struct samsung_pin_bank *bank;
int i;
@@ -816,6 +817,18 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
}
}
+ for_each_child_of_node(node, np) {
+ if (!of_find_property(np, "gpio-controller", NULL))
+ continue;
+ bank = ctrl->pin_banks;
+ for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+ if (!strcmp(bank->name, np->name)) {
+ bank->of_node = np;
+ break;
+ }
+ }
+ }
+
ctrl->base = pin_base;
pin_base += ctrl->nr_pins;
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index b895693..5c53f32 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -111,6 +111,7 @@ struct samsung_pinctrl_drv_data;
* @eint_type: type of the external interrupt supported by the bank.
* @irq_base: starting controller local irq number of the bank.
* @name: name to be prefixed for each pin in this pin bank.
+ * @of_node: OF node of the bank.
*/
struct samsung_pin_bank {
u32 pctl_offset;
@@ -124,6 +125,7 @@ struct samsung_pin_bank {
enum eint_type eint_type;
u32 irq_base;
char *name;
+ struct device_node *of_node;
};
/**
--
1.7.12
^ permalink raw reply related
* [PATCH 08/15] pinctrl: samsung: Hold pointer to driver data in bank struct
From: Tomasz Figa @ 2012-10-11 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1349943081-27939-1-git-send-email-t.figa@samsung.com>
This patch is a preparation for converting the pinctrl-samsung driver to
one GPIO chip and IRQ domain per bank. It allows one having only
a pointer to particular bank struct to access driver data struct.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
drivers/pinctrl/pinctrl-samsung.c | 18 ++++++++++--------
drivers/pinctrl/pinctrl-samsung.h | 2 ++
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index f266710..53493c3 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -789,17 +789,18 @@ static const struct of_device_id samsung_pinctrl_dt_match[];
/* retrieve the soc specific data */
static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
+ struct samsung_pinctrl_drv_data *d,
struct platform_device *pdev)
{
int id;
const struct of_device_id *match;
- const struct device_node *node = pdev->dev.of_node;
+ struct device_node *node = pdev->dev.of_node;
struct device_node *np;
struct samsung_pin_ctrl *ctrl;
struct samsung_pin_bank *bank;
int i;
- id = of_alias_get_id(pdev->dev.of_node, "pinctrl");
+ id = of_alias_get_id(node, "pinctrl");
if (id < 0) {
dev_err(&pdev->dev, "failed to get alias id\n");
return NULL;
@@ -809,6 +810,7 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+ bank->drvdata = d;
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
if (bank->eint_type == EINT_TYPE_GPIO) {
@@ -848,18 +850,18 @@ static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
return -ENODEV;
}
- ctrl = samsung_pinctrl_get_soc_data(pdev);
- if (!ctrl) {
- dev_err(&pdev->dev, "driver data not available\n");
- return -EINVAL;
- }
-
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata) {
dev_err(dev, "failed to allocate memory for driver's "
"private data\n");
return -ENOMEM;
}
+
+ ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev);
+ if (!ctrl) {
+ dev_err(&pdev->dev, "driver data not available\n");
+ return -EINVAL;
+ }
drvdata->ctrl = ctrl;
drvdata->dev = dev;
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 5c53f32..ea5dadd 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -112,6 +112,7 @@ struct samsung_pinctrl_drv_data;
* @irq_base: starting controller local irq number of the bank.
* @name: name to be prefixed for each pin in this pin bank.
* @of_node: OF node of the bank.
+ * @drvdata: link to controller driver data
*/
struct samsung_pin_bank {
u32 pctl_offset;
@@ -126,6 +127,7 @@ struct samsung_pin_bank {
u32 irq_base;
char *name;
struct device_node *of_node;
+ struct samsung_pinctrl_drv_data *drvdata;
};
/**
--
1.7.12
^ permalink raw reply related
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