* [PATCH] Nokia N9/N900/N950 -- mention product names
From: Pavel Machek @ 2012-10-17 21:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121017192525.GD1613@blackmetal.musicnaut.iki.fi>
This adds product names (that most users know) to Kconfig and board
comments.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26..f03f19a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -263,14 +263,14 @@ config MACH_NOKIA_N8X0
select MACH_NOKIA_N810_WIMAX
config MACH_NOKIA_RM680
- bool "Nokia RM-680/696 board"
+ bool "Nokia N950 (RM-680) / N9 (RM-696) phones"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
select MACH_NOKIA_RM696
config MACH_NOKIA_RX51
- bool "Nokia RX-51 board"
+ bool "Nokia N900 (RX-51) phone"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0ad1bb3b..96f8757 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
/*
- * Board support file for Nokia RM-680/696.
+ * Board support file for Nokia N950 (RM-680) / N9 (RM-696).
*
* Copyright (C) 2010 Nokia
*
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd93..b60ca9d 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-omap2/board-rx51.c
+ * Board support file for Nokia N900 (aka RX-51).
*
* Copyright (C) 2007, 2008 Nokia
*
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply related
* [PATCH] ARM: OMAP2+: Only write the sysconfig on idle when necessary
From: Paul Walmsley @ 2012-10-17 20:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <507F16F5.9020803@ti.com>
On Wed, 17 Oct 2012, Jon Hunter wrote:
> Are you looking to go one step further and only update the sysconfig on
> enabling when the context has been lost? That would require more
> changes.
Yes that's exactly it. That would avoid adding a special case for what
should be the common case. From a quick glance it looks like the cache
needs to be loaded in _reset(), omap_hwmod_softreset(), and _enable().
Other than that, seems like the cached value should work.
It should also be possible to avoid the reload in _enable() in most cases
since the PM code should know whether the IP block's powerdomain was
programmed to go off and indeed whether it did so. It shouldn't involve
any extra register reads. But I wouldn't expect you to add that
optimization; would just be nice to have a comment to that effect.
If the meta-theme of your message is that commit
233cbe5b94096f95ba7bca2162d63275b0b90b5b should have had closer scrutiny,
I agree with you, but we're beyond that point now...
- Paul
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Only write the sysconfig on idle when necessary
From: Jon Hunter @ 2012-10-17 20:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.00.1210172023130.9767@utopia.booyaka.com>
On 10/17/2012 03:25 PM, Paul Walmsley wrote:
> cc Rajendra
>
> Hi Jon
>
> On Wed, 17 Oct 2012, Jon Hunter wrote:
>
>> Currently, whenever we idle a device _idle_sysc() is called and writes to the
>> devices SYSCONFIG register to set the idle mode. A lot devices are using the
>> smart-idle mode and so the write to the SYSCONFIG register is programming the
>> same value that is already stored in the register.
>>
>> Writes to the devices SYSCONFIG register can be slow, for example, writing to
>> the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
>> clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
>> take ~100us.
>>
>> Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
>> calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
>> the SYSCONFIG register with a new value.
>>
>> Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
>> idling the device, only write the value if the value has changed. It should be
>> safe to do this on idle as the context of the register will never be lost while
>> the device is active.
>>
>> Verified that suspend, CORE off and retention states are working with this
>> change on OMAP3430 Beagle board.
>
> The code used to do what you propose in _write_sysconfig(), which applied
> to all sysconfig writes, not just idle. But it was changed by commit
> 233cbe5b94096f95ba7bca2162d63275b0b90b5b ("OMAP2+: hwmod: Update the
> sysc_cache in case module context is lost"). Could you take a look at
> this and maybe discuss it with Rajendra? It seems to make more sense to
> me to cache it by default, and only invalidate it when we know that
> context is lost.
Ok, thanks. Yes, only updating the register when the cache value changed
would not work due to the possibility of context being lost. So
Rajendra's change makes sense. However, I think there is room to
optimise this.
With this change, on idle, the cache value and register value are only
updated when needed. This should be safe.
Are you looking to go one step further and only update the sysconfig on
enabling when the context has been lost? That would require more
changes. This was a quick optimisation I saw when reviewing the code.
Rajendra, let me know if you have any comments.
Cheers
Jon
^ permalink raw reply
* [PATCH v2] arm: omap: move OMAP USB platform data to <linux/platform_data/omap-usb.h>
From: Tony Lindgren @ 2012-10-17 20:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350488838-6289-1-git-send-email-balbi@ti.com>
* Felipe Balbi <balbi@ti.com> [121017 08:54]:
> In order to make single zImage work for ARM architecture,
> we need to make sure we don't depend on private headers.
>
> Move USB platform_data to <linux/platform_data/omap-usb.h>
> and keep only internal functions in <plat/usb.h>.
Thanks, looks like I can't make this apply against v3.7-rc1:
patching file arch/arm/plat-omap/include/plat/usb.h
Hunk #1 FAILED at 1.
Hunk #2 FAILED at 26.
Hunk #3 FAILED at 44.
Hunk #4 FAILED at 65.
Hunk #5 FAILED at 81.
Hunk #6 succeeded at 28 with fuzz 2 (offset -128 lines).
5 out of 6 hunks FAILED -- rejects in file arch/arm/plat-omap/include/plat/usb.h
Can you please check it?
Regards,
Tony
^ permalink raw reply
* IS_ERR_OR_NULL - please STOP telling people to use this on a whim
From: Phil Carmody @ 2012-10-17 20:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121017194157.GM21164@n2100.arm.linux.org.uk>
On 17/10/12 20:41 +0100, Russell King - ARM Linux wrote:
> People,
>
> This is not aimed at anyone specifically - but it is aimed at everyone
> who reviews patches to make them aware of this issue, and to modify their
> behaviour.
>
> I'm geting sick and tired of telling people about this. I've just
> floated the idea of removing IS_ERR_OR_NULL from the kernel tree because
> it's one of the most incorrectly used and abused macros we have in the
> source tree.
This makes me sad. I was responsible for its introduction, and my motive
was exactly yours in sending the above.
> It would be one thing if this was only being done by people who are
> submitting new code, but it's far worse than that. Reviewers who should
> know better are telling people to use it _incorrectly_.
>
> Reviewers really need to think about your review comments. Looking
> through the kernel tree today, I see lots of uses of IS_ERR_OR_NULL(),
> many of them are *buggy*.
>
> Take a moment to think about this:
>
> int error_value(struct device *dev, void *foo)
> {
> if (IS_ERR_OR_NULL(foo))
> return PTR_ERR(foo);
> return 0;
> }
>
> Consider the value this function returns for three arguments:
>
> 1. an errno encoded pointer
> 2. a NULL pointer.
> 3. a valid pointer.
>
> If you can't see the problem, then *do* *not* tell anyone to use
> IS_ERR_OR_NULL(), because you do *not* have the understanding necessary
> to make that judgement yourself - you're probably telling people to
> create buggy code.
The problem I saw was functions returning -ERRORs or NULL. There were
too many, and there was too much sloppy code inconsistently handling one
or either of the two, and not always both. I did consider trying to fix
some of the core functions that were returning -ERRORs or NULL to the
drivers I was involved in, but it seemed like there were too many, and
that would be too "brave". I imagined that my macro would help catch
that undesirable situation, and permit people to map the error onto
whatever was most appropriate to propagate on.
The idea of them propagating the undesirable problem up further in the call
chain is the exact antithesis of what I intended.
Thank you for highlighting the issue I didn't foresee (neither did my
colleagues at Nokia, they made good use of it fairly quickly) and in
such unambiguous terms. Better to nip it in the bud, certainly.
> Here's the list so far of what looks like buggy uses specific to ARM.
> There _are_ others elsewhere in the kernel.
>
> drivers/media/video/s5p-mfc/s5p_mfc.c: if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
> drivers/media/video/s5p-mfc/s5p_mfc.c- ret = PTR_ERR(dev->alloc_ctx[0]);
> drivers/media/video/s5p-mfc/s5p_mfc.c- goto err_res;
> drivers/media/video/s5p-mfc/s5p_mfc.c- }
...
:-(
So, what to do? It can and has been used sensibly, so I don't think removing
it is the best option.
Phil
"pcarmody at nokia.com" is no more, I'm now "pc+lkml at asdf.org"
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Only write the sysconfig on idle when necessary
From: Paul Walmsley @ 2012-10-17 20:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350504742-19995-1-git-send-email-jon-hunter@ti.com>
cc Rajendra
Hi Jon
On Wed, 17 Oct 2012, Jon Hunter wrote:
> Currently, whenever we idle a device _idle_sysc() is called and writes to the
> devices SYSCONFIG register to set the idle mode. A lot devices are using the
> smart-idle mode and so the write to the SYSCONFIG register is programming the
> same value that is already stored in the register.
>
> Writes to the devices SYSCONFIG register can be slow, for example, writing to
> the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
> clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
> take ~100us.
>
> Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
> calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
> the SYSCONFIG register with a new value.
>
> Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
> idling the device, only write the value if the value has changed. It should be
> safe to do this on idle as the context of the register will never be lost while
> the device is active.
>
> Verified that suspend, CORE off and retention states are working with this
> change on OMAP3430 Beagle board.
The code used to do what you propose in _write_sysconfig(), which applied
to all sysconfig writes, not just idle. But it was changed by commit
233cbe5b94096f95ba7bca2162d63275b0b90b5b ("OMAP2+: hwmod: Update the
sysc_cache in case module context is lost"). Could you take a look at
this and maybe discuss it with Rajendra? It seems to make more sense to
me to cache it by default, and only invalidate it when we know that
context is lost.
- Paul
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Only write the sysconfig on idle when necessary
From: Jon Hunter @ 2012-10-17 20:12 UTC (permalink / raw)
To: linux-arm-kernel
Currently, whenever we idle a device _idle_sysc() is called and writes to the
devices SYSCONFIG register to set the idle mode. A lot devices are using the
smart-idle mode and so the write to the SYSCONFIG register is programming the
same value that is already stored in the register.
Writes to the devices SYSCONFIG register can be slow, for example, writing to
the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
take ~100us.
Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
the SYSCONFIG register with a new value.
Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
idling the device, only write the value if the value has changed. It should be
safe to do this on idle as the context of the register will never be lost while
the device is active.
Verified that suspend, CORE off and retention states are working with this
change on OMAP3430 Beagle board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/omap_hwmod.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1..962773b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1389,6 +1389,10 @@ static void _idle_sysc(struct omap_hwmod *oh)
if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
_enable_wakeup(oh, &v);
+ /* If the cached value is the same as the new value, skip the write */
+ if (oh->_sysc_cache == v)
+ return;
+
_write_sysconfig(v, oh);
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] mmc: core: Support all MMC capabilities when booting from Device Tree
From: Philip Rakity @ 2012-10-17 19:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210171338.01011.arnd@arndb.de>
On 17 Oct 2012, at 14:38, Arnd Bergmann <arnd@arndb.de> wrote:
> On Monday 15 October 2012, Lee Jones wrote:
>>> and so on. What are you actually missing in the properties that
>>> are already there?
>>
>> MMC_CAP_ERASE
>
> This one seems to be set unconditionally on some controllers but
> not on others. Why would it need to be configurable?
>
>> MMC_CAP_UHS_SDR12
>> MMC_CAP_UHS_SDR25
>> MMC_CAP_UHS_DDR50
>
> Could this be derived from max-frequency?
The problem is the controller may signal it supports DDR but the host cannot. For example no voltage at correct level.
Same issue with 8 bit support. Controller could say supports it but board has only 4 "wires"
>
>> MMC_CAP_1_8V_DDR
>
> Right, I suppose we need this. Should we have a minimum and maximum
> voltage added to the common properties for this?
>
>> MMC_CAP2_DETECT_ON_ERR
>> MMC_CAP2_NO_SLEEP_CMD
>
> I don't see these ones being set anywhere, but they were both
> added by Ulf. Maybe he can comment on if or why they are needed
> in devicetree, rather than being set by the driver unconditionally
> or for specific versions of the host controller.
>
> Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* IS_ERR_OR_NULL - please STOP telling people to use this on a whim
From: Russell King - ARM Linux @ 2012-10-17 19:41 UTC (permalink / raw)
To: linux-arm-kernel
People,
This is not aimed at anyone specifically - but it is aimed at everyone
who reviews patches to make them aware of this issue, and to modify their
behaviour.
I'm geting sick and tired of telling people about this. I've just
floated the idea of removing IS_ERR_OR_NULL from the kernel tree because
it's one of the most incorrectly used and abused macros we have in the
source tree.
It would be one thing if this was only being done by people who are
submitting new code, but it's far worse than that. Reviewers who should
know better are telling people to use it _incorrectly_.
Reviewers really need to think about your review comments. Looking
through the kernel tree today, I see lots of uses of IS_ERR_OR_NULL(),
many of them are *buggy*.
Take a moment to think about this:
int error_value(struct device *dev, void *foo)
{
if (IS_ERR_OR_NULL(foo))
return PTR_ERR(foo);
return 0;
}
Consider the value this function returns for three arguments:
1. an errno encoded pointer
2. a NULL pointer.
3. a valid pointer.
If you can't see the problem, then *do* *not* tell anyone to use
IS_ERR_OR_NULL(), because you do *not* have the understanding necessary
to make that judgement yourself - you're probably telling people to
create buggy code.
Here's the list so far of what looks like buggy uses specific to ARM.
There _are_ others elsewhere in the kernel.
drivers/media/video/s5p-mfc/s5p_mfc.c: if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
drivers/media/video/s5p-mfc/s5p_mfc.c- ret = PTR_ERR(dev->alloc_ctx[0]);
drivers/media/video/s5p-mfc/s5p_mfc.c- goto err_res;
drivers/media/video/s5p-mfc/s5p_mfc.c- }
--
drivers/media/video/s5p-mfc/s5p_mfc.c: if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
drivers/media/video/s5p-mfc/s5p_mfc.c- ret = PTR_ERR(dev->alloc_ctx[1]);
drivers/media/video/s5p-mfc/s5p_mfc.c- goto err_mem_init_ctx_1;
drivers/media/video/s5p-mfc/s5p_mfc.c- }
--
drivers/staging/omapdrm/omap_dmm_tiler.c: if (IS_ERR_OR_NULL(txn))
drivers/staging/omapdrm/omap_dmm_tiler.c- return PTR_ERR(txn);
drivers/staging/omapdrm/omap_dmm_tiler.c-
drivers/staging/omapdrm/omap_dmm_tiler.c- tcm_for_each_slice(slice, *area, area_s) {
--
drivers/staging/omap-thermal/omap-bandgap.c: if (IS_ERR_OR_NULL(bg_ptr)) {
drivers/staging/omap-thermal/omap-bandgap.c- dev_err(&pdev->dev, "failed to fetch platform data\n");
drivers/staging/omap-thermal/omap-bandgap.c- return PTR_ERR(bg_ptr);
drivers/staging/omap-thermal/omap-bandgap.c- }
--
drivers/staging/omap-thermal/omap-thermal-common.c: if (IS_ERR_OR_NULL(data->omap_thermal)) {
drivers/staging/omap-thermal/omap-thermal-common.c- dev_err(bg_ptr->dev, "thermal zone device is NULL\n");
drivers/staging/omap-thermal/omap-thermal-common.c- return PTR_ERR(data->omap_thermal);
drivers/staging/omap-thermal/omap-thermal-common.c- }
--
drivers/staging/omap-thermal/omap-thermal-common.c: if (IS_ERR_OR_NULL(freq_table)) {
drivers/staging/omap-thermal/omap-thermal-common.c- dev_err(bg_ptr->dev,
drivers/staging/omap-thermal/omap-thermal-common.c- "%s: failed to get cpufreq table (%p)\n",
drivers/staging/omap-thermal/omap-thermal-common.c- __func__, freq_table);
--
drivers/staging/omap-thermal/omap-thermal-common.c: if (IS_ERR_OR_NULL(data->cool_dev)) {
drivers/staging/omap-thermal/omap-thermal-common.c- dev_err(bg_ptr->dev,
drivers/staging/omap-thermal/omap-thermal-common.c- "Failed to register cpufreq cooling device\n");
drivers/staging/omap-thermal/omap-thermal-common.c- return PTR_ERR(data->cool_dev);
--
drivers/gpu/drm/exynos/exynos_drm_dmabuf.c: if (IS_ERR_OR_NULL(sgt)) {
drivers/gpu/drm/exynos/exynos_drm_dmabuf.c- ret = PTR_ERR(sgt);
drivers/gpu/drm/exynos/exynos_drm_dmabuf.c- goto err_buf_detach;
drivers/gpu/drm/exynos/exynos_drm_dmabuf.c- }
--
drivers/gpu/drm/exynos/exynos_drm_fbdev.c: if (IS_ERR_OR_NULL(helper->fb)) {
drivers/gpu/drm/exynos/exynos_drm_fbdev.c- DRM_ERROR("failed to create drm framebuffer.\n");
drivers/gpu/drm/exynos/exynos_drm_fbdev.c- ret = PTR_ERR(helper->fb);
drivers/gpu/drm/exynos/exynos_drm_fbdev.c- goto out;
--
^ permalink raw reply
* PDF documentation
From: Constantine Shulyupin @ 2012-10-17 19:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121017165125.12301.qmail@stuge.se>
On Wed, Oct 17, 2012 at 6:51 PM, Peter Stuge <peter@stuge.se> wrote:
> Constantine Shulyupin wrote:
>> Peter, can you please just send me some links to most frequently
>> used online PDF?
>
> I don't have a particular PDF that is used more frequently than
> others. Here's one I used recently, for a common flash chip:
>
> http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/DBACA1C90564EBB248257639003A563A/$File/MX29GL128E,%203V%20(VI-O),%20128Mb,%20v1.5.pdf
>
>> I would like to convert them to html and see how usable it is.
I've converted you pdf and uploaded to a site:
http://makelinux.net/lib/macronix/MX29GL128E/
It can't even approach to replase PDF, but it adds possibility to
send in a e-mail link to a specific page:
COMMON FLASH MEMORY INTERFACE (CFI) MODE:
http://makelinux.net/lib/macronix/MX29GL128E/doc-34
http://makelinux.net/lib/macronix/MX29GL128E/doc-35
Here is jet another document, huge 5K pages DS of OMAP4460:
http://makelinux.net/lib/ti/OMAP4460/
http://makelinux.net/lib/ti/OMAP4460/doc-outline
OMAP4460 USBPHY Registers: http://makelinux.net/lib/ti/OMAP4460/doc-5464
Debug Modules Memory Mapping: http://makelinux.net/lib/ti/OMAP4460/doc-5845
How it looks?
Can it be useful?
--
Constantine Shulyupin
http://www.MakeLinux.com/
Embedded Linux Systems,
Device Drivers, TI DaVinci
^ permalink raw reply
* [GIT PULL 3/3] ARM: Kirkwood: fix for v3.7
From: Jason Cooper @ 2012-10-17 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <pull-1350501943-114231>
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/kirkwood_cache_build_fix_for_v3.7
for you to fetch changes up to f7d87d2726f823dc4a0d4900ac06446e4e485fdb:
Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2 (2012-10-17 17:56:37 +0000)
----------------------------------------------------------------
Depends:
- Based on v3.7-rc1
Adds:
- Better #ifdef logic for CACHE_FEROCEON_L2 to prevent linker errors
----------------------------------------------------------------
Jason Gunthorpe (1):
Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2
arch/arm/mach-kirkwood/board-dt.c | 2 --
arch/arm/mach-kirkwood/common.c | 4 ++--
2 files changed, 2 insertions(+), 4 deletions(-)
^ permalink raw reply
* [GIT PULL 2/3] ARM: mvebu: fix for v3.7
From: Jason Cooper @ 2012-10-17 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <pull-1350501943-114231>
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/mvebu_gpio_fixes_for_v3.7
for you to fetch changes up to 7cf8c9f7810ec1b9feaaa7914aaec4fc73c0c5d5:
gpio: mvebu: Add missing breaks in mvebu_gpio_irq_set_type (2012-10-17 17:40:18 +0000)
----------------------------------------------------------------
Depends:
- Based on v3.7-rc1
Adds:
- missing break;s from converting if{}s to switch{}
----------------------------------------------------------------
Axel Lin (1):
gpio: mvebu: Add missing breaks in mvebu_gpio_irq_set_type
drivers/gpio/gpio-mvebu.c | 3 +++
1 file changed, 3 insertions(+)
^ permalink raw reply
* [PATCH] Nokia N9/N900/N950 -- mention product names
From: Aaro Koskinen @ 2012-10-17 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121017183307.GA12560@elf.ucw.cz>
Hi,
Some minor comments:
On Wed, Oct 17, 2012 at 08:33:08PM +0200, Pavel Machek wrote:
> This adds product names (that most users know) to Kconfig and board
> comments.
Good idea. :-)
> Signed-off-by: Pavel Machek <pavel@ucw.cz>
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 346fd26..da08226 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -263,14 +263,14 @@ config MACH_NOKIA_N8X0
> select MACH_NOKIA_N810_WIMAX
>
> config MACH_NOKIA_RM680
> - bool "Nokia RM-680/696 board"
> + bool "Nokia N9/N950 (RM-680/696) phones"
This should be "N950/N9 (RM-680/RM-696)" or perhaps for clarity
"N950 (RM-680) / N9 (RM-696)".
> depends on ARCH_OMAP3
> default y
> select OMAP_PACKAGE_CBB
> select MACH_NOKIA_RM696
>
> config MACH_NOKIA_RX51
> - bool "Nokia RX-51 board"
> + bool "Nokia N900 phone (RX-51)"
> depends on ARCH_OMAP3
> default y
> select OMAP_PACKAGE_CBB
> diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
> index 0ad1bb3b..26965f3 100644
> --- a/arch/arm/mach-omap2/board-rm680.c
> +++ b/arch/arm/mach-omap2/board-rm680.c
> @@ -1,5 +1,5 @@
> /*
> - * Board support file for Nokia RM-680/696.
> + * Board support file for Nokia N9/N950 (aka RM-680/696).
Same here.
Thanks,
A.
^ permalink raw reply
* [GIT PULL 1/3] ARM: Dove: fixes for v3.7
From: Jason Cooper @ 2012-10-17 19:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <pull-1350501943-114231>
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/mvebu_dove_late_fixes_for_v3.7
for you to fetch changes up to a458926e16a37ef41a4fbf45957cb9faaeb6a6ef:
ARM: dove: Add crypto engine to DT (2012-10-17 17:20:01 +0000)
----------------------------------------------------------------
Depends:
- Based against v3.7-rc1
- Latest changes to arch/arm/mm/cache-tauros2.c
c2b7e05 ARM: cache: add dt support for tauros2 cache
Misc. fixes for latest changes to mach-dove/
Fixes build breakage for mach-dove
----------------------------------------------------------------
Sebastian Hesselbarth (6):
ARM: dove: Add pcie clock support
ARM: dove: Fix tauros2 device tree init
ARM: dove: Fix clock names of sata and gbe
ARM: dove: Restructure SoC device tree descriptor
ARM: dove: Remove watchdog from DT
ARM: dove: Add crypto engine to DT
arch/arm/boot/dts/dove.dtsi | 49 +++++++++++++++++++++++++++++----------------
arch/arm/mach-dove/common.c | 8 ++++----
arch/arm/mach-dove/pcie.c | 5 +++++
3 files changed, 41 insertions(+), 21 deletions(-)
^ permalink raw reply
* [GIT PULL 0/3] ARM: mvebu/kirkwood/dove fixes for v3.7
From: Jason Cooper @ 2012-10-17 19:25 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit ddffeb8c4d0331609ef2581d84de4d763607bd37:
Linux 3.7-rc1 (2012-10-14 14:41:04 -0700)
are available in the git repository at:
git://git.infradead.org/users/jcooper/linux.git tags/mvebu_merge_test_for_v3.7
for you to fetch changes up to 624e773fdcb50ffc27dfb899644d5c0824ae506c:
Merge branch 'v3.7-rc1/mvebu/gpio-fixes' into v3.7-rc1/merge-test (2012-10-17 18:19:07 +0000)
----------------------------------------------------------------
Depends:
- Based on v3.7-rc1
Adds:
- late fixes for dove
- gpio fix for mvebu
- cache build fix for kirkwood
Merge conflicts:
- none observed
I'm trying out using a 'merge-test' branch as a kind of summary for when I send
multiple pull requests. There's *no* need to pull this branch, it's purely
informational.
----------------------------------------------------------------
Axel Lin (1):
gpio: mvebu: Add missing breaks in mvebu_gpio_irq_set_type
Jason Cooper (2):
Merge branch 'v3.7-rc1/kirkwood/cache-build-fix' into v3.7-rc1/merge-test
Merge branch 'v3.7-rc1/mvebu/gpio-fixes' into v3.7-rc1/merge-test
Jason Gunthorpe (1):
Build failure CONFIG_ARCH_KIRKWOOD_DT relies on CACHE_FEROCEON_L2
Sebastian Hesselbarth (6):
ARM: dove: Add pcie clock support
ARM: dove: Fix tauros2 device tree init
ARM: dove: Fix clock names of sata and gbe
ARM: dove: Restructure SoC device tree descriptor
ARM: dove: Remove watchdog from DT
ARM: dove: Add crypto engine to DT
arch/arm/boot/dts/dove.dtsi | 49 +++++++++++++++++++++++++--------------
arch/arm/mach-dove/common.c | 8 +++----
arch/arm/mach-dove/pcie.c | 5 ++++
arch/arm/mach-kirkwood/board-dt.c | 2 --
arch/arm/mach-kirkwood/common.c | 4 ++--
drivers/gpio/gpio-mvebu.c | 3 +++
6 files changed, 46 insertions(+), 25 deletions(-)
^ permalink raw reply
* [PATCHv1] arm:socfpga: Enable SMP for socfpga
From: dinguyen at altera.com @ 2012-10-17 19:18 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
Enable SMP for the SOCFPGA platform.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
arch/arm/boot/dts/socfpga.dtsi | 10 ++
arch/arm/configs/socfpga_defconfig | 9 +-
arch/arm/mach-socfpga/Kconfig | 1 +
arch/arm/mach-socfpga/Makefile | 3 +
arch/arm/mach-socfpga/headsmp.S | 64 +++++++++++
arch/arm/mach-socfpga/include/mach/core.h | 33 ++++++
arch/arm/mach-socfpga/platsmp.c | 166 +++++++++++++++++++++++++++++
arch/arm/mach-socfpga/socfpga.c | 33 +++++-
8 files changed, 315 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-socfpga/headsmp.S
create mode 100644 arch/arm/mach-socfpga/include/mach/core.h
create mode 100644 arch/arm/mach-socfpga/platsmp.c
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0772f57..19aec42 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -143,5 +143,15 @@
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ rstmgr at ffd05000 {
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ };
+
+ sysmgr at ffd08000 {
+ compatible = "altr,sys-mgr";
+ reg = <0xffd08000 0x4000>;
+ };
};
};
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index 0ac1293..349ac22 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -1,5 +1,5 @@
CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SOCFPGA=y
-CONFIG_MACH_SOCFPGA_CYCLONE5=y
-CONFIG_ARM_THUMBEE=y
+# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
CONFIG_VMSPLIT_2G=y
CONFIG_NR_CPUS=2
CONFIG_AEABI=y
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 803a328..566e804 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -12,5 +12,6 @@ config ARCH_SOCFPGA
select GENERIC_CLOCKEVENTS
select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU
+ select HAVE_SMP
select SPARSE_IRQ
select USE_OF
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4fb9324..61b1266 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,4 +2,7 @@
# Makefile for the linux kernel.
#
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
obj-y := socfpga.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
new file mode 100644
index 0000000..b3a24db
--- /dev/null
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2003 ARM Limited
+ * Copyright (c) u-boot contributors
+ * Copyright (c) 2012 Pavel Machek <pavel@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+#define CPU1_START_ADDR 0xffd08010
+
+ENTRY(secondary_trampoline)
+ /* From u-boot: start.S */
+ mrs r0, cpsr
+ bic r0, r0, #0x1f
+ orr r0, r0, #0xd3
+ msr cpsr,r0
+
+/*************************************************************************
+ *
+ * cpu_init_cp15
+ ** Copyright (c) u-boot contributors
+ * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
+ * CONFIG_SYS_ICACHE_OFF is defined.
+ *
+ *************************************************************************/
+ENTRY(cpu_init_cp15)
+ /*
+ * Invalidate L1 I/D
+ */
+ mov r0, #0 @ set up for MCR
+ mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
+ bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
+ orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
+ orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
+ mcr p15, 0, r0, c1, c0, 0
+
+ movw r0, #:lower16:CPU1_START_ADDR
+ movt r0, #:upper16:CPU1_START_ADDR
+
+ ldr r1, [r0]
+ bx r1
+
+ENTRY(secondary_trampoline_end)
+
+ .align
+ .long pen_release
+
diff --git a/arch/arm/mach-socfpga/include/mach/core.h b/arch/arm/mach-socfpga/include/mach/core.h
new file mode 100644
index 0000000..74a4949
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/core.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_CORE_H
+#define __MACH_CORE_H
+
+extern void secondary_startup(void);
+extern void __iomem *socfpga_scu_base_addr;
+
+extern void socfpga_init_clocks(void);
+extern void socfpga_sysmgr_init(void);
+
+extern struct smp_operations socfpga_smp_ops;
+
+#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
+
+#endif
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
new file mode 100644
index 0000000..59d7069
--- /dev/null
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright 2012 Pavel Machek <pavel@denx.de>
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+
+#include <mach/core.h>
+
+static void __iomem *sys_manager_base_addr;
+static void __iomem *rst_manager_base_addr;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void __cpuinit socfpga_secondary_init(unsigned int cpu)
+{
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_secondary_init(0);
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ pen_release = -1;
+ smp_wmb();
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+ extern char secondary_trampoline, secondary_trampoline_end;
+
+ int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+ /*
+ * Set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+ __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
+
+ pen_release = 0;
+ flush_cache_all();
+ smp_wmb();
+ outer_clean_range(0, trampoline_size);
+
+ /* This will release CPU #1 out of reset.*/
+ __raw_writel(0, rst_manager_base_addr + 0x10);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init socfpga_smp_init_cpus(void)
+{
+ unsigned int i, ncores;
+
+ ncores = scu_get_core_count(socfpga_scu_base_addr);
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ /* sanity check */
+ if (ncores > num_possible_cpus()) {
+ pr_warn("socfpga: no. of cores (%d) greater than configured"
+ "maximum of %d - clipping\n", ncores, num_possible_cpus());
+ ncores = num_possible_cpus();
+ }
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(socfpga_scu_base_addr);
+}
+
+void __init socfpga_sysmgr_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
+ sys_manager_base_addr = of_iomap(np, 0);
+
+ np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
+ rst_manager_base_addr = of_iomap(np, 0);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+static void socfpga_cpu_die(unsigned int cpu)
+{
+ cpu_do_idle();
+
+ /* We should have never returned from idle */
+ panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+}
+
+struct smp_operations socfpga_smp_ops __initdata = {
+ .smp_init_cpus = socfpga_smp_init_cpus,
+ .smp_prepare_cpus = socfpga_smp_prepare_cpus,
+ .smp_secondary_init = socfpga_secondary_init,
+ .smp_boot_secondary = socfpga_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = socfpga_cpu_die,
+#endif
+};
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index f01e1eb..20cdfdf 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -21,8 +21,34 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
-extern void socfpga_init_clocks(void);
+#include <mach/core.h>
+
+void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
+
+static struct map_desc scu_io_desc __initdata = {
+ .virtual = SOCFPGA_SCU_VIRT_BASE,
+ .pfn = 0, /* run-time */
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+};
+
+static void __init socfpga_scu_map_io(void)
+{
+ unsigned long base;
+
+ /* Get SCU base */
+ asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+ scu_io_desc.pfn = __phys_to_pfn(base);
+ iotable_init(&scu_io_desc, 1);
+}
+
+static void __init socfpga_map_io(void)
+{
+ socfpga_scu_map_io();
+}
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
@@ -32,6 +58,9 @@ const static struct of_device_id irq_match[] = {
static void __init gic_init_irq(void)
{
of_irq_init(irq_match);
+#ifdef CONFIG_SMP
+ socfpga_sysmgr_init();
+#endif
}
static void socfpga_cyclone5_restart(char mode, const char *cmd)
@@ -53,6 +82,8 @@ static const char *altera_dt_match[] = {
};
DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+ .smp = smp_ops(socfpga_smp_ops),
+ .map_io = socfpga_map_io,
.init_irq = gic_init_irq,
.handle_irq = gic_handle_irq,
.timer = &dw_apb_timer,
--
1.7.9.5
^ permalink raw reply related
* [PATCH] usb: phy: samsung: Introducing usb phy driver for hsotg
From: Russell King - ARM Linux @ 2012-10-17 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <005801cdac56$8da0c120$a8e24360$%kim@samsung.com>
On Wed, Oct 17, 2012 at 08:00:00PM +0900, Kukjin Kim wrote:
> > +static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
> > +{
> > + struct clk *ref_clk;
> > + int refclk_freq = 0;
> > +
> > + ref_clk = clk_get(sphy->dev, "xusbxti");
> > + if (IS_ERR(ref_clk)) {
>
> IS_ERR_OR_NULL(ref_clk)?
For the N'th time, NO. IS_ERR is correct here.
> > + dev_err(sphy->dev, "Failed to get reference clock\n");
> > + return PTR_ERR(ref_clk);
Look, it's the ABI. Not only that but it's also TOTALLY AND UTTERLY WRONG
to use IS_ERR_OR_NULL(foo) and then follow it with return PTR_ERR(foo).
You end up returning ZERO.
Stop telling people to use IS_ERR_OR_NULL without properly thinking about
it first. Virtually every single one of these done this way is a BUG.
Are we clear on this?
^ permalink raw reply
* [PATCHv1] arm:socfpga: Enable SMP for socfpga
From: Rob Herring @ 2012-10-17 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350501498-23601-1-git-send-email-dinguyen@altera.com>
On 10/17/2012 02:18 PM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen@altera.com>
>
> Enable SMP for the SOCFPGA platform.
>
> Signed-off-by: Pavel Machek <pavel@denx.de>
> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 10 ++
> arch/arm/configs/socfpga_defconfig | 9 +-
Does the multi_v7_defconfig not work for you?
> arch/arm/mach-socfpga/Kconfig | 1 +
> arch/arm/mach-socfpga/Makefile | 3 +
> arch/arm/mach-socfpga/headsmp.S | 64 +++++++++++
> arch/arm/mach-socfpga/include/mach/core.h | 33 ++++++
Move core.h to mach-socfpga.
> arch/arm/mach-socfpga/platsmp.c | 166 +++++++++++++++++++++++++++++
> arch/arm/mach-socfpga/socfpga.c | 33 +++++-
> 8 files changed, 315 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/headsmp.S
> create mode 100644 arch/arm/mach-socfpga/include/mach/core.h
> create mode 100644 arch/arm/mach-socfpga/platsmp.c
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 0772f57..19aec42 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -143,5 +143,15 @@
> reg-shift = <2>;
> reg-io-width = <4>;
> };
> +
> + rstmgr at ffd05000 {
> + compatible = "altr,rst-mgr";
> + reg = <0xffd05000 0x1000>;
> + };
> +
> + sysmgr at ffd08000 {
> + compatible = "altr,sys-mgr";
> + reg = <0xffd08000 0x4000>;
> + };
Bindings need documentation.
> };
> };
> diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
> index 0ac1293..349ac22 100644
> --- a/arch/arm/configs/socfpga_defconfig
> +++ b/arch/arm/configs/socfpga_defconfig
> @@ -1,5 +1,5 @@
> CONFIG_EXPERIMENTAL=y
> -CONFIG_SYSVIPC=y
> +CONFIG_NO_HZ=y
> CONFIG_IKCONFIG=y
> CONFIG_IKCONFIG_PROC=y
> CONFIG_LOG_BUF_SHIFT=14
> @@ -16,10 +16,13 @@ CONFIG_MODULE_UNLOAD=y
> # CONFIG_IOSCHED_DEADLINE is not set
> # CONFIG_IOSCHED_CFQ is not set
> CONFIG_ARCH_SOCFPGA=y
> -CONFIG_MACH_SOCFPGA_CYCLONE5=y
> -CONFIG_ARM_THUMBEE=y
> +# CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
> # CONFIG_CACHE_L2X0 is not set
> CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_SMP=y
> +CONFIG_ARM_ARCH_TIMER=y
> +CONFIG_HIGHMEM=y
> +CONFIG_HIGHPTE=y
> CONFIG_VMSPLIT_2G=y
> CONFIG_NR_CPUS=2
> CONFIG_AEABI=y
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 803a328..566e804 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -12,5 +12,6 @@ config ARCH_SOCFPGA
> select GENERIC_CLOCKEVENTS
> select GPIO_PL061 if GPIOLIB
> select HAVE_ARM_SCU
> + select HAVE_SMP
> select SPARSE_IRQ
> select USE_OF
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 4fb9324..61b1266 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -2,4 +2,7 @@
> # Makefile for the linux kernel.
> #
>
> +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
> +
This can be removed if core.h is moved.
> obj-y := socfpga.o
> +obj-$(CONFIG_SMP) += headsmp.o platsmp.o
> diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
> new file mode 100644
> index 0000000..b3a24db
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/headsmp.S
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright (c) 2003 ARM Limited
> + * Copyright (c) u-boot contributors
> + * Copyright (c) 2012 Pavel Machek <pavel@denx.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> + __INIT
> +
> +#define CPU1_START_ADDR 0xffd08010
> +
> +ENTRY(secondary_trampoline)
This appears to be your reset code at phys addr 0. How does core 0 boot
if you are copying this to 0?
> + /* From u-boot: start.S */
> + mrs r0, cpsr
> + bic r0, r0, #0x1f
> + orr r0, r0, #0xd3
> + msr cpsr,r0
> +
> +/*************************************************************************
> + *
> + * cpu_init_cp15
> + ** Copyright (c) u-boot contributors
> + * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
> + * CONFIG_SYS_ICACHE_OFF is defined.
> + *
> + *************************************************************************/
> +ENTRY(cpu_init_cp15)
> + /*
> + * Invalidate L1 I/D
> + */
> + mov r0, #0 @ set up for MCR
> + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
> + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
> + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
> + mcr p15, 0, r0, c7, c10, 4 @ DSB
> + mcr p15, 0, r0, c7, c5, 4 @ ISB
> +
> + /*
> + * disable MMU stuff and caches
> + */
> + mrc p15, 0, r0, c1, c0, 0
> + bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
> + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
> + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
> + orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
> + orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
All this should get done by v7_setup.
> + mcr p15, 0, r0, c1, c0, 0
> +
> + movw r0, #:lower16:CPU1_START_ADDR
> + movt r0, #:upper16:CPU1_START_ADDR
> +
> + ldr r1, [r0]
> + bx r1
> +
> +ENTRY(secondary_trampoline_end)
> +
> + .align
> + .long pen_release
> +
> diff --git a/arch/arm/mach-socfpga/include/mach/core.h b/arch/arm/mach-socfpga/include/mach/core.h
> new file mode 100644
> index 0000000..74a4949
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/core.h
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright 2012 Pavel Machek <pavel@denx.de>
> + * Copyright (C) 2012 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#ifndef __MACH_CORE_H
> +#define __MACH_CORE_H
> +
> +extern void secondary_startup(void);
> +extern void __iomem *socfpga_scu_base_addr;
> +
> +extern void socfpga_init_clocks(void);
> +extern void socfpga_sysmgr_init(void);
> +
> +extern struct smp_operations socfpga_smp_ops;
> +
> +#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
> +
> +#endif
> diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
> new file mode 100644
> index 0000000..59d7069
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/platsmp.c
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright 2010-2011 Calxeda, Inc.
> + * Copyright 2012 Pavel Machek <pavel@denx.de>
> + * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
> + * Copyright (C) 2012 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/hardware/gic.h>
> +#include <asm/smp_scu.h>
> +#include <asm/smp_plat.h>
> +
> +#include <mach/core.h>
> +
> +static void __iomem *sys_manager_base_addr;
> +static void __iomem *rst_manager_base_addr;
> +
> +static DEFINE_SPINLOCK(boot_lock);
> +
> +static void __cpuinit socfpga_secondary_init(unsigned int cpu)
> +{
> + /*
> + * if any interrupts are already enabled for the primary
> + * core (e.g. timer irq), then they will not have been enabled
> + * for us: do so
> + */
> + gic_secondary_init(0);
> +
> + /*
> + * let the primary processor know we're out of the
> + * pen, then head off into the C entry point
> + */
> + pen_release = -1;
> + smp_wmb();
> +
> + /*
> + * Synchronise with the boot thread.
> + */
> + spin_lock(&boot_lock);
> + spin_unlock(&boot_lock);
> +}
> +
> +static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + unsigned long timeout;
> + extern char secondary_trampoline, secondary_trampoline_end;
> +
> + int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
> +
> + /*
> + * Set synchronisation state between this boot processor
> + * and the secondary one
> + */
> + spin_lock(&boot_lock);
> +
> + memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
> +
> + __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10));
> +
> + pen_release = 0;
> + flush_cache_all();
> + smp_wmb();
> + outer_clean_range(0, trampoline_size);
> +
> + /* This will release CPU #1 out of reset.*/
> + __raw_writel(0, rst_manager_base_addr + 0x10);
> +
> + timeout = jiffies + (1 * HZ);
> + while (time_before(jiffies, timeout)) {
> + smp_rmb();
> + if (pen_release == -1)
> + break;
> +
> + udelay(10);
> + }
> +
> + /*
> + * now the secondary core is starting up let it run its
> + * calibrations, then wait for it to finish
> + */
> + spin_unlock(&boot_lock);
> + return pen_release != -1 ? -ENOSYS : 0;
You don't need any of this if you can reset secondary cores on hotplug.
Rob
^ permalink raw reply
* [PATCH RFC 02/15 v5] gpio: Add sysfs support to block GPIO API
From: Greg KH @ 2012-10-17 19:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350477107-26512-3-git-send-email-stigge@antcom.de>
On Wed, Oct 17, 2012 at 02:31:34PM +0200, Roland Stigge wrote:
> This patch adds sysfs support to the block GPIO API.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
>
> ---
> Documentation/ABI/testing/sysfs-gpio | 6
> drivers/gpio/gpiolib.c | 214 +++++++++++++++++++++++++++++++++++
> include/asm-generic/gpio.h | 11 +
> include/linux/gpio.h | 13 ++
> 4 files changed, 243 insertions(+), 1 deletion(-)
>
> --- linux-2.6.orig/Documentation/ABI/testing/sysfs-gpio
> +++ linux-2.6/Documentation/ABI/testing/sysfs-gpio
> @@ -24,4 +24,8 @@ Description:
> /base ... (r/o) same as N
> /label ... (r/o) descriptive, not necessarily unique
> /ngpio ... (r/o) number of GPIOs; numbered N to N + (ngpio - 1)
> -
> + /blockN ... for each GPIO block #N
> + /ngpio ... (r/o) number of GPIOs in this group
> + /exported ... sysfs export state of this group (0, 1)
> + /value ... current value as 32 or 64 bit integer in decimal
> + (only available if /exported is 1)
I think you need some more documentation here, as I just noticed
something "odd":
> +static int gpio_block_value_unexport(struct gpio_block *block)
> +{
> + struct device *dev;
> + int i;
> +
> + dev = class_find_device(&gpio_block_class, NULL, block, match_export);
> + if (!dev)
> + return -ENODEV;
> +
> + for (i = 0; i < block->ngpio; i++)
> + gpio_free(block->gpio[i]);
> +
> + device_remove_file(dev, &dev_attr_block_value);
> +
> + return 0;
> +}
Wait, what? You are removing a sysfs file in this function, from within
a sysfs write:
> +static ssize_t gpio_block_exported_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + long value;
> + int status;
> + struct gpio_block *block = dev_get_drvdata(dev);
> + int exported = gpio_block_value_is_exported(block);
> +
> + status = kstrtoul(buf, 0, &value);
> + if (status < 0)
> + goto err;
> +
> + if (value != exported) {
> + if (value)
> + status = gpio_block_value_export(block);
> + else
> + status = gpio_block_value_unexport(block);
That looks like a recipie for disaster. Why do you allow userspace to
do this?
Anyway, the other fixups for how you create/destroy the attribute files
looks great, thanks for making those changes.
greg k-h
^ permalink raw reply
* [PATCH] ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driver
From: Jon Hunter @ 2012-10-17 18:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Vaibhav Hiremath <hvaibhav@ti.com>
Add dmtimer clock aliases for AM33XX devices so that the parent clock for
the dmtimer can be set correctly by the dmtimer driver. Without these clock
aliases the dmtimer driver will fail to find the parent clocks for the dmtimer.
Verified that DMTIMERs can be successfully requested on AM335x beagle bone.
Original patch was provided by Vaibhav Hiremath [1]. Changelog and
additional verification performed by Jon Hunter.
[1] http://marc.info/?l=linux-omap&m=134693631608018&w=2
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/clock33xx_data.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 114ab4b..1a45d6b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1073,6 +1073,8 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
+ CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
+ CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
};
int __init am33xx_clk_init(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] mmc: core: Support all MMC capabilities when booting from Device Tree
From: Ulf Hansson @ 2012-10-17 18:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201210171338.01011.arnd@arndb.de>
On 17 October 2012 15:38, Arnd Bergmann <arnd@arndb.de> wrote:
> On Monday 15 October 2012, Lee Jones wrote:
>> > and so on. What are you actually missing in the properties that
>> > are already there?
>>
>> MMC_CAP_ERASE
>
> This one seems to be set unconditionally on some controllers but
> not on others. Why would it need to be configurable?
>
>> MMC_CAP_UHS_SDR12
>> MMC_CAP_UHS_SDR25
>> MMC_CAP_UHS_DDR50
>
> Could this be derived from max-frequency?
No, this is likely depending on what the hw controller supports. Not
connected to the freq.
UHS also means 1.8 V I/O voltage.
>
>> MMC_CAP_1_8V_DDR
>
> Right, I suppose we need this. Should we have a minimum and maximum
> voltage added to the common properties for this?
>
>> MMC_CAP2_DETECT_ON_ERR
>> MMC_CAP2_NO_SLEEP_CMD
>
> I don't see these ones being set anywhere, but they were both
> added by Ulf. Maybe he can comment on if or why they are needed
> in devicetree, rather than being set by the driver unconditionally
> or for specific versions of the host controller.
>From ux500 perspective there are patches not been up-streamed yet
which are using these host caps, for whatever it is worth for you to
know and consider.
Actually, I think quite a few of the host caps in mmc could be debated
whether those should exist at all.
Some are directly mapped to what the host controller hw support, some
are purely what the host driver (sw) support, but then there are
others kind of "mmc/sd/sdio software support configuration" which are
kind of strange host caps to me. For example MMC_CAP2_DETECT_ON_ERR
which I invented. :-). I think it especially these "software support
configuration" caps that might be causing this dt issues.
Would be very interesting to hear if someone is sharing my thoughts
around the host caps. Or if I am totally wrong here.
Kind regards
Ulf Hansson
^ permalink raw reply
* [PATCH 2/2] ARM: OMAP2+: Add device-tree support for 32kHz counter
From: Jon Hunter @ 2012-10-17 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350498803-22150-1-git-send-email-jon-hunter@ti.com>
For OMAP devices, the 32kHz counter is the default clock-source for the kernel.
However, this is not the only possible clock-source the kernel can use for OMAP
devices.
When booting with device-tree, if the 32kHz counter is the desired clock-source
for the kernel, then parse the device-tree blob to ensure that the counter is
present and if so map memory for the counter using the device-tree of_iomap()
function so we are no longer reliant on the OMAP HWMOD framework to do this for
us.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
arch/arm/mach-omap2/timer.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index d064afd..a67688f 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -159,6 +159,11 @@ static struct of_device_id omap_timer_match[] __initdata = {
{ }
};
+static struct of_device_id omap_counter_match[] __initdata = {
+ { .compatible = "ti,omap-counter32k", },
+ { }
+};
+
/**
* omap_get_timer_dt - get a timer using device-tree
* @match - device-tree match structure for matching a device type
@@ -378,11 +383,26 @@ static u32 notrace dmtimer_read_sched_clock(void)
static int __init omap2_sync32k_clocksource_init(void)
{
int ret;
+ struct device_node *np = NULL;
struct omap_hwmod *oh;
void __iomem *vbase;
const char *oh_name = "counter_32k";
/*
+ * If device-tree is present, then search the DT blob
+ * to see if the 32kHz counter is supported.
+ */
+ if (of_have_populated_dt()) {
+ np = omap_get_timer_dt(omap_counter_match, NULL);
+ if (!np)
+ return -ENODEV;
+
+ of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
+ if (!oh_name)
+ return -ENODEV;
+ }
+
+ /*
* First check hwmod data is available for sync32k counter
*/
oh = omap_hwmod_lookup(oh_name);
@@ -391,7 +411,13 @@ static int __init omap2_sync32k_clocksource_init(void)
omap_hwmod_setup_one(oh_name);
- vbase = omap_hwmod_get_mpu_rt_va(oh);
+ if (of_have_populated_dt()) {
+ vbase = of_iomap(np, 0);
+ of_node_put(np);
+ } else {
+ vbase = omap_hwmod_get_mpu_rt_va(oh);
+ }
+
if (!vbase) {
pr_warn("%s: failed to get counter_32k resource\n", __func__);
return -ENXIO;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: OMAP: Add counter-32k nodes
From: Jon Hunter @ 2012-10-17 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1350498803-22150-1-git-send-email-jon-hunter@ti.com>
Adds the counter-32k timers nodes present in OMAP2/3/4 devices and
device-tree binding documentation for OMAP counter-32k.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
---
.../devicetree/bindings/arm/omap/counter32k.txt | 15 +++++++++++++++
arch/arm/boot/dts/omap2420.dtsi | 6 ++++++
arch/arm/boot/dts/omap2430.dtsi | 6 ++++++
arch/arm/boot/dts/omap3.dtsi | 6 ++++++
arch/arm/boot/dts/omap4.dtsi | 6 ++++++
5 files changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/omap/counter32k.txt
diff --git a/Documentation/devicetree/bindings/arm/omap/counter32k.txt b/Documentation/devicetree/bindings/arm/omap/counter32k.txt
new file mode 100644
index 0000000..1983fae
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/counter32k.txt
@@ -0,0 +1,15 @@
+OMAP Counter-32K bindings
+
+Required properties:
+- compatible: Must be "ti,omap-counter32k" for OMAP controllers
+- reg: Contains timer register address range (base address and length)
+- ti,hwmods: Name of the hwmod associated to the counter, which is typically
+ "counter_32k"
+
+Example:
+
+counter32k: counter32k at 4a304000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4a304000 0x001f>;
+ ti,hwmods = "counter_32k";
+};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 5f68a70..082193f 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,12 @@
compatible = "ti,omap2420", "ti,omap2";
ocp {
+ counter32k: counter32k at 48004000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x48004000 0x001f>;
+ ti,hwmods = "counter_32k";
+ };
+
omap2420_pmx: pinmux at 48000030 {
compatible = "ti,omap2420-padconf", "pinctrl-single";
reg = <0x48000030 0x0113>;
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 7439987..2e568cf 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,12 @@
compatible = "ti,omap2430", "ti,omap2";
ocp {
+ counter32k: counter32k at 49020000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x49020000 0x001f>;
+ ti,hwmods = "counter_32k";
+ };
+
omap2430_pmx: pinmux at 49002030 {
compatible = "ti,omap2430-padconf", "pinctrl-single";
reg = <0x49002030 0x0154>;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 3fb910f..aa775b2 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,6 +61,12 @@
ranges;
ti,hwmods = "l3_main";
+ counter32k: counter32k at 48320000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x48320000 0x001f>;
+ ti,hwmods = "counter_32k";
+ };
+
intc: interrupt-controller at 48200000 {
compatible = "ti,omap2-intc";
interrupt-controller;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f6ac2b7..3eb66ee 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -95,6 +95,12 @@
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+ counter32k: counter32k at 4a304000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4a304000 0x001f>;
+ ti,hwmods = "counter_32k";
+ };
+
omap4_pmx_core: pinmux at 4a100040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a100040 0x0196>;
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/2] ARM: OMAP2+: Add device-tree support for 32kHz counter
From: Jon Hunter @ 2012-10-17 18:33 UTC (permalink / raw)
To: linux-arm-kernel
This series adds device-tree support for the 32kHz counter on OMAP2+ devices,
which is used as the default kernel clock-source for OMAP devices.
Boot tested on OMAP2420 H4, OMAP3430 Beagle Board and OMAP4430 Panda Board
with and without device-tree present.
Based and dependent upon OMAP2+ series that adds device-tree support for
DMTIMERs [1].
[1] http://marc.info/?l=linux-omap&m=135049690119218&w=2
Jon Hunter (2):
ARM: dts: OMAP: Add counter-32k nodes
ARM: OMAP2+: Add device-tree support for 32kHz counter
.../devicetree/bindings/arm/omap/counter32k.txt | 15 +++++++++++
arch/arm/boot/dts/omap2420.dtsi | 6 +++++
arch/arm/boot/dts/omap2430.dtsi | 6 +++++
arch/arm/boot/dts/omap3.dtsi | 6 +++++
arch/arm/boot/dts/omap4.dtsi | 6 +++++
arch/arm/mach-omap2/timer.c | 28 +++++++++++++++++++-
6 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/counter32k.txt
--
1.7.9.5
^ permalink raw reply
* [PATCH] Nokia N9/N900/N950 -- mention product names
From: Pavel Machek @ 2012-10-17 18:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20120504181105.GL5613@atomide.com>
Hi!
This adds product names (that most users know) to Kconfig and board
comments.
Signed-off-by: Pavel Machek <pavel@ucw.cz>
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26..da08226 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -263,14 +263,14 @@ config MACH_NOKIA_N8X0
select MACH_NOKIA_N810_WIMAX
config MACH_NOKIA_RM680
- bool "Nokia RM-680/696 board"
+ bool "Nokia N9/N950 (RM-680/696) phones"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
select MACH_NOKIA_RM696
config MACH_NOKIA_RX51
- bool "Nokia RX-51 board"
+ bool "Nokia N900 phone (RX-51)"
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 0ad1bb3b..26965f3 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
/*
- * Board support file for Nokia RM-680/696.
+ * Board support file for Nokia N9/N950 (aka RM-680/696).
*
* Copyright (C) 2010 Nokia
*
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 345dd93..b60ca9d 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-omap2/board-rx51.c
+ * Board support file for Nokia N900 (aka RX-51).
*
* Copyright (C) 2007, 2008 Nokia
*
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply related
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