* ttySAC0 or ttyS0 in 3.6.x ARM Linux?
From: woody @ 2012-11-15 7:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
In the 3.6.6 ARM kernel, should I use ttySAC0 or ttyS0 to specify the
'console' kernel command line?
Thanks.
--
woody
I can't go back to yesterday - because I was a different person then.
^ permalink raw reply
* [PATCH v2 2/3] serial: mxs-auart: add the DMA support for mx28
From: Lauri Hintsala @ 2012-11-15 7:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A45F83.1010009@freescale.com>
Hi,
On 11/15/2012 05:20 AM, Huang Shijie wrote:
> ? 2012?11?13? 17:42, Lauri Hintsala ??:
>> Hi Huang,
>>
>> DMA support doesn't work with latest stable v3.6.5 or development
>> 3.7-rc5 kernels. I get following error message when I open the serial
>> port /dev/ttyAPP0:
>>
>> [ 48.730000] mxs-auart 8006a000.serial: step 1 error
>> [ 48.750000] mxs-auart 8006a000.serial: We can not start up the DMA.
>>
> I tested this patch set in imx28-evk board Rev C with linux-next-20121114.
> it works fine.
>
> Maybe you can try the linux-next code.
I tested linux-next-20121114 on apx4devkit (imx28 based device) and I
got the same error message:
# stty -F /dev/ttyAPP0 crtscts; microcom /dev/ttyAPP0 -s 115200
[ 133.710000] mxs-auart 8006a000.serial: step 1 error
[ 133.720000] mxs-auart 8006a000.serial: We can not start up the DMA.
> About the flow control:
> If we do not enable the HW flow control, the data may lost. And I do not
> know how to handle with the Xon/Xoff when the DMA is supported.
I do not have the answer but it is already implemented in Freescale's
reference kernel
(http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/serial/mxs-auart.c?h=imx_2.6.35_11.09.01).
So I think it is possible to handle all data without HW flow control.
Best Regards,
Lauri Hintsala
^ permalink raw reply
* [PATCH v7] Network driver for the Armada 370 and Armada XP ARM Marvell SoCs
From: Thomas Petazzoni @ 2012-11-15 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114.215922.1242337385782766449.davem@davemloft.net>
David,
On Wed, 14 Nov 2012 21:59:22 -0500 (EST), David Miller wrote:
> From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Date: Wed, 14 Nov 2012 15:56:44 +0100
>
> > The previous versions of this patch set have been sent on September
> > 4th (v1), October 11th (v2), October 23rd (v3), October 26th (v4),
> > November 12th (v5), November 13th (v6) and now comes the v7 of the
> > driver. The number of comments over the last versions have been really
> > small, and I would really appreciate if this driver could land into
> > the 3.8 kernel release.
>
> I can't apply this patch to net-next, because for one thing there
> are missing dependencies. For example, the file:
>
> arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
>
> doesn't exist there, therefore patch #6 won't apply.
Yes, this is expected: those patches were provided to allow people to
test the driver on the OpenBlocks platform, which is much more widely
available than the Armada XP evaluation board from Marvell.
Would you mind if we take, with your Ack, the network driver through
the arm-soc tree, so that we can carry the related patches modifying
the Device Tree and so on? If not, then I'll send you a pull request
with just the drivers/net changes, and we'll integrate the ARM-related
changes through the arm-soc tree, in which we will have the necessary
dependencies. I'm fine with any of those solutions.
Thanks,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCHv2] i2c: omap: Move the remove constraint
From: Shubhrajyoti D @ 2012-11-15 7:34 UTC (permalink / raw)
To: linux-arm-kernel
Currently we just queue the transfer and release the
qos constraints, however we donot wait for the transfer
to complete to release the constraint. Move the remove
constraint after the bus busy as we are sure that the
transfers are completed by then.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
---
v2: rebase to the for-next branch
drivers/i2c/busses/i2c-omap.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 482c63d..fabcbe1 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -654,13 +654,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
break;
}
- if (dev->set_mpu_wkup_lat != NULL)
- dev->set_mpu_wkup_lat(dev->dev, -1);
-
if (r == 0)
r = num;
omap_i2c_wait_for_bb(dev);
+
+ if (dev->set_mpu_wkup_lat != NULL)
+ dev->set_mpu_wkup_lat(dev->dev, -1);
+
out:
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/4] pinctrl: dove: Prevent NULL dereference if of_match_device returns NULL
From: Thomas Petazzoni @ 2012-11-15 7:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352955096.6793.1.camel@phoenix>
Dear Axel Lin,
On Thu, 15 Nov 2012 12:51:36 +0800, Axel Lin wrote:
> of_match_device() may return NULL.
>
> Signed-off-by: Axel Lin <axel.lin@ingics.com>
Could you detail under what conditions of_match_device() may return
NULL in the specific case of this driver? This of_match_device() call
is using the same dove_pinctrl_of_match array that is used to ->probe()
this driver. So I don't see how you can get into ->probe() without
having a matching entry.
Am I missing something?
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v7] Network driver for the Armada 370 and Armada XP ARM Marvell SoCs
From: David Miller @ 2012-11-15 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115083319.76483256@skate>
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Thu, 15 Nov 2012 08:33:19 +0100
> Would you mind if we take, with your Ack, the network driver through
> the arm-soc tree, so that we can carry the related patches modifying
> the Device Tree and so on? If not, then I'll send you a pull request
> with just the drivers/net changes, and we'll integrate the ARM-related
> changes through the arm-soc tree, in which we will have the necessary
> dependencies. I'm fine with any of those solutions.
Sure, no problem, take it via the ARM tree:
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply
* [PATCH V2 0/3] ARM: tegra: add speedo identification for T20/T30
From: Danny Huang @ 2012-11-15 7:42 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds speedo identification functionality for tegra
T20 and T30. It reads speedo value from fuse and chooses CPU and core
process ID by checking speedo corner tables.
V2:
* Split spare fuse related changes to a separate patch
* Keep original fuse init flow on an unknown chip
* Change size check of speedo cornor table
* Set speedo id to 0 with unknown chip revision/SKU
* Set process id to 0 when speedo value out of range
Danny Huang (3):
ARM: tegra: flexible spare fuse read function
ARM: tegra: Add speedo-based process identification
ARM: tegra: T30 speedo-based process identification
arch/arm/mach-tegra/Makefile | 2 +
arch/arm/mach-tegra/fuse.c | 49 ++++--
arch/arm/mach-tegra/fuse.h | 16 ++
arch/arm/mach-tegra/tegra20_speedo.c | 109 +++++++++++++
arch/arm/mach-tegra/tegra30_speedo.c | 292 +++++++++++++++++++++++++++++++++++
5 files changed, 457 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/mach-tegra/tegra20_speedo.c
create mode 100644 arch/arm/mach-tegra/tegra30_speedo.c
--
1.8.0
^ permalink raw reply
* [PATCH V2 1/3] ARM: tegra: flexible spare fuse read function
From: Danny Huang @ 2012-11-15 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352965354-650-1-git-send-email-dahuang@nvidia.com>
Change the spare fuse base from a definition to a variable.
It provides flexibilty to read spare fuse on different chip.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
---
arch/arm/mach-tegra/fuse.c | 19 ++++++++++++-------
arch/arm/mach-tegra/fuse.h | 2 ++
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 6c752e8..bd19c2f 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -28,7 +28,8 @@
#define FUSE_UID_LOW 0x108
#define FUSE_UID_HIGH 0x10c
#define FUSE_SKU_INFO 0x110
-#define FUSE_SPARE_BIT 0x200
+
+#define TEGRA20_FUSE_SPARE_BIT 0x200
int tegra_sku_id;
int tegra_cpu_process_id;
@@ -36,6 +37,8 @@ int tegra_core_process_id;
int tegra_chip_id;
enum tegra_revision tegra_revision;
+static int tegra_fuse_spare_bit;
+
/* The BCT to use at boot is specified by board straps that can be read
* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
*/
@@ -56,14 +59,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
[TEGRA_REVISION_A04] = "A04",
};
-static inline u32 tegra_fuse_readl(unsigned long offset)
+u32 tegra_fuse_readl(unsigned long offset)
{
return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}
-static inline bool get_spare_fuse(int bit)
+bool tegra_spare_fuse(int bit)
{
- return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
+ return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
}
static enum tegra_revision tegra_get_revision(u32 id)
@@ -77,7 +80,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
return TEGRA_REVISION_A02;
case 3:
if (tegra_chip_id == TEGRA20 &&
- (get_spare_fuse(18) || get_spare_fuse(19)))
+ (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
return TEGRA_REVISION_A03p;
else
return TEGRA_REVISION_A03;
@@ -99,10 +102,12 @@ void tegra_init_fuse(void)
reg = tegra_fuse_readl(FUSE_SKU_INFO);
tegra_sku_id = reg & 0xFF;
- reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+ tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+
+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
tegra_cpu_process_id = (reg >> 6) & 3;
- reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
tegra_core_process_id = (reg >> 12) & 3;
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index d2107b2..aef1223 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -48,5 +48,7 @@ extern int tegra_bct_strapping;
unsigned long long tegra_chip_uid(void);
void tegra_init_fuse(void);
+bool tegra_spare_fuse(int bit);
+u32 tegra_fuse_readl(unsigned long offset);
#endif
--
1.8.0
^ permalink raw reply related
* [PATCH V2 2/3] ARM: tegra: Add speedo-based process identification
From: Danny Huang @ 2012-11-15 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352965354-650-1-git-send-email-dahuang@nvidia.com>
Detect CPU and core process ID by checking speedo corner tables.
This can provide a more accurate process ID.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/fuse.c | 31 +++++++---
arch/arm/mach-tegra/fuse.h | 7 +++
arch/arm/mach-tegra/tegra20_speedo.c | 109 +++++++++++++++++++++++++++++++++++
4 files changed, 140 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/mach-tegra/tegra20_speedo.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6f224f7..75418f1 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
ifeq ($(CONFIG_CPU_IDLE),y)
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index bd19c2f..9fd02c5 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -35,9 +35,11 @@ int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
+int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;
static int tegra_fuse_spare_bit;
+static void (*tegra_init_speedo_data)(void);
/* The BCT to use at boot is specified by board straps that can be read
* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
@@ -91,6 +93,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
}
}
+static void tegra_get_process_id(void)
+{
+ u32 reg;
+
+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+ tegra_cpu_process_id = (reg >> 6) & 3;
+ reg = tegra_fuse_readl(tegra_fuse_spare_bit);
+ tegra_core_process_id = (reg >> 12) & 3;
+}
+
void tegra_init_fuse(void)
{
u32 id;
@@ -102,21 +114,24 @@ void tegra_init_fuse(void)
reg = tegra_fuse_readl(FUSE_SKU_INFO);
tegra_sku_id = reg & 0xFF;
- tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
-
- reg = tegra_fuse_readl(tegra_fuse_spare_bit);
- tegra_cpu_process_id = (reg >> 6) & 3;
-
- reg = tegra_fuse_readl(tegra_fuse_spare_bit);
- tegra_core_process_id = (reg >> 12) & 3;
-
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
tegra_chip_id = (id >> 8) & 0xff;
+ tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
+
+ switch (tegra_chip_id) {
+ case TEGRA20:
+ tegra_init_speedo_data = &tegra20_init_speedo_data;
+ break;
+ default:
+ tegra_init_speedo_data = &tegra_get_process_id;
+ }
+
tegra_revision = tegra_get_revision(id);
+ tegra_init_speedo_data();
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aef1223..7347c88 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -42,6 +42,7 @@ extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
extern int tegra_chip_id;
+extern int tegra_soc_speedo_id;
extern enum tegra_revision tegra_revision;
extern int tegra_bct_strapping;
@@ -51,4 +52,10 @@ void tegra_init_fuse(void);
bool tegra_spare_fuse(int bit);
u32 tegra_fuse_readl(unsigned long offset);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void tegra20_init_speedo_data(void);
+#else
+static inline void tegra20_init_speedo_data(void) {}
+#endif
+
#endif
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c
new file mode 100644
index 0000000..97feba3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_speedo.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CPU_SPEEDO_LSBIT 20
+#define CPU_SPEEDO_MSBIT 29
+#define CPU_SPEEDO_REDUND_LSBIT 30
+#define CPU_SPEEDO_REDUND_MSBIT 39
+#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
+
+#define CORE_SPEEDO_LSBIT 40
+#define CORE_SPEEDO_MSBIT 47
+#define CORE_SPEEDO_REDUND_LSBIT 48
+#define CORE_SPEEDO_REDUND_MSBIT 55
+#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
+
+#define SPEEDO_MULT 4
+
+#define PROCESS_CORNERS_NUM 4
+
+#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
+#define SPEEDO_ID_SELECT_1(sku) \
+ (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
+ ((sku) != 27) && ((sku) != 28))
+
+enum {
+ SPEEDO_ID_0,
+ SPEEDO_ID_1,
+ SPEEDO_ID_2,
+ SPEEDO_ID_COUNT,
+};
+
+static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
+ {315, 366, 420, UINT_MAX},
+ {303, 368, 419, UINT_MAX},
+ {316, 331, 383, UINT_MAX},
+};
+
+static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
+ {165, 195, 224, UINT_MAX},
+ {165, 195, 224, UINT_MAX},
+ {165, 195, 224, UINT_MAX},
+};
+
+void tegra20_init_speedo_data(void)
+{
+ u32 reg;
+ u32 val;
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
+
+ if (SPEEDO_ID_SELECT_0(tegra_revision))
+ tegra_soc_speedo_id = SPEEDO_ID_0;
+ else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
+ tegra_soc_speedo_id = SPEEDO_ID_1;
+ else
+ tegra_soc_speedo_id = SPEEDO_ID_2;
+
+ val = 0;
+ for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
+ reg = tegra_spare_fuse(i) |
+ tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
+ val = (val << 1) | (reg & 0x1);
+ }
+ val = val * SPEEDO_MULT;
+ pr_debug("%s CPU speedo value %u\n", __func__, val);
+
+ for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+ if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
+ break;
+ }
+ tegra_cpu_process_id = i;
+
+ val = 0;
+ for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
+ reg = tegra_spare_fuse(i) |
+ tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
+ val = (val << 1) | (reg & 0x1);
+ }
+ val = val * SPEEDO_MULT;
+ pr_debug("%s Core speedo value %u\n", __func__, val);
+
+ for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+ if (val <= core_process_speedos[tegra_soc_speedo_id][i])
+ break;
+ }
+ tegra_core_process_id = i;
+
+ pr_info("Tegra2 Soc Speedo ID %d", tegra_soc_speedo_id);
+}
--
1.8.0
^ permalink raw reply related
* [PATCH V2 3/3] ARM: tegra: T30 speedo-based process identification
From: Danny Huang @ 2012-11-15 7:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352965354-650-1-git-send-email-dahuang@nvidia.com>
This patch adds speedo-based process identification support for T30.
Signed-off-by: Danny Huang <dahuang@nvidia.com>
---
arch/arm/mach-tegra/Makefile | 1 +
arch/arm/mach-tegra/fuse.c | 11 +-
arch/arm/mach-tegra/fuse.h | 7 +
arch/arm/mach-tegra/tegra30_speedo.c | 292 +++++++++++++++++++++++++++++++++++
4 files changed, 309 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-tegra/tegra30_speedo.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 75418f1..0979e8b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
endif
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 9fd02c5..8121742 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -30,11 +30,13 @@
#define FUSE_SKU_INFO 0x110
#define TEGRA20_FUSE_SPARE_BIT 0x200
+#define TEGRA30_FUSE_SPARE_BIT 0x244
int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
+int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;
@@ -120,13 +122,18 @@ void tegra_init_fuse(void)
id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
tegra_chip_id = (id >> 8) & 0xff;
- tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
-
switch (tegra_chip_id) {
case TEGRA20:
+ tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
tegra_init_speedo_data = &tegra20_init_speedo_data;
break;
+ case TEGRA30:
+ tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
+ tegra_init_speedo_data = &tegra30_init_speedo_data;
+ break;
default:
+ pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
+ tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
tegra_init_speedo_data = &tegra_get_process_id;
}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 7347c88..ff1383d 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -42,6 +42,7 @@ extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
extern int tegra_chip_id;
+extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
extern int tegra_soc_speedo_id;
extern enum tegra_revision tegra_revision;
@@ -58,4 +59,10 @@ void tegra20_init_speedo_data(void);
static inline void tegra20_init_speedo_data(void) {}
#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void tegra30_init_speedo_data(void);
+#else
+static inline void tegra30_init_speedo_data(void) {}
+#endif
+
#endif
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c
new file mode 100644
index 0000000..9dc76ad
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_speedo.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM 1
+#define CPU_PROCESS_CORNERS_NUM 6
+
+#define FUSE_SPEEDO_CALIB_0 0x114
+#define FUSE_PACKAGE_INFO 0X1FC
+#define FUSE_TEST_PROG_VER 0X128
+
+#define G_SPEEDO_BIT_MINUS1 58
+#define G_SPEEDO_BIT_MINUS1_R 59
+#define G_SPEEDO_BIT_MINUS2 60
+#define G_SPEEDO_BIT_MINUS2_R 61
+#define LP_SPEEDO_BIT_MINUS1 62
+#define LP_SPEEDO_BIT_MINUS1_R 63
+#define LP_SPEEDO_BIT_MINUS2 64
+#define LP_SPEEDO_BIT_MINUS2_R 65
+
+enum {
+ THRESHOLD_INDEX_0,
+ THRESHOLD_INDEX_1,
+ THRESHOLD_INDEX_2,
+ THRESHOLD_INDEX_3,
+ THRESHOLD_INDEX_4,
+ THRESHOLD_INDEX_5,
+ THRESHOLD_INDEX_6,
+ THRESHOLD_INDEX_7,
+ THRESHOLD_INDEX_8,
+ THRESHOLD_INDEX_9,
+ THRESHOLD_INDEX_10,
+ THRESHOLD_INDEX_11,
+ THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+ {180},
+ {170},
+ {195},
+ {180},
+ {168},
+ {192},
+ {180},
+ {170},
+ {195},
+ {180},
+ {180},
+ {180},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+ {306, 338, 360, 376, UINT_MAX},
+ {295, 336, 358, 375, UINT_MAX},
+ {325, 325, 358, 375, UINT_MAX},
+ {325, 325, 358, 375, UINT_MAX},
+ {292, 324, 348, 364, UINT_MAX},
+ {324, 324, 348, 364, UINT_MAX},
+ {324, 324, 348, 364, UINT_MAX},
+ {295, 336, 358, 375, UINT_MAX},
+ {358, 358, 358, 358, 397, UINT_MAX},
+ {364, 364, 364, 364, 397, UINT_MAX},
+ {295, 336, 358, 375, 391, UINT_MAX},
+ {295, 336, 358, 375, 391, UINT_MAX},
+};
+
+static int threshold_index;
+static int package_id;
+
+static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
+{
+ u32 reg;
+ int ate_ver;
+ int bit_minus1;
+ int bit_minus2;
+
+ reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
+
+ *speedo_lp = (reg & 0xFFFF) * 4;
+ *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
+
+ ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
+ pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
+
+ if (ate_ver >= 26) {
+ bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
+ bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
+ bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
+ bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
+ *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
+
+ bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
+ bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
+ bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
+ bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
+ *speedo_g |= (bit_minus1 << 1) | bit_minus2;
+ } else {
+ *speedo_lp |= 0x3;
+ *speedo_g |= 0x3;
+ }
+}
+
+static void rev_sku_to_speedo_ids(int rev, int sku)
+{
+ switch (rev) {
+ case TEGRA_REVISION_A01:
+ tegra_cpu_speedo_id = 0;
+ tegra_soc_speedo_id = 0;
+ threshold_index = THRESHOLD_INDEX_0;
+ break;
+ case TEGRA_REVISION_A02:
+ case TEGRA_REVISION_A03:
+ switch (sku) {
+ case 0x87:
+ case 0x82:
+ tegra_cpu_speedo_id = 1;
+ tegra_soc_speedo_id = 1;
+ threshold_index = THRESHOLD_INDEX_1;
+ break;
+ case 0x81:
+ switch (package_id) {
+ case 1:
+ tegra_cpu_speedo_id = 2;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_2;
+ break;
+ case 2:
+ tegra_cpu_speedo_id = 4;
+ tegra_soc_speedo_id = 1;
+ threshold_index = THRESHOLD_INDEX_7;
+ break;
+ default:
+ pr_err("Tegra3: Unknown pkg %d\n", package_id);
+ BUG();
+ break;
+ }
+ break;
+ case 0x80:
+ switch (package_id) {
+ case 1:
+ tegra_cpu_speedo_id = 5;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_8;
+ break;
+ case 2:
+ tegra_cpu_speedo_id = 6;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_9;
+ break;
+ default:
+ pr_err("Tegra3: Unknown pkg %d\n", package_id);
+ BUG();
+ break;
+ }
+ break;
+ case 0x83:
+ switch (package_id) {
+ case 1:
+ tegra_cpu_speedo_id = 7;
+ tegra_soc_speedo_id = 1;
+ threshold_index = THRESHOLD_INDEX_10;
+ break;
+ case 2:
+ tegra_cpu_speedo_id = 3;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_3;
+ break;
+ default:
+ pr_err("Tegra3: Unknown pkg %d\n", package_id);
+ BUG();
+ break;
+ }
+ break;
+ case 0x8F:
+ tegra_cpu_speedo_id = 8;
+ tegra_soc_speedo_id = 1;
+ threshold_index = THRESHOLD_INDEX_11;
+ break;
+ case 0x08:
+ tegra_cpu_speedo_id = 1;
+ tegra_soc_speedo_id = 1;
+ threshold_index = THRESHOLD_INDEX_4;
+ break;
+ case 0x02:
+ tegra_cpu_speedo_id = 2;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_5;
+ break;
+ case 0x04:
+ tegra_cpu_speedo_id = 3;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_6;
+ break;
+ case 0:
+ switch (package_id) {
+ case 1:
+ tegra_cpu_speedo_id = 2;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_2;
+ break;
+ case 2:
+ tegra_cpu_speedo_id = 3;
+ tegra_soc_speedo_id = 2;
+ threshold_index = THRESHOLD_INDEX_3;
+ break;
+ default:
+ pr_err("Tegra3: Unknown pkg %d\n", package_id);
+ BUG();
+ break;
+ }
+ break;
+ default:
+ pr_warn("Tegra3: Unknown SKU %d\n", sku);
+ tegra_cpu_speedo_id = 0;
+ tegra_soc_speedo_id = 0;
+ threshold_index = THRESHOLD_INDEX_0;
+ break;
+ }
+ break;
+ default:
+ pr_warn("Tegra3: Unknown chip rev %d\n", rev);
+ tegra_cpu_speedo_id = 0;
+ tegra_soc_speedo_id = 0;
+ threshold_index = THRESHOLD_INDEX_0;
+ break;
+ }
+}
+
+void tegra30_init_speedo_data(void)
+{
+ u32 cpu_speedo_val;
+ u32 core_speedo_val;
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+ THRESHOLD_INDEX_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+ THRESHOLD_INDEX_COUNT);
+
+ package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
+
+ rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
+ fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
+ pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
+ pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
+
+ for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
+ if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
+ break;
+ }
+ tegra_cpu_process_id = i - 1;
+
+ if (tegra_cpu_process_id == -1) {
+ pr_warn("Tegra3: CPU speedo value %3d out of range",
+ cpu_speedo_val);
+ tegra_cpu_process_id = 0;
+ tegra_cpu_speedo_id = 1;
+ }
+
+ for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
+ if (core_speedo_val < core_process_speedos[threshold_index][i])
+ break;
+ }
+ tegra_core_process_id = i - 1;
+
+ if (tegra_core_process_id == -1) {
+ pr_warn("Tegra3: CORE speedo value %3d out of range",
+ core_speedo_val);
+ tegra_core_process_id = 0;
+ tegra_soc_speedo_id = 1;
+ }
+
+ pr_info("Tegra3: CPU Speedo ID %d, Soc Speedo ID %d",
+ tegra_cpu_speedo_id, tegra_soc_speedo_id);
+}
--
1.8.0
^ permalink raw reply related
* [PATCH v7] Network driver for the Armada 370 and Armada XP ARM Marvell SoCs
From: Thomas Petazzoni @ 2012-11-15 8:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121115.024213.1356436436054345008.davem@davemloft.net>
David,
On Thu, 15 Nov 2012 02:42:13 -0500 (EST), David Miller wrote:
> From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Date: Thu, 15 Nov 2012 08:33:19 +0100
>
> > Would you mind if we take, with your Ack, the network driver through
> > the arm-soc tree, so that we can carry the related patches modifying
> > the Device Tree and so on? If not, then I'll send you a pull request
> > with just the drivers/net changes, and we'll integrate the ARM-related
> > changes through the arm-soc tree, in which we will have the necessary
> > dependencies. I'm fine with any of those solutions.
>
> Sure, no problem, take it via the ARM tree:
>
> Acked-by: David S. Miller <davem@davemloft.net>
Excellent, thanks!
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/3] OF: Add helper for matching against linux, stdout-path
From: Sascha Hauer @ 2012-11-15 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACxGe6uW+XN6RDnP+8QFXaCYqqPZO4dZM_aynR6AVMYZT=KuMg@mail.gmail.com>
On Wed, Nov 14, 2012 at 08:49:54PM +0000, Grant Likely wrote:
> > +int of_device_is_stdout_path(struct device_node *dn)
> > +{
> > + const char *name;
> > +
> > + name = of_get_property(of_chosen, "linux,stdout-path", NULL);
> > + if (name == NULL)
> > + return 0;
> > +
> > + if (dn == of_find_node_by_path(name))
>
> need to of_node_put() the return value of of_find_node_by_path()
>
> > + return 1;
> > +
> > + return 0;
> > +}
>
> Hi Sascha,
>
> I'm fine with the helper, but there really is no need for a completely
> separate .c file. Just put it in drivers/of/base.c.
Agreed.
Thanks,
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] ARM: OMAP2+: omap_twl: Change TWL4030_MODULE_PM_RECEIVER to TWL_MODULE_PM_RECEIVER
From: Peter Ujfalusi @ 2012-11-15 8:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352799152-20980-1-git-send-email-peter.ujfalusi@ti.com>
Hi Tony,
On 11/13/2012 10:32 AM, Peter Ujfalusi wrote:
> To facilitate upcoming cleanup in twl stack.
> No functional change.
Would you please consider this patch for 3.8? It would shorten the time I'll
need to progress on the cleanup regarding to twl-core greatly.
Thank you,
P?ter
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
> arch/arm/mach-omap2/omap_twl.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
> index 2bf35dc..018abb4 100644
> --- a/arch/arm/mach-omap2/omap_twl.c
> +++ b/arch/arm/mach-omap2/omap_twl.c
> @@ -337,8 +337,8 @@ int __init omap3_twl_set_sr_bit(bool enable)
> if (twl_sr_enable_autoinit)
> pr_warning("%s: unexpected multiple calls\n", __func__);
>
> - ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
> - TWL4030_DCDC_GLOBAL_CFG);
> + ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
> + TWL4030_DCDC_GLOBAL_CFG);
> if (ret)
> goto err;
>
> @@ -347,8 +347,8 @@ int __init omap3_twl_set_sr_bit(bool enable)
> else
> temp &= ~SMARTREFLEX_ENABLE;
>
> - ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
> - TWL4030_DCDC_GLOBAL_CFG);
> + ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
> + TWL4030_DCDC_GLOBAL_CFG);
> if (!ret) {
> twl_sr_enable_autoinit = true;
> return 0;
>
^ permalink raw reply
* [PATCH resend] rtc: i.MX dryice: Add devicetree support
From: Sascha Hauer @ 2012-11-15 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121114145253.aa79fb48.akpm@linux-foundation.org>
On Wed, Nov 14, 2012 at 02:52:53PM -0800, Andrew Morton wrote:
> On Mon, 12 Nov 2012 09:42:50 +0100
> Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> > Add devicetree probing, fixing some whitespace damage along the way.
> >
>
> I've already merged the below. It has better code but a little less
> documentation:
Oops, missed that. Too many RTCs...
Sorry for the noise.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v2 1/2] ARM: mx27: Add VPU support
From: Sascha Hauer @ 2012-11-15 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352917238-29694-1-git-send-email-fabio.estevam@freescale.com>
On Wed, Nov 14, 2012 at 04:20:36PM -0200, Fabio Estevam wrote:
> mx27 has a VPU (Video Processing Unit) block that allows doing H264/MPEG4
> decoding and encoding in hardware.
>
> Add support for it in a common SoC file instead of per board file.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Javier,
>
> I removed dma_declare_coherent_memory call, as per Sascha's suggestion on my
> first submission of adding mx27pdk VPU support. Hope this is ok with you.
>
> Changes since v1:
> - Call imx27_add_coda() on a common mx27 location instead of per board.
> arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 18 ------------------
> arch/arm/mach-imx/mm-imx27.c | 3 ++-
> 2 files changed, 2 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index b744226..ee9cbff 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -434,23 +434,6 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
> .flags = IMX_SSI_DMA | IMX_SSI_SYN,
> };
>
> -/* coda */
> -
> -static void __init visstrim_coda_init(void)
> -{
> - struct platform_device *pdev;
> - int dma;
> -
> - pdev = imx27_add_coda();
> - dma = dma_declare_coherent_memory(&pdev->dev,
> - mx2_camera_base + MX2_CAMERA_BUF_SIZE,
> - mx2_camera_base + MX2_CAMERA_BUF_SIZE,
> - MX2_CAMERA_BUF_SIZE,
> - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> - if (!(dma & DMA_MEMORY_MAP))
> - return;
> -}
> -
> /* DMA deinterlace */
> static struct platform_device visstrim_deinterlace = {
> .name = "m2m-deinterlace",
> @@ -548,7 +531,6 @@ static void __init visstrim_m10_board_init(void)
> gpio_led_register_device(0, &visstrim_m10_led_data);
> visstrim_deinterlace_init();
> visstrim_camera_init();
> - visstrim_coda_init();
> }
>
> static void __init visstrim_m10_timer_init(void)
> diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
> index 4f1be65..fddadb1 100644
> --- a/arch/arm/mach-imx/mm-imx27.c
> +++ b/arch/arm/mach-imx/mm-imx27.c
> @@ -25,9 +25,9 @@
> #include <asm/mach/map.h>
>
> #include "common.h"
> -#include "devices/devices-common.h"
> #include "hardware.h"
> #include "iomux-v1.h"
> +#include "devices-imx27.h"
>
> /* MX27 memory map definition */
> static struct map_desc imx27_io_desc[] __initdata = {
> @@ -98,4 +98,5 @@ void __init imx27_soc_init(void)
> /* imx27 has the imx21 type audmux */
> platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
> ARRAY_SIZE(imx27_audmux_res));
> + imx27_add_coda();
As Eric mentioned this may lead to problems on the i.MX27L without VPU.
Do you have the possibility to test this?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH] ARM: dts: add board dts file for Exynos4412 based SMDK board
From: Thomas Abraham @ 2012-11-15 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0bef01cdbc11$cf1bbd60$6d533820$%kim@samsung.com>
On 6 November 2012 16:58, Kukjin Kim <kgene.kim@samsung.com> wrote:
> Thomas Abraham wrote:
>>
>> Add a minimal board dts file for Samsung Exynos4412 based SMDK board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> This patch depends the on the following patch posted by Tomasz Figa.
>> "ARM: dts: exynos4: Add support for Exynos4x12 SoCs"
>>
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/exynos4412-smdk4412.dts | 45
>> +++++++++++++++++++++++++++++
>> 2 files changed, 46 insertions(+), 0 deletions(-)
>> create mode 100644 arch/arm/boot/dts/exynos4412-smdk4412.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index f37cf9f..36488a5 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
>> dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>> exynos4210-smdkv310.dtb \
>> exynos4210-trats.dtb \
>> + exynos4412-smdk4412.dtb \
>> exynos5250-smdk5250.dtb
>> dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
>> dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
>> diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
>> b/arch/arm/boot/dts/exynos4412-smdk4412.dts
>> new file mode 100644
>> index 0000000..f05bf57
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
>> @@ -0,0 +1,45 @@
>> +/*
>> + * Samsung's Exynos4412 based SMDK board device tree source
>> + *
>> + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Device tree source file for Samsung's SMDK4412 board which is based on
>> + * Samsung's Exynos4412 SoC.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/dts-v1/;
>> +/include/ "exynos4412.dtsi"
>> +
>> +/ {
>> + model = "Samsung SMDK evaluation board based on Exynos4412";
>> + compatible = "samsung,smdk4412", "samsung,exynos4412";
>> +
>> + memory {
>> + reg = <0x40000000 0x40000000>;
>> + };
>> +
>> + chosen {
>> + bootargs ="root=/dev/ram0 rw ramdisk=8192
>> initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
>> + };
>> +
>> + serial at 13800000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13810000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13820000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13830000 {
>> + status = "okay";
>> + };
>> +};
>> --
>> 1.6.6.rc2
>
> Looks good to me, will apply.
>
> BTW, its default console is ttySAC1 not ttySAC2?
Thanks Mr. Kim. There is support for both ttySAC1 and ttySAC2 as uart
ports. There are corresponding switches on the board that have to be
set. But the default setting is always to use ttySAC1.
Thanks,
Thomas.
^ permalink raw reply
* [PATCHv2] i2c: omap: Move the remove constraint
From: Jean Pihet @ 2012-11-15 8:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352964883-9846-1-git-send-email-shubhrajyoti@ti.com>
Hi Shubhrajyoti,
On Thu, Nov 15, 2012 at 8:34 AM, Shubhrajyoti D <shubhrajyoti@ti.com> wrote:
> Currently we just queue the transfer and release the
> qos constraints, however we donot wait for the transfer
Typo: donot
> to complete to release the constraint. Move the remove
> constraint after the bus busy as we are sure that the
> transfers are completed by then.
>
> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Looks good!
Acked-by: Jean Pihet <j-pihet@ti.com>
Regards,
Jean
> ---
> v2: rebase to the for-next branch
>
> drivers/i2c/busses/i2c-omap.c | 7 ++++---
> 1 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
> index 482c63d..fabcbe1 100644
> --- a/drivers/i2c/busses/i2c-omap.c
> +++ b/drivers/i2c/busses/i2c-omap.c
> @@ -654,13 +654,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> break;
> }
>
> - if (dev->set_mpu_wkup_lat != NULL)
> - dev->set_mpu_wkup_lat(dev->dev, -1);
> -
> if (r == 0)
> r = num;
>
> omap_i2c_wait_for_bb(dev);
> +
> + if (dev->set_mpu_wkup_lat != NULL)
> + dev->set_mpu_wkup_lat(dev->dev, -1);
> +
> out:
> pm_runtime_mark_last_busy(dev->dev);
> pm_runtime_put_autosuspend(dev->dev);
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] ARM: dts: add board dts file for Exynos4412 based SMDK board
From: Thomas Abraham @ 2012-11-15 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1629120.eNASZVgxGi@amdc1227>
Hi Tomasz,
Thanks for your comments.
On 12 November 2012 19:37, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Thomas,
>
> On Saturday 03 of November 2012 20:19:32 Thomas Abraham wrote:
>> Add a minimal board dts file for Samsung Exynos4412 based SMDK board.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> This patch depends the on the following patch posted by Tomasz Figa.
>> "ARM: dts: exynos4: Add support for Exynos4x12 SoCs"
>>
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/exynos4412-smdk4412.dts | 45
>> +++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 0
>> deletions(-)
>> create mode 100644 arch/arm/boot/dts/exynos4412-smdk4412.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index f37cf9f..36488a5 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
>> dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
>> exynos4210-smdkv310.dtb \
>> exynos4210-trats.dtb \
>> + exynos4412-smdk4412.dtb \
>> exynos5250-smdk5250.dtb
>> dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
>> dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
>> diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts
>> b/arch/arm/boot/dts/exynos4412-smdk4412.dts new file mode 100644
>> index 0000000..f05bf57
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
>> @@ -0,0 +1,45 @@
>> +/*
>> + * Samsung's Exynos4412 based SMDK board device tree source
>> + *
>> + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Device tree source file for Samsung's SMDK4412 board which is based
>> on + * Samsung's Exynos4412 SoC.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> +*/
>> +
>> +/dts-v1/;
>> +/include/ "exynos4412.dtsi"
>> +
>> +/ {
>> + model = "Samsung SMDK evaluation board based on Exynos4412";
>> + compatible = "samsung,smdk4412", "samsung,exynos4412";
>> +
>> + memory {
>> + reg = <0x40000000 0x40000000>;
>> + };
>
> This will not boot, because section size limit is set to 256 MiB.
>
> It might work with CONFIG_ARM_ATAG_DTB_COMPAT enabled, because the memory
> configuration from DT is ignored and values from ATAGs are taken instead.
>
> I suggest you to change it to 4 banks of 256 MiB.
Thanks for pointing this out. So are there any existing exynos based
platforms that use sparse mem? If not, we should probably remove the
section length configuration itself for mach-exynos. I suspect this
setting might not help with the single kernel image support as well.
Thanks,
Thomas.
>
>> + chosen {
>> + bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M
>> console=ttySAC1,115200 init=/linuxrc"; + };
>> +
>> + serial at 13800000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13810000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13820000 {
>> + status = "okay";
>> + };
>> +
>> + serial at 13830000 {
>> + status = "okay";
>> + };
>> +};
>
> Otherwise looks fine.
>
> Best regards,
> --
> Tomasz Figa
> Samsung Poland R&D Center
> SW Solution Development, Linux Platform
>
^ permalink raw reply
* [PATCH RESEND 3/4] pinctrl: at91: Prevent NULL dereference if of_match_device returns NULL
From: Nicolas Ferre @ 2012-11-15 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1352955480.6793.8.camel@phoenix>
On 11/15/2012 05:58 AM, Axel Lin :
> of_match_device() may return NULL.
>
> Signed-off-by: Axel Lin <axel.lin@ingics.com>
Seems sensible,
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> This resend CC Jean-Christophe.
>
> drivers/pinctrl/pinctrl-at91.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
> index 8490a55..32006c8 100644
> --- a/drivers/pinctrl/pinctrl-at91.c
> +++ b/drivers/pinctrl/pinctrl-at91.c
> @@ -829,13 +829,18 @@ static int __devinit at91_pinctrl_probe_dt(struct platform_device *pdev,
> uint32_t *tmp;
> struct device_node *np = pdev->dev.of_node;
> struct device_node *child;
> + const struct of_device_id *match;
>
> if (!np)
> return -ENODEV;
>
> + match = of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
> + if (!match)
> + return -ENODEV;
> +
> info->dev = &pdev->dev;
> - info->ops = (struct at91_pinctrl_mux_ops*)
> - of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
> + info->ops = (struct at91_pinctrl_mux_ops *) match->data;
> +
> at91_pinctrl_child_count(info, np);
>
> if (info->nbanks < 1) {
> @@ -1359,6 +1364,7 @@ static struct of_device_id at91_gpio_of_match[] __devinitdata = {
> static int __devinit at91_gpio_probe(struct platform_device *pdev)
> {
> struct device_node *np = pdev->dev.of_node;
> + const struct of_device_id *match;
> struct resource *res;
> struct at91_gpio_chip *at91_chip = NULL;
> struct gpio_chip *chip;
> @@ -1399,8 +1405,11 @@ static int __devinit at91_gpio_probe(struct platform_device *pdev)
> goto err;
> }
>
> - at91_chip->ops = (struct at91_pinctrl_mux_ops*)
> - of_match_device(at91_gpio_of_match, &pdev->dev)->data;
> + match = of_match_device(at91_gpio_of_match, &pdev->dev);
> + if (!match)
> + return -ENODEV;
> +
> + at91_chip->ops = (struct at91_pinctrl_mux_ops *) match->data;
> at91_chip->pioc_virq = irq;
> at91_chip->pioc_idx = alias_idx;
>
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v4 5/9] document: devicetree: bind pinconf with pin-single
From: Haojian Zhuang @ 2012-11-15 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A15E0C.2010903@wwwdotorg.org>
On Tue, Nov 13, 2012 at 4:37 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/07/2012 08:19 AM, Haojian Zhuang wrote:
>> Add comments with pinconf & gpio range in the document of
>> pinctrl-single.
>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
>
>> Required properties:
>> -- compatible : "pinctrl-single"
>> +- compatible : "pinctrl-single" or "pinconf-single".
>> + "pinctrl-single" means that pinconf isn't supported.
>> + "pinconf-single" means that generic pinconf is supported.
>>
>> - reg : offset and length of the register set for the mux registers
>>
>> @@ -14,9 +16,33 @@ Optional properties:
>> - pinctrl-single,function-off : function off mode for disabled state if
>> available and same for all registers; if not specified, disabling of
>> pin functions is ignored
>> +
>> - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
>> more than one pin
>>
>> +- pinctrl-single,power-source-mask : mask of setting power source in
>> + the pinmux register
>> +
>> +- pinctrl-single,power-source : value of setting power source field
>> + in the pinmux register
>
> Isn't power-source an enumeration? As such, shouldn't the pinctrl state
> definition supply the value, rather than the pin controller definition?
>
> The above two properties imply to me that you're saying "these bits
> (power-source-mask) in any pin register must be set to this one value
> (power-source)". However, I think you want to say "these bits
> (power-source-mask) are used to configure the power source", and then
> allow the state nodes (what's reference from pinctrl client devices'
> pinctrl-n properties) to define the value.
Got it.
>
> Perhaps that's your intent already, but if so, the properties for the
> two different nodes should be documented separately, not all interleaved
> in a single list, without any indication of which node they get put into.
>
>> +- pinctrl-single,bias-mask : mask of setting bias value in the pinmux
>> + register
>> +
>> +- pinctrl-single,bias-disable : value of disabling bias in the pinmux
>> + register
>> +
>> +- pinctrl-single,bias-pull-down : value of setting bias pull down in
>> + the pinmux register
>> +
>> +- pinctrl-single,bias-pull-up : value of setting bias pull up in the
>> + pinmux register
>> +
>> +- pinctrl-single,bias : value of setting bias in the pinmux register
>
> If there are bias-disable, bias-pull-down, and bias-pull-up properties,
> what is the plain "bias" property for?
>
Sure. I'll use input bias to explain it.
>> +- pinctrl-single,input-schmitt-mask : mask of setting input schmitt
>> + in the pinmux register
>
> And if the "value" properties go into the pinctrl state nodes, why isn't
> there a "value" property for schmitt?
>
>> +Optional sub-node: In case some pins could be configured as GPIO in the pinmux
>> +register. If both GPIO nubmer and pin base of those pins are in ascending order,
>> +those pins could be defined as a GPIO range. The sub-node should be defined in
>> +.dtsi files of those silicons.
>
> Pinctrl state definitions are also nodes directly inside the pin
> controller node. How does the pin controller driver know whether a child
> node is a state definition, or a GPIO range? Is the node required to
> have some specific name?
I think that "pinctrl-single,gpio" is enough. If the child node
doesn't contain the
gpio property, it won't be parsed as gpio range sub-node.
^ permalink raw reply
* [PATCH v4 5/9] document: devicetree: bind pinconf with pin-single
From: Haojian Zhuang @ 2012-11-15 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <50A15E0C.2010903@wwwdotorg.org>
On Tue, Nov 13, 2012 at 4:37 AM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 11/07/2012 08:19 AM, Haojian Zhuang wrote:
>> Add comments with pinconf & gpio range in the document of
>> pinctrl-single.
>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
>
>> Required properties:
>> -- compatible : "pinctrl-single"
>> +- compatible : "pinctrl-single" or "pinconf-single".
>> + "pinctrl-single" means that pinconf isn't supported.
>> + "pinconf-single" means that generic pinconf is supported.
>>
>> - reg : offset and length of the register set for the mux registers
>>
>> @@ -14,9 +16,33 @@ Optional properties:
>> - pinctrl-single,function-off : function off mode for disabled state if
>> available and same for all registers; if not specified, disabling of
>> pin functions is ignored
>> +
>> - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
>> more than one pin
>>
>> +- pinctrl-single,power-source-mask : mask of setting power source in
>> + the pinmux register
>> +
>> +- pinctrl-single,power-source : value of setting power source field
>> + in the pinmux register
>
> Isn't power-source an enumeration? As such, shouldn't the pinctrl state
> definition supply the value, rather than the pin controller definition?
>
> The above two properties imply to me that you're saying "these bits
> (power-source-mask) in any pin register must be set to this one value
> (power-source)". However, I think you want to say "these bits
> (power-source-mask) are used to configure the power source", and then
> allow the state nodes (what's reference from pinctrl client devices'
> pinctrl-n properties) to define the value.
Got it.
>
> Perhaps that's your intent already, but if so, the properties for the
> two different nodes should be documented separately, not all interleaved
> in a single list, without any indication of which node they get put into.
>
>> +- pinctrl-single,bias-mask : mask of setting bias value in the pinmux
>> + register
>> +
>> +- pinctrl-single,bias-disable : value of disabling bias in the pinmux
>> + register
>> +
>> +- pinctrl-single,bias-pull-down : value of setting bias pull down in
>> + the pinmux register
>> +
>> +- pinctrl-single,bias-pull-up : value of setting bias pull up in the
>> + pinmux register
>> +
>> +- pinctrl-single,bias : value of setting bias in the pinmux register
>
> If there are bias-disable, bias-pull-down, and bias-pull-up properties,
> what is the plain "bias" property for?
>
Sure. I'll use input bias to explain it.
>> +- pinctrl-single,input-schmitt-mask : mask of setting input schmitt
>> + in the pinmux register
>
> And if the "value" properties go into the pinctrl state nodes, why isn't
> there a "value" property for schmitt?
>
>> +Optional sub-node: In case some pins could be configured as GPIO in the pinmux
>> +register. If both GPIO nubmer and pin base of those pins are in ascending order,
>> +those pins could be defined as a GPIO range. The sub-node should be defined in
>> +.dtsi files of those silicons.
>
> Pinctrl state definitions are also nodes directly inside the pin
> controller node. How does the pin controller driver know whether a child
> node is a state definition, or a GPIO range? Is the node required to
> have some specific name?
I think that "pinctrl-single,gpio" is enough. If the child node
doesn't contain the
gpio property, it won't be parsed as gpio range sub-node.
^ permalink raw reply
* [PATCH] ARM i.MX dts: Consistently add labels to devicenodes
From: Sascha Hauer @ 2012-11-15 8:31 UTC (permalink / raw)
To: linux-arm-kernel
Having labels before each node allows board bindings to reference
to nodes by using the &nodename {} notation. This way boards do not
have to resemble the whole devicetree layout. Due to less indention
needed the board files also get better readability. Since the label
make the documentation behind the nodes unnecessary it is removed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boot/dts/imx27.dtsi | 5 ++-
arch/arm/boot/dts/imx51.dtsi | 40 +++++++++----------
arch/arm/boot/dts/imx53.dtsi | 42 ++++++++++----------
arch/arm/boot/dts/imx6q.dtsi | 88 +++++++++++++++++++++---------------------
4 files changed, 88 insertions(+), 87 deletions(-)
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 3e54f14..4192e87 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -58,7 +58,7 @@
reg = <0x10000000 0x10000000>;
ranges;
- wdog at 10002000 {
+ wdog: wdog at 10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x4000>;
interrupts = <27>;
@@ -218,7 +218,8 @@
status = "disabled";
};
};
- nand at d8000000 {
+
+ nfc: nand at d8000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 75d069f..9fd7657 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -76,14 +76,14 @@
reg = <0x70000000 0x40000>;
ranges;
- esdhc at 70004000 { /* ESDHC1 */
+ esdhc1: esdhc at 70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
status = "disabled";
};
- esdhc at 70008000 { /* ESDHC2 */
+ esdhc2: esdhc at 70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
@@ -97,7 +97,7 @@
status = "disabled";
};
- ecspi at 70010000 { /* ECSPI1 */
+ ecspi1: ecspi at 70010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
@@ -115,14 +115,14 @@
status = "disabled";
};
- esdhc at 70020000 { /* ESDHC3 */
+ esdhc3: esdhc at 70020000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
status = "disabled";
};
- esdhc at 70024000 { /* ESDHC4 */
+ esdhc4: esdhc at 70024000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
@@ -130,28 +130,28 @@
};
};
- usb at 73f80000 {
+ usbotg: usb at 73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
- usb at 73f80200 {
+ usbh1: usb at 73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
- usb at 73f80400 {
+ usbh2: usb at 73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
- usb at 73f80600 {
+ usbh3: usb at 73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
@@ -198,20 +198,20 @@
#interrupt-cells = <2>;
};
- wdog at 73f98000 { /* WDOG1 */
+ wdog1: wdog at 73f98000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
};
- wdog at 73f9c000 { /* WDOG2 */
+ wdog2: wdog at 73f9c000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
status = "disabled";
};
- iomuxc at 73fa8000 {
+ iomuxc: iomuxc at 73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
@@ -349,7 +349,7 @@
reg = <0x80000000 0x10000000>;
ranges;
- ecspi at 83fac000 { /* ECSPI2 */
+ ecspi2: ecspi at 83fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
@@ -358,14 +358,14 @@
status = "disabled";
};
- sdma at 83fb0000 {
+ sdma: sdma at 83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
- cspi at 83fc0000 {
+ cspi: cspi at 83fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
@@ -374,7 +374,7 @@
status = "disabled";
};
- i2c at 83fc4000 { /* I2C2 */
+ i2c2: i2c at 83fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
@@ -383,7 +383,7 @@
status = "disabled";
};
- i2c at 83fc8000 { /* I2C1 */
+ i2c1: i2c at 83fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
@@ -401,13 +401,13 @@
status = "disabled";
};
- audmux at 83fd0000 {
+ audmux: audmux at 83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
status = "disabled";
};
- nand at 83fdb000 {
+ nfc: nand at 83fdb000 {
compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>;
@@ -423,7 +423,7 @@
status = "disabled";
};
- ethernet at 83fec000 {
+ fec: ethernet at 83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 76ebb1a..08effd1 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -81,14 +81,14 @@
reg = <0x50000000 0x40000>;
ranges;
- esdhc at 50004000 { /* ESDHC1 */
+ esdhc1: esdhc at 50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
status = "disabled";
};
- esdhc at 50008000 { /* ESDHC2 */
+ esdhc2: esdhc at 50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
@@ -102,7 +102,7 @@
status = "disabled";
};
- ecspi at 50010000 { /* ECSPI1 */
+ ecspi1: ecspi at 50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -120,14 +120,14 @@
status = "disabled";
};
- esdhc at 50020000 { /* ESDHC3 */
+ esdhc3: esdhc at 50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
status = "disabled";
};
- esdhc at 50024000 { /* ESDHC4 */
+ esdhc4: esdhc at 50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
@@ -135,28 +135,28 @@
};
};
- usb at 53f80000 {
+ usbotg: usb at 53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
- usb at 53f80200 {
+ usbh1: usb at 53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
- usb at 53f80400 {
+ usbh2: usb at 53f80400 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
- usb at 53f80600 {
+ usbh3: usb at 53f80600 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
@@ -203,20 +203,20 @@
#interrupt-cells = <2>;
};
- wdog at 53f98000 { /* WDOG1 */
+ wdog1: wdog at 53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
};
- wdog at 53f9c000 { /* WDOG2 */
+ wdog2: wdog at 53f9c000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
status = "disabled";
};
- iomuxc at 53fa8000 {
+ iomuxc: iomuxc at 53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
@@ -429,7 +429,7 @@
#interrupt-cells = <2>;
};
- i2c at 53fec000 { /* I2C3 */
+ i2c3: i2c at 53fec000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
@@ -460,7 +460,7 @@
status = "disabled";
};
- ecspi at 63fac000 { /* ECSPI2 */
+ ecspi2: ecspi at 63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -469,14 +469,14 @@
status = "disabled";
};
- sdma at 63fb0000 {
+ sdma: sdma at 63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
- cspi at 63fc0000 {
+ cspi: cspi at 63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
@@ -485,7 +485,7 @@
status = "disabled";
};
- i2c at 63fc4000 { /* I2C2 */
+ i2c2: i2c at 63fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
@@ -494,7 +494,7 @@
status = "disabled";
};
- i2c at 63fc8000 { /* I2C1 */
+ i2c1: i2c at 63fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
@@ -512,13 +512,13 @@
status = "disabled";
};
- audmux at 63fd0000 {
+ audmux: audmux at 63fd0000 {
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
reg = <0x63fd0000 0x4000>;
status = "disabled";
};
- nand at 63fdb000 {
+ nfc: nand at 63fdb000 {
compatible = "fsl,imx53-nand";
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
interrupts = <8>;
@@ -534,7 +534,7 @@
status = "disabled";
};
- ethernet at 63fec000 {
+ fec: ethernet at 63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f3990b0..56772b9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -100,7 +100,7 @@
clocks = <&clks 106>;
};
- gpmi-nand at 00112000 {
+ nfc: gpmi-nand at 00112000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@@ -144,12 +144,12 @@
reg = <0x02000000 0x40000>;
ranges;
- spdif at 02004000 {
+ spdif: spdif at 02004000 {
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
};
- ecspi at 02008000 { /* eCSPI1 */
+ ecspi1: ecspi at 02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -160,7 +160,7 @@
status = "disabled";
};
- ecspi at 0200c000 { /* eCSPI2 */
+ ecspi2: ecspi at 0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -171,7 +171,7 @@
status = "disabled";
};
- ecspi at 02010000 { /* eCSPI3 */
+ ecspi3: ecspi at 02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -182,7 +182,7 @@
status = "disabled";
};
- ecspi at 02014000 { /* eCSPI4 */
+ ecspi4: ecspi at 02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -193,7 +193,7 @@
status = "disabled";
};
- ecspi at 02018000 { /* eCSPI5 */
+ ecspi5: ecspi at 02018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -213,7 +213,7 @@
status = "disabled";
};
- esai at 02024000 {
+ esai: esai at 02024000 {
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
};
@@ -248,7 +248,7 @@
status = "disabled";
};
- asrc at 02034000 {
+ asrc: asrc at 02034000 {
reg = <0x02034000 0x4000>;
interrupts = <0 50 0x04>;
};
@@ -258,7 +258,7 @@
};
};
- vpu at 02040000 {
+ vpu: vpu at 02040000 {
reg = <0x02040000 0x3c000>;
interrupts = <0 3 0x04 0 12 0x04>;
};
@@ -267,37 +267,37 @@
reg = <0x0207c000 0x4000>;
};
- pwm at 02080000 { /* PWM1 */
+ pwm1: pwm at 02080000 {
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
};
- pwm at 02084000 { /* PWM2 */
+ pwm2: pwm at 02084000 {
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
};
- pwm at 02088000 { /* PWM3 */
+ pwm3: pwm at 02088000 {
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
};
- pwm at 0208c000 { /* PWM4 */
+ pwm4: pwm at 0208c000 {
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
};
- flexcan at 02090000 { /* CAN1 */
+ can1: flexcan at 02090000 {
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
};
- flexcan at 02094000 { /* CAN2 */
+ can2: flexcan at 02094000 {
reg = <0x02094000 0x4000>;
interrupts = <0 111 0x04>;
};
- gpt at 02098000 {
+ gpt: gpt at 02098000 {
compatible = "fsl,imx6q-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
@@ -373,19 +373,19 @@
#interrupt-cells = <2>;
};
- kpp at 020b8000 {
+ kpp: kpp at 020b8000 {
reg = <0x020b8000 0x4000>;
interrupts = <0 82 0x04>;
};
- wdog at 020bc000 { /* WDOG1 */
+ wdog1: wdog at 020bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
clocks = <&clks 0>;
};
- wdog at 020c0000 { /* WDOG2 */
+ wdog2: wdog at 020c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
@@ -509,23 +509,23 @@
interrupts = <0 19 0x04 0 20 0x04>;
};
- epit at 020d0000 { /* EPIT1 */
+ epit1: epit at 020d0000 { /* EPIT1 */
reg = <0x020d0000 0x4000>;
interrupts = <0 56 0x04>;
};
- epit at 020d4000 { /* EPIT2 */
+ epit2: epit at 020d4000 { /* EPIT2 */
reg = <0x020d4000 0x4000>;
interrupts = <0 57 0x04>;
};
- src at 020d8000 {
+ src: src at 020d8000 {
compatible = "fsl,imx6q-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
};
- gpc at 020dc000 {
+ gpc: gpc at 020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
@@ -536,7 +536,7 @@
reg = <0x020e0000 0x38>;
};
- iomuxc at 020e0000 {
+ iomuxc: iomuxc at 020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
@@ -748,17 +748,17 @@
};
};
- dcic at 020e4000 { /* DCIC1 */
+ dcic1: dcic at 020e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 124 0x04>;
};
- dcic at 020e8000 { /* DCIC2 */
+ dcic2: dcic at 020e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 125 0x04>;
};
- sdma at 020ec000 {
+ sdma: sdma at 020ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
@@ -784,7 +784,7 @@
reg = <0x0217c000 0x4000>;
};
- usb at 02184000 { /* USB OTG */
+ usbotg: usb at 02184000 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
@@ -794,7 +794,7 @@
status = "disabled";
};
- usb at 02184200 { /* USB1 */
+ usbh1: usb at 02184200 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
@@ -804,7 +804,7 @@
status = "disabled";
};
- usb at 02184400 { /* USB2 */
+ usbh2: usb at 02184400 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 41 0x04>;
@@ -813,7 +813,7 @@
status = "disabled";
};
- usb at 02184600 { /* USB3 */
+ usbh3: usb at 02184600 {
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
reg = <0x02184600 0x200>;
interrupts = <0 42 0x04>;
@@ -822,14 +822,14 @@
status = "disabled";
};
- usbmisc: usbmisc at 02184800 {
+ usbmisc: usbmisc: usbmisc at 02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks 162>;
};
- ethernet at 02188000 {
+ fec: ethernet at 02188000 {
compatible = "fsl,imx6q-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 118 0x04 0 119 0x04>;
@@ -843,7 +843,7 @@
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
};
- usdhc at 02190000 { /* uSDHC1 */
+ usdhc1: usdhc at 02190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
@@ -852,7 +852,7 @@
status = "disabled";
};
- usdhc at 02194000 { /* uSDHC2 */
+ usdhc2: usdhc at 02194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
@@ -861,7 +861,7 @@
status = "disabled";
};
- usdhc at 02198000 { /* uSDHC3 */
+ usdhc3: usdhc at 02198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
@@ -870,7 +870,7 @@
status = "disabled";
};
- usdhc at 0219c000 { /* uSDHC4 */
+ usdhc4: usdhc at 0219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
@@ -879,7 +879,7 @@
status = "disabled";
};
- i2c at 021a0000 { /* I2C1 */
+ i2c1: i2c at 021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
@@ -889,7 +889,7 @@
status = "disabled";
};
- i2c at 021a4000 { /* I2C2 */
+ i2c2: i2c at 021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
@@ -899,7 +899,7 @@
status = "disabled";
};
- i2c at 021a8000 { /* I2C3 */
+ i2c3: i2c at 021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
@@ -913,12 +913,12 @@
reg = <0x021ac000 0x4000>;
};
- mmdc at 021b0000 { /* MMDC0 */
+ mmdc0: mmdc at 021b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
- mmdc at 021b4000 { /* MMDC1 */
+ mmdc1: mmdc at 021b4000 { /* MMDC1 */
reg = <0x021b4000 0x4000>;
};
@@ -946,7 +946,7 @@
interrupts = <0 109 0x04>;
};
- audmux at 021d8000 {
+ audmux: audmux at 021d8000 {
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
--
1.7.10.4
^ permalink raw reply related
* [PATCH v3 01/11] clk: samsung: add common clock framework helper functions for Samsung platforms
From: Thomas Abraham @ 2012-11-15 8:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3129811.yIGKilgVGz@flatron>
Hi Tomasz,
Thanks for reviewing these patches!
On 15 November 2012 04:42, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Thomas,
>
> Looks mostly good, but I have some minor comments inline.
>
> On Thursday 15 of November 2012 03:37:23 Thomas Abraham wrote:
>> All Samsung platforms include different types of clock including
>> fixed-rate, mux, divider and gate clock types. There are typically
>> hundreds of such clocks on each of the Samsung platforms. To enable
>> Samsung platforms to register these clocks using the common clock
>> framework, a bunch of utility functions are introduced here which
>> simplify the clock registration process. The clocks are usually
>> statically instantiated and registered with common clock framework.
>>
>> Cc: Mike Turquette <mturquette@linaro.org>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
>> ---
>> drivers/clk/Makefile | 1 +
>> drivers/clk/samsung/Makefile | 5 +
>> drivers/clk/samsung/clk.c | 176 ++++++++++++++++++++++++++++++++++
>> drivers/clk/samsung/clk.h | 218
>> ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 400
>> insertions(+), 0 deletions(-)
>> create mode 100644 drivers/clk/samsung/Makefile
>> create mode 100644 drivers/clk/samsung/clk.c
>> create mode 100644 drivers/clk/samsung/clk.h
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 2701235..808f8e1 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -19,6 +19,7 @@ endif
>> obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
>> obj-$(CONFIG_ARCH_U8500) += ux500/
>> obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
>> +obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
>>
>> # Chip specific
>> obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> new file mode 100644
>> index 0000000..3f926b0
>> --- /dev/null
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -0,0 +1,5 @@
>> +#
>> +# Samsung Clock specific Makefile
>> +#
>> +
>> +obj-$(CONFIG_PLAT_SAMSUNG) += clk.o
>> diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
>> new file mode 100644
>> index 0000000..ebc6fb6
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk.c
>> @@ -0,0 +1,176 @@
>> +/*
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2012 Linaro Ltd.
>> + * Author: Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + *
>> + * This file includes utility functions to register clocks to common
>> + * clock framework for Samsung platforms.
>> +*/
>> +
>> +#include "clk.h"
>> +
>> +static DEFINE_SPINLOCK(lock);
>> +static struct clk **clk_table;
>> +static struct clk_onecell_data clk_data;
>> +void __iomem *reg_base;
>
> Shouldn't it be static?
Yes, I missed that. Will fix.
>
>> +
>> +/* setup the essentials required to support clock lookup using ccf */
>> +void __init samsung_clk_init(struct device_node *np, void __iomem
>> *base, + unsigned long nr_clks)
>> +{
>> + reg_base = base;
>> + if (!np)
>> + return;
>> +
>> + clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
>> + if (!clk_table)
>> + panic("could not allocate clock lookup table\n");
>> +
>> + clk_data.clks = clk_table;
>> + clk_data.clk_num = nr_clks;
>> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>> +}
>> +
>> +/* add a clock instance to the clock lookup table used for dt based
>> lookup */ +void samsung_clk_add_lookup(struct clk *clk, unsigned int
>> id) +{
>> + if (clk_table && id)
>
> I'm not sure if we really need this kind of checks, but if we do, then
> shouldn't we also check id against clk_data.clk_num to prevent out of
> bound index?
The entry into the lookup table is required only for device tree based
platforms. And clk_table is a dynamically allocated table if booting
with device tree support. Since the call to samsung_clk_add_lookup is
made for non-dt platforms as well, the check for clk_table ensures
that the entry to lookup table is done only for device tree enabled
platforms. The check for 'id' ensures that the lookup entry index 0 is
not used. There is no clock which has id as 0.
>
>> + clk_table[id] = clk;
>> +}
>> +
>> +/* register a list of fixed clocks */
>> +void __init samsung_clk_register_fixed_rate(
>> + struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
>> +{
>> + struct clk *clk;
>> + unsigned int idx, ret;
>> +
>> + for (idx = 0; idx < nr_clk; idx++, list++) {
>> + clk = clk_register_fixed_rate(NULL, list->name,
>> + list->parent_name, list->flags, list->fixed_rate);
>> + if (IS_ERR(clk)) {
>> + pr_err("%s: failed to register clock %s\n", __func__,
>> + list->name);
>> + continue;
>> + }
>> +
>> + samsung_clk_add_lookup(clk, list->id);
>> +
>> + /*
>> + * Unconditionally add a clock lookup for the fixed rate
> clocks.
>> + * There are not many of these on any of Samsung platforms.
>> + */
>> + ret = clk_register_clkdev(clk, list->name, NULL);
>> + if (ret)
>> + pr_err("%s: failed to register clock lookup for %s",
>> + __func__, list->name);
>> + }
>> +}
>> +
>> +/* register a list of mux clocks */
>> +void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
>> + unsigned int nr_clk)
>> +{
>> + struct clk *clk;
>> + unsigned int idx, ret;
>> +
>> + for (idx = 0; idx < nr_clk; idx++, list++) {
>> + clk = clk_register_mux(NULL, list->name, list->parent_names,
>> + list->num_parents, list->flags, reg_base + list->offset,
>> + list->shift, list->width, list->mux_flags, &lock);
>> + if (IS_ERR(clk)) {
>> + pr_err("%s: failed to register clock %s\n", __func__,
>> + list->name);
>> + continue;
>> + }
>> +
>> + samsung_clk_add_lookup(clk, list->id);
>> +
>> + /* register a clock lookup only if a clock alias is specified
> */
>> + if (list->alias) {
>> + ret = clk_register_clkdev(clk, list->alias,
>> + list->dev_name);
>> + if (ret)
>> + pr_err("%s: failed to register lookup %s\n",
>> + __func__, list->alias);
>> + }
>> + }
>> +}
>> +
>> +/* register a list of div clocks */
>> +void __init samsung_clk_register_div(struct samsung_div_clock *list,
>> + unsigned int nr_clk)
>> +{
>> + struct clk *clk;
>> + unsigned int idx, ret;
>> +
>> + for (idx = 0; idx < nr_clk; idx++, list++) {
>> + clk = clk_register_divider(NULL, list->name, list-
>>parent_name,
>> + list->flags, reg_base + list->offset, list->shift,
>> + list->width, list->div_flags, &lock);
>> + if (IS_ERR(clk)) {
>> + pr_err("clock: failed to register clock %s\n",
>> + list->name);
>> + continue;
>> + }
>> +
>> + samsung_clk_add_lookup(clk, list->id);
>> +
>> + /* register a clock lookup only if a clock alias is specified
> */
>> + if (list->alias) {
>> + ret = clk_register_clkdev(clk, list->alias,
>> + list->dev_name);
>> + if (ret)
>> + pr_err("%s: failed to register lookup %s\n",
>> + __func__, list->alias);
>> + }
>> + }
>> +}
>> +
>> +/* register a list of gate clocks */
>> +void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
>> + unsigned int nr_clk)
>> +{
>> + struct clk *clk;
>> + unsigned int idx, ret;
>> +
>> + for (idx = 0; idx < nr_clk; idx++, list++) {
>> + clk = clk_register_gate(NULL, list->name, list->parent_name,
>> + list->flags, reg_base + list->offset,
>> + list->bit_idx, list->gate_flags, &lock);
>> + if (IS_ERR(clk)) {
>> + pr_err("clock: failed to register clock %s\n",
>> + list->name);
>> + continue;
>> + }
>> +
>> + /* register a clock lookup only if a clock alias is specified
> */
>> + if (list->alias) {
>> + ret = clk_register_clkdev(clk, list->alias,
>> + list->dev_name);
>> + if (ret)
>> + pr_err("%s: failed to register lookup %s\n",
>> + __func__, list->alias);
>> + }
>> +
>> + samsung_clk_add_lookup(clk, list->id);
>> + }
>> +}
>> +
>> +/* utility function to get the rate of a specified clock */
>> +unsigned long _get_rate(const char *clk_name)
>> +{
>> + struct clk *clk;
>> + unsigned long rate;
>> +
>> + clk = clk_get(NULL, clk_name);
>> + if (IS_ERR(clk))
>> + return 0;
>> + rate = clk_get_rate(clk);
>> + clk_put(clk);
>> + return rate;
>> +}
>> diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
>> new file mode 100644
>> index 0000000..ab43498
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk.h
>> @@ -0,0 +1,218 @@
>> +/*
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2012 Linaro Ltd.
>> + * Author: Thomas Abraham <thomas.ab@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as +
>> * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for all Samsung platforms
>> +*/
>> +
>> +#ifndef __SAMSUNG_CLK_H
>> +#define __SAMSUNG_CLK_H
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +
>> +#include <mach/map.h>
>> +
>> +/**
>> + * struct samsung_fixed_rate_clock: information about fixed-rate clock
>> + * @id: platform specific id of the clock.
>> + * @name: name of this fixed-rate clock.
>> + * @parent_name: optional parent clock name.
>> + * @flags: optional fixed-rate clock flags.
>> + * @fixed-rate: fixed clock rate of this clock.
>> + */
>> +struct samsung_fixed_rate_clock {
>> + unsigned int id;
>> + char *name;
>
> Shouldn't it be const char *name?
Yes, I will fix this.
>
>> + const char *parent_name;
>> + unsigned long flags;
>> + unsigned long fixed_rate;
>> +};
>> +
>> +#define FRATE(_id, cname, pname, f, frate) \
>> + { \
>> + .id = _id, \
>> + .name = cname, \
>> + .parent_name = pname, \
>> + .flags = f, \
>> + .fixed_rate = frate, \
>> + }
>> +
>> +/**
>> + * struct samsung_mux_clock: information about mux clock
>> + * @id: platform specific id of the clock.
>> + * @dev_name: name of the device to which this clock belongs.
>> + * @name: name of this mux clock.
>> + * @parent_names: array of pointer to parent clock names.
>> + * @num_parents: number of parents listed in @parent_names.
>> + * @flags: optional flags for basic clock.
>> + * @offset: offset of the register for configuring the mux.
>> + * @shift: starting bit location of the mux control bit-field in @reg.
>> + * @width: width of the mux control bit-field in @reg.
>> + * @mux_flags: flags for mux-type clock.
>> + * @alias: optional clock alias name to be assigned to this clock.
>> + */
>> +struct samsung_mux_clock {
>> + const unsigned int id;
>
> Is const unsigned int really correct?
Sorry, I did not get the problem here.
>
>> + const char *dev_name;
>> + const char *name;
>> + const char **parent_names;
>> + u8 num_parents;
>> + unsigned long flags;
>> + unsigned long offset;
>> + u8 shift;
>> + u8 width;
>> + u8 mux_flags;
>> + const char *alias;
>> +};
>> +
>> +#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
>> + { \
>> + .id = _id, \
>> + .dev_name = dname, \
>> + .name = cname, \
>> + .parent_names = pnames, \
>> + .num_parents = ARRAY_SIZE(pnames), \
>> + .flags = f, \
>> + .offset = o, \
>> + .shift = s, \
>> + .width = w, \
>> + .mux_flags = mf, \
>> + .alias = a, \
>> + }
>> +
>> +#define MUX(_id, cname, pnames, o, s, w) \
>> + __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
>> +
>> +#define MUX_A(_id, cname, pnames, o, s, w, a) \
>> + __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
>> +
>> +#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
>> + __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
>> +
>> +/**
>> + * @id: platform specific id of the clock.
>> + * struct samsung_div_clock: information about div clock
>> + * @dev_name: name of the device to which this clock belongs.
>> + * @name: name of this div clock.
>> + * @parent_name: name of the parent clock.
>> + * @flags: optional flags for basic clock.
>> + * @offset: offset of the register for configuring the div.
>> + * @shift: starting bit location of the div control bit-field in @reg.
>> + * @div_flags: flags for div-type clock.
>> + * @alias: optional clock alias name to be assigned to this clock.
>> + */
>> +struct samsung_div_clock {
>> + const unsigned int id;
>
> ditto
>
>> + const char *dev_name;
>> + const char *name;
>> + const char *parent_name;
>> + unsigned long flags;
>> + unsigned long offset;
>> + u8 shift;
>> + u8 width;
>> + u8 div_flags;
>> + const char *alias;
>> +};
>> +
>> +#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a) \
>> + { \
>> + .id = _id, \
>> + .dev_name = dname, \
>> + .name = cname, \
>> + .parent_name = pname, \
>> + .flags = f, \
>> + .offset = o, \
>> + .shift = s, \
>> + .width = w, \
>> + .div_flags = df, \
>> + .alias = a, \
>> + }
>> +
>> +#define DIV(_id, cname, pname, o, s, w) \
>> + __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL)
>> +
>> +#define DIV_A(_id, cname, pname, o, s, w, a) \
>> + __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a)
>> +
>> +#define DIV_F(_id, cname, pname, o, s, w, f, df) \
>> + __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL)
>> +
>> +/**
>> + * struct samsung_gate_clock: information about gate clock
>> + * @id: platform specific id of the clock.
>> + * @dev_name: name of the device to which this clock belongs.
>> + * @name: name of this gate clock.
>> + * @parent_name: name of the parent clock.
>> + * @flags: optional flags for basic clock.
>> + * @offset: offset of the register for configuring the gate.
>> + * @bit_idx: bit index of the gate control bit-field in @reg.
>> + * @gate_flags: flags for gate-type clock.
>> + * @alias: optional clock alias name to be assigned to this clock.
>> + */
>> +struct samsung_gate_clock {
>> + const unsigned int id;
>
> ditto
>
>> + const char *dev_name;
>> + const char *name;
>> + const char *parent_name;
>> + unsigned long flags;
>> + unsigned long offset;
>> + u8 bit_idx;
>> + u8 gate_flags;
>> + const char *alias;
>> +};
>> +
>> +#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
>> + { \
>> + .id = _id, \
>> + .dev_name = dname, \
>> + .name = cname, \
>> + .parent_name = pname, \
>> + .flags = f, \
>> + .offset = o, \
>> + .bit_idx = b, \
>> + .gate_flags = gf, \
>> + .alias = a, \
>> + }
>> +
>> +#define GATE(_id, cname, pname, o, b, f, gf) \
>> + __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
>> +
>> +#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
>> + __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
>> +
>> +#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
>> + __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
>> +
>> +#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
>> + __GATE(_id, dname, cname, pname, o, b, f, gf, a)
>> +
>> +#define PNAME(x) static const char *x[] __initdata
>> +
>> +extern void __iomem *reg_base;
>
> Where is it used? The name suggests that it should rather be static.
Right, this should not have been there. I will remove this.
Thanks,
Thomas.
^ permalink raw reply
* [PATCH 1/1] ARM: ux500: Describe UART platform registering issues more accurately
From: Lee Jones @ 2012-11-15 8:33 UTC (permalink / raw)
To: linux-arm-kernel
UARTs no longer require call-back information, since the reset
call-back was removed in 43b5f0d69291374f602ad8e1817f329573a59010.
The only AUXDATA dependencies remaining for UARTs are DMA settings.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
arch/arm/mach-ux500/cpu-db8500.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 4a0c40a..d2076ce 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -262,11 +262,10 @@ static struct device * __init u8500_of_init_devices(void)
static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
- /* Requires DMA and call-back bindings. */
+ /* Requires DMA bindings. */
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
- /* Requires DMA bindings. */
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 0/10] use pinctrl-single in arch mmp
From: Haojian Zhuang @ 2012-11-15 8:36 UTC (permalink / raw)
To: linux-arm-kernel
Changelog:
v5:
1. Move the properties of pinconf into pin group. So those mask
properties could be merged with other pinconf properties.
2. Append lookup pinctrl map method.
3. Append input schmitt disable config parameter.
4. Clean code.
v4:
1. Define gpio range as sub-node, not label. And remove
pinctrl-single,gpio-ranges property.
2. Use new two properties in sub-node, reg &
pinctrl-single,gpio. GPIO number & GPIO function are listed in
the pinctrl-single,gpio property.
3. Reference the names like pinctrl-single,bias.
4. Add compatible name "pinconf-single". If the compatible name is
"pinctrl-single", there's no pinconf. If the compatible name is
"pinconf-single", there's the generic pinconf in pinctrl-single.
5. Update documents.
v3:
1. Add more comments in document.
2. Replace pcs_readl() & pcs_writel() by pcs->read() & pcs->write().
3. Clean code.
v2:
1. Remove "pinctrl-single,gpio-mask". Since GPIO function is one of the
mux function in the pinmux register of both OMAP and PXA/MMP silicons.
Use "pinctrl-single,function-mask" instead.
2. Remove "pinctrl-single,gpio-enable" & "pinctrl-single,gpio-disable".
Use "pinctrl-single,gpio-func" instead. Because GPIO mode is only one
of the mux functions in the pinmux register. Defining "gpio-enable" &
"gpio-disable" are redundant.
3. Define register with __iomem, not u32 type.
4. Remove "pinctrl-single,input-schmit-shift",
"pinctrl-single,power-source-shift", "pinctrl-single,bias-shift". All
these properties could be calculated by mask fields.
5. Return -EPROBE_DEFER if pinmux could be got in device driver. And
the device driver would be probed again deferred.
^ permalink raw reply
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