* [PATCH V2 1/5] PCI/AER: replace pci_reset_bridge_secondary_bus with pci_reset_bus
From: Sinan Kaya @ 2016-09-16 20:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474056395-21843-1-git-send-email-okaya@codeaurora.org>
The error handling path is not saving and restoring the settings on
other devices getting impacted by a secondary bus reset. Using a better
API to take care of this.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/pci/pcie/aer/aerdrv.c | 2 +-
drivers/pci/pcie/aer/aerdrv_core.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 48d21e0..7880cd1 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -350,7 +350,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
- pci_reset_bridge_secondary_bus(dev);
+ pci_reset_bus(dev->subordinate);
dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
/* Clear Root Error Status */
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 521e39c..0339cc3 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -403,7 +403,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
*/
static pci_ers_result_t default_reset_link(struct pci_dev *dev)
{
- pci_reset_bridge_secondary_bus(dev);
+ pci_reset_bus(dev->subordinate);
dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
return PCI_ERS_RESULT_RECOVERED;
}
--
1.9.1
^ permalink raw reply related
* [PATCH V2 0/5] PCI: error handling clean up and add CRS support
From: Sinan Kaya @ 2016-09-16 20:06 UTC (permalink / raw)
To: linux-arm-kernel
Device states on the bus are not saved and restored for some of the bus
reset paths as:
1. IB/hfi1 via pci_reset_bridge_secondary_bus
2. PCI/AER via pci_reset_bridge_secondary_bus
3. PCI: dev_reset via parent bus reset
Changing the external API usage to pci_reset_bus outside of PCI code and
adding save/restore into pci_parent_bus_reset function. Note that
pci_parent_bus_reset is called with a device lock held.
A PCIe endpoint is allowed to issue CRS following an FLR request to
indicate that it is not ready to accept new requests. Changing the polling
mechanism in FLR wait function to go read the vendor ID instead of the
command/status register. A CRS indication will only be given if the address
to be read is vendor ID.
v1:
http://www.spinics.net/lists/linux-pci/msg53596.html
* initial implementation
Sinan Kaya (5):
PCI/AER: replace pci_reset_bridge_secondary_bus with pci_reset_bus
IB/hfi1: replace pci_reset_bridge_secondary_bus with pci_reset_bus
PCI: save and restore bus on parent bus reset
PCI: add CRS support to error handling path
PCI: handle CRS returned by device after FLR
drivers/infiniband/hw/hfi1/pcie.c | 4 +---
drivers/pci/pci.c | 28 +++++++++++++++++++++++++++-
drivers/pci/pcie/aer/aerdrv.c | 2 +-
drivers/pci/pcie/aer/aerdrv_core.c | 2 +-
4 files changed, 30 insertions(+), 6 deletions(-)
--
1.9.1
^ permalink raw reply
* [RFT] arm64 dts: exynos: Fix invalid GIC interrupt flags in exynos7
From: Krzysztof Kozlowski @ 2016-09-16 20:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 20 +++++--
arch/arm64/boot/dts/exynos/exynos7.dtsi | 69 +++++++++++++------------
2 files changed, 51 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index f77ddaf21d04..983c63ba38c8 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -20,8 +20,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>;
};
gpa1: gpa1 {
@@ -31,8 +37,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
- interrupts = <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>;
};
gpa2: gpa2 {
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 6328a66ed97e..0a80dabfbe95 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -106,7 +106,7 @@
pdma0: pdma at 10E10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10E10000 0x1000>;
- interrupts = <0 225 0>;
+ interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys0 ACLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -117,7 +117,7 @@
pdma1: pdma at 10EB0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10EB0000 0x1000>;
- interrupts = <0 226 0>;
+ interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys0 ACLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -220,7 +220,7 @@
serial_0: serial at 13630000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13630000 0x100>;
- interrupts = <0 440 0>;
+ interrupts = <0 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric0 PCLK_UART0>,
<&clock_peric0 SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
@@ -230,7 +230,7 @@
serial_1: serial at 14c20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c20000 0x100>;
- interrupts = <0 456 0>;
+ interrupts = <0 456 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART1>,
<&clock_peric1 SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
@@ -240,7 +240,7 @@
serial_2: serial at 14c30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c30000 0x100>;
- interrupts = <0 457 0>;
+ interrupts = <0 457 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART2>,
<&clock_peric1 SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
@@ -250,7 +250,7 @@
serial_3: serial at 14c40000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14c40000 0x100>;
- interrupts = <0 458 0>;
+ interrupts = <0 458 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART3>,
<&clock_peric1 SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
@@ -264,62 +264,62 @@
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 16 0>;
+ interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_bus0: pinctrl at 13470000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x13470000 0x1000>;
- interrupts = <0 383 0>;
+ interrupts = <0 383 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_nfc: pinctrl at 14cd0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14cd0000 0x1000>;
- interrupts = <0 473 0>;
+ interrupts = <0 473 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_touch: pinctrl at 14ce0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ce0000 0x1000>;
- interrupts = <0 474 0>;
+ interrupts = <0 474 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_ff: pinctrl at 14c90000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14c90000 0x1000>;
- interrupts = <0 475 0>;
+ interrupts = <0 475 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_ese: pinctrl at 14ca0000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14ca0000 0x1000>;
- interrupts = <0 476 0>;
+ interrupts = <0 476 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys0: pinctrl at 10e60000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x10e60000 0x1000>;
- interrupts = <0 221 0>;
+ interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys1: pinctrl at 15690000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x15690000 0x1000>;
- interrupts = <0 203 0>;
+ interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_bus1: pinctrl at 14870000 {
compatible = "samsung,exynos7-pinctrl";
reg = <0x14870000 0x1000>;
- interrupts = <0 384 0>;
+ interrupts = <0 384 IRQ_TYPE_LEVEL_HIGH>;
};
hsi2c_0: hsi2c at 13640000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13640000 0x1000>;
- interrupts = <0 441 0>;
+ interrupts = <0 441 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -332,7 +332,7 @@
hsi2c_1: hsi2c at 13650000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13650000 0x1000>;
- interrupts = <0 442 0>;
+ interrupts = <0 442 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -345,7 +345,7 @@
hsi2c_2: hsi2c at 14e60000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e60000 0x1000>;
- interrupts = <0 459 0>;
+ interrupts = <0 459 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -358,7 +358,7 @@
hsi2c_3: hsi2c at 14e70000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e70000 0x1000>;
- interrupts = <0 460 0>;
+ interrupts = <0 460 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -371,7 +371,7 @@
hsi2c_4: hsi2c at 13660000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13660000 0x1000>;
- interrupts = <0 443 0>;
+ interrupts = <0 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -384,7 +384,7 @@
hsi2c_5: hsi2c at 13670000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13670000 0x1000>;
- interrupts = <0 444 0>;
+ interrupts = <0 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -397,7 +397,7 @@
hsi2c_6: hsi2c at 14e00000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e00000 0x1000>;
- interrupts = <0 461 0>;
+ interrupts = <0 461 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -410,7 +410,7 @@
hsi2c_7: hsi2c at 13e10000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13e10000 0x1000>;
- interrupts = <0 462 0>;
+ interrupts = <0 462 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -423,7 +423,7 @@
hsi2c_8: hsi2c at 14e20000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x14e20000 0x1000>;
- interrupts = <0 463 0>;
+ interrupts = <0 463 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -436,7 +436,7 @@
hsi2c_9: hsi2c at 13680000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13680000 0x1000>;
- interrupts = <0 445 0>;
+ interrupts = <0 445 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -449,7 +449,7 @@
hsi2c_10: hsi2c at 13690000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x13690000 0x1000>;
- interrupts = <0 446 0>;
+ interrupts = <0 446 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -462,7 +462,7 @@
hsi2c_11: hsi2c at 136a0000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x136a0000 0x1000>;
- interrupts = <0 447 0>;
+ interrupts = <0 447 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -499,7 +499,8 @@
rtc: rtc at 10590000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10590000 0x100>;
- interrupts = <0 355 0>, <0 356 0>;
+ interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>,
+ <0 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_ccore PCLK_RTC>;
clock-names = "rtc";
status = "disabled";
@@ -508,7 +509,7 @@
watchdog: watchdog at 101d0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x101d0000 0x100>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peris PCLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -517,7 +518,7 @@
mmc_0: mmc at 15740000 {
compatible = "samsung,exynos7-dw-mshc-smu";
- interrupts = <0 201 0>;
+ interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15740000 0x2000>;
@@ -530,7 +531,7 @@
mmc_1: mmc at 15750000 {
compatible = "samsung,exynos7-dw-mshc";
- interrupts = <0 202 0>;
+ interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15750000 0x2000>;
@@ -543,7 +544,7 @@
mmc_2: mmc at 15560000 {
compatible = "samsung,exynos7-dw-mshc-smu";
- interrupts = <0 216 0>;
+ interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x15560000 0x2000>;
@@ -557,7 +558,7 @@
adc: adc at 13620000 {
compatible = "samsung,exynos7-adc";
reg = <0x13620000 0x100>;
- interrupts = <0 448 0>;
+ interrupts = <0 448 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric0 PCLK_ADCIF>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -577,7 +578,7 @@
tmuctrl_0: tmu at 10060000 {
compatible = "samsung,exynos7-tmu";
reg = <0x10060000 0x200>;
- interrupts = <0 108 0>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peris PCLK_TMU>,
<&clock_peris SCLK_TMU>;
clock-names = "tmu_apbif", "tmu_sclk";
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/2] soc: qcom: add l2 cache perf events driver
From: Neil Leeder @ 2016-09-16 19:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916164011.GB3179@leverpostej>
On 9/16/2016 12:40 PM, Mark Rutland wrote:
> On Fri, Sep 16, 2016 at 11:33:39AM -0400, Neil Leeder wrote:
[...]
>> On 9/1/2016 12:30 PM, Mark Rutland wrote:
>>> On Tue, Aug 30, 2016 at 01:01:33PM -0400, Neil Leeder wrote:
>>>> + /* Don't allow groups with mixed PMUs, except for s/w events */
>>>> + if (event->group_leader->pmu != event->pmu &&
>>>> + !is_software_event(event->group_leader)) {
>>>> + dev_warn(&l2cache_pmu->pdev->dev,
>>>> + "Can't create mixed PMU group\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + list_for_each_entry(sibling, &event->group_leader->sibling_list,
>>>> + group_entry)
>>>> + if (sibling->pmu != event->pmu &&
>>>> + !is_software_event(sibling)) {
>>>> + dev_warn(&l2cache_pmu->pdev->dev,
>>>> + "Can't create mixed PMU group\n");
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + hwc->idx = -1;
>>>> + hwc->config_base = event->attr.config;
>>>> +
>>>> + /*
>>>> + * Ensure all events are on the same cpu so all events are in the
>>>> + * same cpu context, to avoid races on pmu_enable etc.
>>>> + */
>>>> + slice = get_hml2_pmu(event->cpu);
>>>> + event->cpu = slice->on_cpu;
>>>
>>> This could put an event on a different CPU to its group siblings, which
>>> is broken.
>>
>> This is the same logic as in arm-ccn.c:arm_ccn_pmu_event_init(), where there
>> is a single CPU designated as the CPU to be used for all events.
>>
>> All events for this slice are forced to slice->on_cpu which is the CPU
>> set in the cpumask for this slice.
>
> The CCN is a little different. For the CCN, a single CPU is designated
> to handle *all* events.
>
> For this driver, a CPU is designated per-slice, judging by the existence
> of hml2_pmu::on_cpu (unless that's superfluous). We've only verified
> that the events are all for this PMU, not the same slice, and thus each
> event->cpu may differ.
>
I see. So I can add a check that the group_leader event must be on the
same slice, and thus on the same CPU.
>> I'm not sure how this can put an event on a different CPU to its group
>> siblings?
>
> In practice today, we'll try to schedule the event on it's group
> leader's CPU, but accounting and subsequent manipulation could go wrong.
>
> Thanks,
> Mark.
>
Neil
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 10/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5440.dtsi | 48 ++++++++++++++++++++++++---------------
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index e6bffd13cedd..20f600225121 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5440.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5440", "samsung,exynos5";
@@ -91,7 +92,7 @@
cpufreq at 160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
- interrupts = <0 57 0>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
operating-points = <
/* KHz uV */
1500000 1100000
@@ -108,7 +109,7 @@
serial_0: serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
- interrupts = <0 2 0>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -116,7 +117,7 @@
serial_1: serial at C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
- interrupts = <0 3 0>;
+ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
clock-names = "uart", "clk_uart_baud0";
};
@@ -124,7 +125,7 @@
spi_0: spi at D0000 {
compatible = "samsung,exynos5440-spi";
reg = <0xD0000 0x100>;
- interrupts = <0 4 0>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,spi-src-clk = <0>;
@@ -136,8 +137,14 @@
pin_ctrl: pinctrl at E0000 {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
- <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
@@ -162,7 +169,7 @@
i2c at F0000 {
compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>;
- interrupts = <0 5 0>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -172,7 +179,7 @@
i2c at 100000 {
compatible = "samsung,exynos5440-i2c";
reg = <0x100000 0x1000>;
- interrupts = <0 6 0>;
+ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_B_125>;
@@ -182,7 +189,7 @@
watchdog at 110000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
- interrupts = <0 1 0>;
+ interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "watchdog";
};
@@ -209,7 +216,8 @@
rtc at 130000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
- interrupts = <0 17 0>, <0 16 0>;
+ interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "rtc";
};
@@ -217,7 +225,7 @@
tmuctrl_0: tmuctrl at 160118 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -226,7 +234,7 @@
tmuctrl_1: tmuctrl at 16011C {
compatible = "samsung,exynos5440-tmu";
reg = <0x16011C 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -235,7 +243,7 @@
tmuctrl_2: tmuctrl at 160120 {
compatible = "samsung,exynos5440-tmu";
reg = <0x160120 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
clock-names = "tmu_apbif";
#include "exynos5440-tmu-sensor-conf.dtsi"
@@ -259,7 +267,7 @@
sata at 210000 {
compatible = "snps,exynos5440-ahci";
reg = <0x210000 0x10000>;
- interrupts = <0 30 0>;
+ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>;
clock-names = "sata";
};
@@ -267,7 +275,7 @@
ohci at 220000 {
compatible = "samsung,exynos5440-ohci";
reg = <0x220000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -275,7 +283,7 @@
ehci at 221000 {
compatible = "samsung,exynos5440-ehci";
reg = <0x221000 0x1000>;
- interrupts = <0 29 0>;
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB>;
clock-names = "usbhost";
};
@@ -285,7 +293,9 @@
reg = <0x290000 0x1000
0x270000 0x1000
0x271000 0x40>;
- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+ interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
@@ -306,7 +316,9 @@
reg = <0x2a0000 0x1000
0x272000 0x1000
0x271040 0x40>;
- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
--
2.7.4
^ permalink raw reply related
* [PATCH 09/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5260.dtsi | 39 ++++++++++++++++++++++++---------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index a86a4898d077..b0848a3d3d88 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos5260-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos5260", "samsung,exynos5";
@@ -181,10 +182,18 @@
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
clock-names = "fin_pll", "mct";
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 122 0>, <0 123 0>,
- <0 124 0>, <0 125 0>, <0 126 0>,
- <0 127 0>, <0 128 0>, <0 129 0>;
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 127 IRQ_TYPE_LEVEL_HIGH>,
+ <0 128 IRQ_TYPE_LEVEL_HIGH>,
+ <0 129 IRQ_TYPE_LEVEL_HIGH>;
};
cci: cci at 10F00000 {
@@ -210,25 +219,25 @@
pinctrl_0: pinctrl at 11600000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x11600000 0x1000>;
- interrupts = <0 79 0>;
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl at 12290000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x12290000 0x1000>;
- interrupts = <0 157 0>;
+ interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl at 128B0000 {
compatible = "samsung,exynos5260-pinctrl";
reg = <0x128B0000 0x1000>;
- interrupts = <0 243 0>;
+ interrupts = <0 243 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller at 10D50000 {
@@ -239,7 +248,7 @@
uart0: serial at 12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 146 0>;
+ interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -248,7 +257,7 @@
uart1: serial at 12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 147 0>;
+ interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -257,7 +266,7 @@
uart2: serial at 12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 148 0>;
+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -266,7 +275,7 @@
uart3: serial at 12860000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12860000 0x100>;
- interrupts = <0 145 0>;
+ interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -275,7 +284,7 @@
mmc_0: mmc at 12140000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12140000 0x2000>;
- interrupts = <0 156 0>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
@@ -287,7 +296,7 @@
mmc_1: mmc at 12150000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12150000 0x2000>;
- interrupts = <0 158 0>;
+ interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
@@ -299,7 +308,7 @@
mmc_2: mmc at 12160000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12160000 0x2000>;
- interrupts = <0 159 0>;
+ interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
--
2.7.4
^ permalink raw reply related
* [PATCH 08/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5410/exynos542x
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410.dtsi | 26 ++++++-------
arch/arm/boot/dts/exynos5420.dtsi | 78 +++++++++++++++++++--------------------
arch/arm/boot/dts/exynos54xx.dtsi | 34 ++++++++---------
3 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 137f48464f8b..dae5715b41b9 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -85,7 +85,7 @@
tmu_cpu0: tmu at 10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <GIC_SPI 65 0>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -94,7 +94,7 @@
tmu_cpu1: tmu at 10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <GIC_SPI 183 0>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -103,7 +103,7 @@
tmu_cpu2: tmu at 10068000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10068000 0x100>;
- interrupts = <GIC_SPI 184 0>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -112,7 +112,7 @@
tmu_cpu3: tmu at 1006c000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x1006c000 0x100>;
- interrupts = <GIC_SPI 185 0>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -121,7 +121,7 @@
mmc_0: mmc at 12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
@@ -133,7 +133,7 @@
mmc_1: mmc at 12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
@@ -145,7 +145,7 @@
mmc_2: mmc at 12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
@@ -157,31 +157,31 @@
pinctrl_0: pinctrl at 13400000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl at 14000000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl at 10d10000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl at 03860000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -329,7 +329,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 200 0>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 00c4cfa54839..906a1a42a7ea 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -193,7 +193,7 @@
mfc: codec at 11000000 {
compatible = "samsung,mfc-v7";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
power-domains = <&mfc_pd>;
@@ -203,7 +203,7 @@
mmc_0: mmc at 12200000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x2000>;
@@ -215,7 +215,7 @@
mmc_1: mmc at 12210000 {
compatible = "samsung,exynos5420-dw-mshc-smu";
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x2000>;
@@ -227,7 +227,7 @@
mmc_2: mmc at 12220000 {
compatible = "samsung,exynos5420-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -320,37 +320,37 @@
pinctrl_0: pinctrl at 13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl at 13410000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13410000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl at 14000000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl at 14010000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x14010000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_4: pinctrl at 03860000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
amba {
@@ -363,7 +363,7 @@
adma: adma at 03880000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x03880000 0x1000>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_audss EXYNOS_ADMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -374,7 +374,7 @@
pdma0: pdma at 121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -385,7 +385,7 @@
pdma1: pdma at 121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -396,7 +396,7 @@
mdma0: mdma at 10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -407,7 +407,7 @@
mdma1: mdma at 11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -479,7 +479,7 @@
spi_0: spi at 12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -495,7 +495,7 @@
spi_1: spi at 12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
- interrupts = <0 69 0>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -511,7 +511,7 @@
spi_2: spi at 12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -539,7 +539,7 @@
dsi at 14500000 {
compatible = "samsung,exynos5410-mipi-dsi";
reg = <0x14500000 0x10000>;
- interrupts = <0 82 0>;
+ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
@@ -552,7 +552,7 @@
adc: adc at 12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TSADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -564,7 +564,7 @@
hsi2c_8: i2c at 12E00000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E00000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -577,7 +577,7 @@
hsi2c_9: i2c at 12E10000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E10000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -590,7 +590,7 @@
hsi2c_10: i2c at 12E20000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12E20000 0x1000>;
- interrupts = <0 203 0>;
+ interrupts = <0 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -603,7 +603,7 @@
hdmi: hdmi at 14530000 {
compatible = "samsung,exynos5420-hdmi";
reg = <0x14530000 0x70000>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -622,7 +622,7 @@
mixer: mixer at 14450000 {
compatible = "samsung,exynos5420-mixer";
reg = <0x14450000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -633,7 +633,7 @@
rotator: rotator at 11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -642,7 +642,7 @@
gsc_0: video-scaler at 13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -652,7 +652,7 @@
gsc_1: video-scaler at 13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
power-domains = <&gsc_pd>;
@@ -662,7 +662,7 @@
jpeg_0: jpeg at 11F50000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F50000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG>;
iommus = <&sysmmu_jpeg0>;
@@ -671,7 +671,7 @@
jpeg_1: jpeg at 11F60000 {
compatible = "samsung,exynos5420-jpeg";
reg = <0x11F60000 0x1000>;
- interrupts = <0 168 0>;
+ interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "jpeg";
clocks = <&clock CLK_JPEG2>;
iommus = <&sysmmu_jpeg1>;
@@ -691,7 +691,7 @@
tmu_cpu0: tmu at 10060000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -700,7 +700,7 @@
tmu_cpu1: tmu at 10064000 {
compatible = "samsung,exynos5420-tmu";
reg = <0x10064000 0x100>;
- interrupts = <0 183 0>;
+ interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -709,7 +709,7 @@
tmu_cpu2: tmu at 10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
- interrupts = <0 184 0>;
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -718,7 +718,7 @@
tmu_cpu3: tmu at 1006c000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
- interrupts = <0 185 0>;
+ interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -727,7 +727,7 @@
tmu_gpu: tmu at 100a0000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
- interrupts = <0 215 0>;
+ interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -799,7 +799,7 @@
sysmmu_scaler1r: sysmmu at 0x12890000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12890000 0x1000>;
- interrupts = <0 186 0>;
+ interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
#iommu-cells = <0>;
@@ -808,7 +808,7 @@
sysmmu_scaler2r: sysmmu at 0x128A0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x128A0000 0x1000>;
- interrupts = <0 188 0>;
+ interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
#iommu-cells = <0>;
@@ -867,7 +867,7 @@
sysmmu_jpeg1: sysmmu at 0x11F20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11F20000 0x1000>;
- interrupts = <0 169 0>;
+ interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
#iommu-cells = <0>;
@@ -1445,7 +1445,7 @@
};
&usbdrd_dwc3_1 {
- interrupts = <GIC_SPI 73 0>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdrd_phy1 {
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9d31cdce1959..8640b01f1c94 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -62,34 +62,34 @@
<1 &combiner 23 4>,
<2 &combiner 25 2>,
<3 &combiner 25 3>,
- <4 &gic 0 120 0>,
- <5 &gic 0 121 0>,
- <6 &gic 0 122 0>,
- <7 &gic 0 123 0>,
- <8 &gic 0 128 0>,
- <9 &gic 0 129 0>,
- <10 &gic 0 130 0>,
- <11 &gic 0 131 0>;
+ <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
+ <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
+ <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
+ <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
+ <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
+ <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
};
};
watchdog: watchdog at 101d0000 {
compatible = "samsung,exynos5420-wdt";
reg = <0x101d0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
};
sss: sss at 10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
};
/* i2c_0-3 are defined in exynos5.dtsi */
hsi2c_4: i2c at 12ca0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12ca0000 0x1000>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -98,7 +98,7 @@
hsi2c_5: i2c at 12cb0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cb0000 0x1000>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -107,7 +107,7 @@
hsi2c_6: i2c at 12cc0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cc0000 0x1000>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -116,7 +116,7 @@
hsi2c_7: i2c at 12cd0000 {
compatible = "samsung,exynos5250-hsi2c";
reg = <0x12cd0000 0x1000>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -131,7 +131,7 @@
usbdrd_dwc3_0: dwc3 at 12000000 {
compatible = "snps,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -166,7 +166,7 @@
usbhost2: usb at 12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -179,7 +179,7 @@
usbhost1: usb at 12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
^ permalink raw reply related
* [PATCH 07/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5250.dtsi | 80 +++++++++++++++++++--------------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7357d99b47c..4e00c0d06c67 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -181,8 +181,8 @@
<0x1 0 &combiner 23 4>,
<0x2 0 &combiner 25 2>,
<0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
+ <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
+ <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -195,31 +195,31 @@
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_1: pinctrl at 13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
- interrupts = <0 45 0>;
+ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_2: pinctrl at 10d10000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
- interrupts = <0 50 0>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_3: pinctrl at 03860000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller at 10040000 {
@@ -236,7 +236,7 @@
watchdog at 101D0000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x101D0000 0x100>;
- interrupts = <0 42 0>;
+ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -245,7 +245,7 @@
g2d at 10850000 {
compatible = "samsung,exynos5250-g2d";
reg = <0x10850000 0x1000>;
- interrupts = <0 91 0>;
+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_G2D>;
clock-names = "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -254,7 +254,7 @@
mfc: codec at 11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>;
clock-names = "mfc";
@@ -265,7 +265,7 @@
rotator: rotator at 11C00000 {
compatible = "samsung,exynos5250-rotator";
reg = <0x11C00000 0x64>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -274,7 +274,7 @@
tmu: tmu at 10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -284,7 +284,7 @@
compatible = "snps,dwc-ahci";
samsung,sata-freq = <66>;
reg = <0x122F0000 0x1ff>;
- interrupts = <0 115 0>;
+ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
clock-names = "sata", "sclk_sata";
phys = <&sata_phy>;
@@ -306,7 +306,7 @@
i2c_4: i2c at 12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C4>;
@@ -319,7 +319,7 @@
i2c_5: i2c at 12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C5>;
@@ -332,7 +332,7 @@
i2c_6: i2c at 12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C6>;
@@ -345,7 +345,7 @@
i2c_7: i2c at 12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C7>;
@@ -358,7 +358,7 @@
i2c_8: i2c at 12CE0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
- interrupts = <0 64 0>;
+ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C_HDMI>;
@@ -380,7 +380,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d20000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@@ -396,7 +396,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d30000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@@ -412,7 +412,7 @@
compatible = "samsung,exynos4210-spi";
status = "disabled";
reg = <0x12d40000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@@ -426,7 +426,7 @@
mmc_0: mmc at 12200000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12200000 0x1000>;
@@ -438,7 +438,7 @@
mmc_1: mmc at 12210000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12210000 0x1000>;
@@ -450,7 +450,7 @@
mmc_2: mmc at 12220000 {
compatible = "samsung,exynos5250-dw-mshc";
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x12220000 0x1000>;
@@ -463,7 +463,7 @@
mmc_3: mmc at 12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
@@ -526,7 +526,7 @@
usbdrd_dwc3: dwc3 at 12000000 {
compatible = "synopsys,dwc3";
reg = <0x12000000 0x10000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
phy-names = "usb2-phy", "usb3-phy";
};
@@ -544,7 +544,7 @@
ehci: usb at 12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -559,7 +559,7 @@
ohci: usb at 12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB2>;
clock-names = "usbhost";
@@ -591,7 +591,7 @@
pdma0: pdma at 121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -602,7 +602,7 @@
pdma1: pdma at 121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -613,7 +613,7 @@
mdma0: mdma at 10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
- interrupts = <0 33 0>;
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -624,7 +624,7 @@
mdma1: mdma at 11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -636,7 +636,7 @@
gsc_0: gsc at 13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
@@ -646,7 +646,7 @@
gsc_1: gsc at 13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL1>;
clock-names = "gscl";
@@ -656,7 +656,7 @@
gsc_2: gsc at 13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL2>;
clock-names = "gscl";
@@ -666,7 +666,7 @@
gsc_3: gsc at 13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL3>;
clock-names = "gscl";
@@ -677,7 +677,7 @@
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
power-domains = <&pd_disp1>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
@@ -690,7 +690,7 @@
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
power-domains = <&pd_disp1>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "hdmi", "sclk_hdmi";
@@ -706,7 +706,7 @@
adc: adc at 12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ADC>;
clock-names = "adc";
#io-channel-cells = <1>;
@@ -718,7 +718,7 @@
sss at 10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 06/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5.dtsi | 60 ++++++++++++++++++++++++++++++------------
1 file changed, 43 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 8f06609879f5..d9b1607db5ad 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -53,14 +54,38 @@
interrupt-controller;
samsung,combiner-nr = <32>;
reg = <0x10440000 0x1000>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
- <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>,
+ <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller at 10481000 {
@@ -82,31 +107,31 @@
serial_0: serial at 12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
};
serial_1: serial at 12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
};
serial_2: serial at 12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
};
serial_3: serial at 12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
};
i2c_0: i2c at 12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
- interrupts = <0 56 0>;
+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -116,7 +141,7 @@
i2c_1: i2c at 12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
- interrupts = <0 57 0>;
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -126,7 +151,7 @@
i2c_2: i2c at 12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -136,7 +161,7 @@
i2c_3: i2c at 12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
@@ -153,7 +178,8 @@
rtc: rtc at 101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
- interrupts = <0 43 0>, <0 44 0>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH 05/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos3250.dtsi | 93 ++++++++++++++++++-------------
2 files changed, 71 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 40ea7de44933..9ee16ab30608 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -374,8 +374,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -385,8 +391,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 45 IRQ_TYPE_LEVEL_HIGH>,
+ <0 46 IRQ_TYPE_LEVEL_HIGH>,
+ <0 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index e9d2556c0dfd..9703d81d1eb3 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -20,6 +20,7 @@
#include "exynos4-cpu-thermal.dtsi"
#include "exynos-syscon-restart.dtsi"
#include <dt-bindings/clock/exynos3250.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos3250";
@@ -211,7 +212,8 @@
rtc: rtc at 10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
+ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
+ <0 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&pmu_system_controller>;
status = "disabled";
};
@@ -219,7 +221,7 @@
tmu: tmu at 100C0000 {
compatible = "samsung,exynos3250-tmu";
reg = <0x100C0000 0x100>;
- interrupts = <0 216 0>;
+ interrupts = <0 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_TMU_APBIF>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
@@ -240,8 +242,14 @@
mct at 10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+ interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
+ <0 219 IRQ_TYPE_LEVEL_HIGH>,
+ <0 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>,
+ <0 226 IRQ_TYPE_LEVEL_HIGH>,
+ <0 227 IRQ_TYPE_LEVEL_HIGH>,
+ <0 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
@@ -249,24 +257,24 @@
pinctrl_1: pinctrl at 11000000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
+ interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
- interrupts = <0 48 0>;
+ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,exynos3250-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
+ interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
};
jpeg: codec at 11830000 {
compatible = "samsung,exynos3250-jpeg";
reg = <0x11830000 0x1000>;
- interrupts = <0 171 0>;
+ interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
clock-names = "jpeg", "sclk";
power-domains = <&pd_cam>;
@@ -280,7 +288,8 @@
sysmmu_jpeg: sysmmu at 11A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <0 156 0>, <0 161 0>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>,
+ <0 161 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -291,7 +300,9 @@
compatible = "samsung,exynos3250-fimd";
reg = <0x11c00000 0x30000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>,
+ <0 85 IRQ_TYPE_LEVEL_HIGH>,
+ <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
@@ -303,7 +314,7 @@
dsi_0: dsi at 11C80000 {
compatible = "samsung,exynos3250-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -318,7 +329,8 @@
sysmmu_fimd0: sysmmu at 11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>,
+ <0 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -328,7 +340,7 @@
hsotg: hsotg at 12480000 {
compatible = "snps,dwc2";
reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
+ interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -339,7 +351,7 @@
mshc_0: mshc at 12510000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
+ interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -351,7 +363,7 @@
mshc_1: mshc at 12520000 {
compatible = "samsung,exynos5420-dw-mshc";
reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
+ interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -363,7 +375,7 @@
mshc_2: mshc at 12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
+ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -391,7 +403,7 @@
pdma0: pdma at 12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
+ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -402,7 +414,7 @@
pdma1: pdma at 12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
+ interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -415,7 +427,7 @@
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>;
- interrupts = <0 137 0>;
+ interrupts = <0 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
@@ -427,7 +439,7 @@
mfc: codec at 13400000 {
compatible = "samsung,mfc-v7";
reg = <0x13400000 0x10000>;
- interrupts = <0 102 0>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "mfc", "sclk_mfc";
clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
power-domains = <&pd_mfc>;
@@ -437,7 +449,8 @@
sysmmu_mfc: sysmmu at 13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <0 96 0>, <0 98 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>,
+ <0 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
@@ -447,7 +460,7 @@
serial_0: serial at 13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -458,7 +471,7 @@
serial_1: serial at 13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -469,7 +482,7 @@
serial_2: serial at 13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
+ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
@@ -482,7 +495,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -495,7 +508,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -508,7 +521,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
+ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -521,7 +534,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
+ interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -534,7 +547,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
+ interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -547,7 +560,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -560,7 +573,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
+ interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -573,7 +586,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
+ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +597,7 @@
spi_0: spi at 13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
+ interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -600,7 +613,7 @@
spi_1: spi at 13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
+ interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -616,7 +629,7 @@
i2s2: i2s at 13970000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13970000 0x100>;
- interrupts = <0 126 0>;
+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0";
dmas = <&pdma0 14>, <&pdma0 13>;
@@ -629,15 +642,19 @@
pwm: pwm at 139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 108 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a7-pmu";
- interrupts = <0 18 0>, <0 19 0>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>;
};
ppmu_dmc0: ppmu_dmc0 at 106a0000 {
--
2.7.4
^ permalink raw reply related
* [PATCH 04/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4415
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos4415.dtsi | 92 ++++++++++++++++++-------------
2 files changed, 70 insertions(+), 42 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
index 75af9c56123e..4863147be39a 100644
--- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
@@ -358,8 +358,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
- <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
+ <0 33 IRQ_TYPE_LEVEL_HIGH>,
+ <0 34 IRQ_TYPE_LEVEL_HIGH>,
+ <0 35 IRQ_TYPE_LEVEL_HIGH>,
+ <0 36 IRQ_TYPE_LEVEL_HIGH>,
+ <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -369,8 +375,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
- <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <0 43 IRQ_TYPE_LEVEL_HIGH>,
+ <0 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 45 IRQ_TYPE_LEVEL_HIGH>,
+ <0 46 IRQ_TYPE_LEVEL_HIGH>,
+ <0 47 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
index 3c40f8a956dd..2ad6b6f9a37b 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/clock/exynos4415.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "samsung,exynos4415";
@@ -105,7 +106,7 @@
pinctrl_2: pinctrl at 03860000 {
compatible = "samsung,exynos4415-pinctrl";
reg = <0x03860000 0x1000>;
- interrupts = <0 242 0>;
+ interrupts = <0 242 IRQ_TYPE_LEVEL_HIGH>;
};
chipid at 10000000 {
@@ -180,15 +181,21 @@
rtc: rtc at 10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
- interrupts = <0 73 0>, <0 74 0>;
+ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, <0 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
mct at 10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
- <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+ interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
+ <0 219 IRQ_TYPE_LEVEL_HIGH>,
+ <0 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>,
+ <0 226 IRQ_TYPE_LEVEL_HIGH>,
+ <0 227 IRQ_TYPE_LEVEL_HIGH>,
+ <0 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
clock-names = "fin_pll", "mct";
};
@@ -227,26 +234,28 @@
pinctrl_1: pinctrl at 11000000 {
compatible = "samsung,exynos4415-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 225 0>;
+ interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 48 0>;
+ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,exynos4415-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 240 0>;
+ interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
};
fimd: fimd at 11C00000 {
compatible = "samsung,exynos4415-fimd";
reg = <0x11C00000 0x30000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
- interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>,
+ <0 85 IRQ_TYPE_LEVEL_HIGH>,
+ <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
@@ -258,7 +267,7 @@
dsi_0: dsi at 11C80000 {
compatible = "samsung,exynos4415-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 83 0>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
samsung,phy-type = <0>;
samsung,power-domain = <&pd_lcd0>;
phys = <&mipi_phy 1>;
@@ -273,7 +282,8 @@
sysmmu_fimd0: sysmmu at 11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <0 80 0>, <0 81 0>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>,
+ <0 81 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -283,7 +293,7 @@
hsotg: hsotg at 12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
- interrupts = <0 141 0>;
+ interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBDEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -294,7 +304,7 @@
mshc_0: mshc at 12510000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12510000 0x1000>;
- interrupts = <0 142 0>;
+ interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -306,7 +316,7 @@
mshc_1: mshc at 12520000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12520000 0x1000>;
- interrupts = <0 143 0>;
+ interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -318,7 +328,7 @@
mshc_2: mshc at 12530000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12530000 0x1000>;
- interrupts = <0 144 0>;
+ interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
clock-names = "biu", "ciu";
fifo-depth = <0x80>;
@@ -330,7 +340,7 @@
ehci: ehci at 12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
- interrupts = <0 140 0>;
+ interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBHOST>;
clock-names = "usbhost";
status = "disabled";
@@ -356,7 +366,7 @@
ohci: ohci at 12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
- interrupts = <0 140 0>;
+ interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBHOST>;
clock-names = "usbhost";
status = "disabled";
@@ -390,7 +400,7 @@
pdma0: pdma at 12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 138 0>;
+ interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -401,7 +411,7 @@
pdma1: pdma at 12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 139 0>;
+ interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -414,7 +424,7 @@
compatible = "samsung,exynos3250-adc",
"samsung,exynos-adc-v2";
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
- interrupts = <0 137 0>;
+ interrupts = <0 137 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc", "sclk";
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
#io-channel-cells = <1>;
@@ -425,7 +435,7 @@
serial_0: serial at 13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -434,7 +444,7 @@
serial_1: serial at 13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 110 0>;
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -443,7 +453,7 @@
serial_2: serial at 13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 111 0>;
+ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -452,7 +462,7 @@
serial_3: serial at 13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
@@ -463,7 +473,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 113 0>;
+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -476,7 +486,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 114 0>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -489,7 +499,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 115 0>;
+ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -502,7 +512,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 116 0>;
+ interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -515,7 +525,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 117 0>;
+ interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -528,7 +538,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 118 0>;
+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -541,7 +551,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 119 0>;
+ interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -554,7 +564,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 120 0>;
+ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -565,7 +575,7 @@
spi_0: spi at 13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 121 0>;
+ interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -581,7 +591,7 @@
spi_1: spi at 13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 122 0>;
+ interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -597,7 +607,7 @@
spi_2: spi at 13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
- interrupts = <0 123 0>;
+ interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -619,7 +629,7 @@
i2s0: i2s at 3830000 {
compatible = "samsung,s5pv210-i2s";
reg = <0x03830000 0x100>;
- interrupts = <0 124 0>;
+ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0";
@@ -634,15 +644,21 @@
pwm: pwm at 139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
- <0 107 0>, <0 108 0>;
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 108 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
status = "disabled";
};
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 03/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere, also
for one private interrupt.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 20 ++++++++++---
arch/arm/boot/dts/exynos4x12.dtsi | 48 ++++++++++++++++++++-----------
2 files changed, 48 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 856b29254374..d579accc95db 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -579,8 +579,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -590,8 +596,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 3394bdcf10ae..2f52b685daf9 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -88,11 +88,11 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
<1 &combiner 12 5>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 1 12 0>;
+ <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -112,7 +112,7 @@
g2d: g2d at 10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
iommus = <&sysmmu_g2d>;
@@ -127,7 +127,7 @@
fimc_lite_0: fimc-lite at 12390000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x12390000 0x1000>;
- interrupts = <0 105 0>;
+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>;
clock-names = "flite";
@@ -138,7 +138,7 @@
fimc_lite_1: fimc-lite at 123A0000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0x123A0000 0x1000>;
- interrupts = <0 106 0>;
+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE1>;
clock-names = "flite";
@@ -149,7 +149,8 @@
fimc_is: fimc-is at 12000000 {
compatible = "samsung,exynos4212-fimc-is", "simple-bus";
reg = <0x12000000 0x260000>;
- interrupts = <0 90 0>, <0 95 0>;
+ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>,
+ <0 95 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&clock CLK_FIMC_LITE0>,
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
@@ -200,7 +201,7 @@
mshc_0: mmc at 12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
- interrupts = <0 77 0>;
+ interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <0x80>;
@@ -461,11 +462,26 @@
};
&combiner {
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
- <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>,
+ <0 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0 48 IRQ_TYPE_LEVEL_HIGH>,
+ <0 42 IRQ_TYPE_LEVEL_HIGH>;
};
&exynos_usbphy {
@@ -529,18 +545,18 @@
&pinctrl_0 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
&pinctrl_1 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -554,7 +570,7 @@
&pinctrl_3 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x106E0000 0x1000>;
- interrupts = <0 72 0>;
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
};
&pmu_system_controller {
--
2.7.4
^ permalink raw reply related
* [PATCH 02/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 20 +++++++++++++----
arch/arm/boot/dts/exynos4210.dtsi | 36 ++++++++++++++++++++-----------
2 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 9331c6252eff..152f324f44c7 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -535,8 +535,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
- <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+ interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>,
+ <0 17 IRQ_TYPE_LEVEL_HIGH>,
+ <0 18 IRQ_TYPE_LEVEL_HIGH>,
+ <0 19 IRQ_TYPE_LEVEL_HIGH>,
+ <0 20 IRQ_TYPE_LEVEL_HIGH>,
+ <0 21 IRQ_TYPE_LEVEL_HIGH>,
+ <0 22 IRQ_TYPE_LEVEL_HIGH>,
+ <0 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
@@ -546,8 +552,14 @@
interrupt-controller;
interrupt-parent = <&gic>;
- interrupts = <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
- <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0 25 IRQ_TYPE_LEVEL_HIGH>,
+ <0 26 IRQ_TYPE_LEVEL_HIGH>,
+ <0 27 IRQ_TYPE_LEVEL_HIGH>,
+ <0 28 IRQ_TYPE_LEVEL_HIGH>,
+ <0 29 IRQ_TYPE_LEVEL_HIGH>,
+ <0 30 IRQ_TYPE_LEVEL_HIGH>,
+ <0 31 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2d9b02967105..736ab8587ab0 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -109,12 +109,12 @@
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
- interrupt-map = <0 &gic 0 57 0>,
- <1 &gic 0 69 0>,
+ interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
<2 &combiner 12 6>,
<3 &combiner 12 7>,
- <4 &gic 0 42 0>,
- <5 &gic 0 48 0>;
+ <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
+ <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -127,18 +127,18 @@
pinctrl_0: pinctrl at 11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
- interrupts = <0 47 0>;
+ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_1: pinctrl at 11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
- interrupts = <0 46 0>;
+ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
- interrupts = <0 32 0>;
+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -182,7 +182,7 @@
g2d: g2d at 12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
- interrupts = <0 89 0>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
clock-names = "sclk_fimg2d", "fimg2d";
power-domains = <&pd_lcd0>;
@@ -424,10 +424,22 @@
&combiner {
samsung,combiner-nr = <16>;
- interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
- <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
- <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
- <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>,
+ <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0 5 IRQ_TYPE_LEVEL_HIGH>,
+ <0 6 IRQ_TYPE_LEVEL_HIGH>,
+ <0 7 IRQ_TYPE_LEVEL_HIGH>,
+ <0 8 IRQ_TYPE_LEVEL_HIGH>,
+ <0 9 IRQ_TYPE_LEVEL_HIGH>,
+ <0 10 IRQ_TYPE_LEVEL_HIGH>,
+ <0 11 IRQ_TYPE_LEVEL_HIGH>,
+ <0 12 IRQ_TYPE_LEVEL_HIGH>,
+ <0 13 IRQ_TYPE_LEVEL_HIGH>,
+ <0 14 IRQ_TYPE_LEVEL_HIGH>,
+ <0 15 IRQ_TYPE_LEVEL_HIGH>;
};
&mdma1 {
--
2.7.4
^ permalink raw reply related
* [PATCH 01/10] ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474054971-16831-1-git-send-email-krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Choose level high everywhere.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos4.dtsi | 94 ++++++++++++++++++++++--------------------
1 file changed, 50 insertions(+), 44 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 5f034eb5a5e2..e6f4da7f0038 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -21,6 +21,7 @@
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
@@ -168,7 +169,7 @@
dsi_0: dsi at 11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
- interrupts = <0 79 0>;
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
@@ -191,7 +192,7 @@
fimc_0: fimc at 11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
- interrupts = <0 84 0>;
+ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -203,7 +204,7 @@
fimc_1: fimc at 11810000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11810000 0x1000>;
- interrupts = <0 85 0>;
+ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -215,7 +216,7 @@
fimc_2: fimc at 11820000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11820000 0x1000>;
- interrupts = <0 86 0>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -227,7 +228,7 @@
fimc_3: fimc at 11830000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11830000 0x1000>;
- interrupts = <0 87 0>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
@@ -239,7 +240,7 @@
csis_0: csis at 11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x4000>;
- interrupts = <0 78 0>;
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
clock-names = "csis", "sclk_csis";
bus-width = <4>;
@@ -254,7 +255,7 @@
csis_1: csis at 11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
- interrupts = <0 80 0>;
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
bus-width = <2>;
@@ -270,7 +271,7 @@
watchdog: watchdog at 10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
- interrupts = <0 43 0>;
+ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
status = "disabled";
@@ -280,7 +281,8 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupt-parent = <&pmu_system_controller>;
- interrupts = <0 44 0>, <0 45 0>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
+ <0 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
status = "disabled";
@@ -289,7 +291,7 @@
keypad: keypad at 100A0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
- interrupts = <0 109 0>;
+ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
@@ -298,7 +300,7 @@
sdhci_0: sdhci at 12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
- interrupts = <0 73 0>;
+ interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -307,7 +309,7 @@
sdhci_1: sdhci at 12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
- interrupts = <0 74 0>;
+ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -316,7 +318,7 @@
sdhci_2: sdhci at 12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
- interrupts = <0 75 0>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -325,7 +327,7 @@
sdhci_3: sdhci at 12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
- interrupts = <0 76 0>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
@@ -344,7 +346,7 @@
hsotg: hsotg at 12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
- interrupts = <0 71 0>;
+ interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
@@ -355,7 +357,7 @@
ehci: ehci at 12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -381,7 +383,7 @@
ohci: ohci at 12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
- interrupts = <0 70 0>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
@@ -423,7 +425,7 @@
mfc: codec at 13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
+ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
@@ -434,7 +436,7 @@
serial_0: serial at 13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
- interrupts = <0 52 0>;
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
@@ -445,7 +447,7 @@
serial_1: serial at 13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
- interrupts = <0 53 0>;
+ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
@@ -456,7 +458,7 @@
serial_2: serial at 13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
@@ -467,7 +469,7 @@
serial_3: serial at 13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
- interrupts = <0 55 0>;
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>, <&pdma1 18>;
@@ -480,7 +482,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
- interrupts = <0 58 0>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -493,7 +495,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
- interrupts = <0 59 0>;
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -506,7 +508,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
- interrupts = <0 60 0>;
+ interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -519,7 +521,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
- interrupts = <0 61 0>;
+ interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -532,7 +534,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
- interrupts = <0 62 0>;
+ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -545,7 +547,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
- interrupts = <0 63 0>;
+ interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -558,7 +560,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
- interrupts = <0 64 0>;
+ interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -571,7 +573,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
- interrupts = <0 65 0>;
+ interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
@@ -584,7 +586,7 @@
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x138E0000 0x100>;
- interrupts = <0 93 0>;
+ interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
@@ -598,7 +600,7 @@
spi_0: spi at 13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
- interrupts = <0 66 0>;
+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -613,7 +615,7 @@
spi_1: spi at 13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
- interrupts = <0 67 0>;
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -628,7 +630,7 @@
spi_2: spi at 13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
- interrupts = <0 68 0>;
+ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
@@ -643,7 +645,11 @@
pwm: pwm at 139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
- interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
+ <0 38 IRQ_TYPE_LEVEL_HIGH>,
+ <0 39 IRQ_TYPE_LEVEL_HIGH>,
+ <0 40 IRQ_TYPE_LEVEL_HIGH>,
+ <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
@@ -660,7 +666,7 @@
pdma0: pdma at 12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
- interrupts = <0 35 0>;
+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -671,7 +677,7 @@
pdma1: pdma at 12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
- interrupts = <0 36 0>;
+ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -682,7 +688,7 @@
mdma1: mdma at 12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
- interrupts = <0 34 0>;
+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
@@ -712,7 +718,7 @@
jpeg_codec: jpeg-codec at 11840000 {
compatible = "samsung,exynos4210-jpeg";
reg = <0x11840000 0x1000>;
- interrupts = <0 88 0>;
+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_JPEG>;
clock-names = "jpeg";
power-domains = <&pd_cam>;
@@ -722,7 +728,7 @@
rotator: rotator at 12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x64>;
- interrupts = <0 83 0>;
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
@@ -731,7 +737,7 @@
hdmi: hdmi at 12D00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
- interrupts = <0 92 0>;
+ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
"mout_hdmi";
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -746,7 +752,7 @@
hdmicec: cec at 100B0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
- interrupts = <0 114 0>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -757,7 +763,7 @@
mixer: mixer at 12C10000 {
compatible = "samsung,exynos4210-mixer";
- interrupts = <0 91 0>;
+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
@@ -984,7 +990,7 @@
sss: sss at 10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
- interrupts = <0 112 0>;
+ interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
--
2.7.4
^ permalink raw reply related
* [RFC PATCH 00/10] ARM: dts: exynos: Fix invalid GIC interrupt flags
From: Krzysztof Kozlowski @ 2016-09-16 19:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Marek (internally), Geert and Alban reported errors like:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The patchset fixes this issue.
Tested on:
1. Exynos4412: Odroid U3,
2. Exynos5410: Odroid XU,
3. Exynos5422: Odroid XU3.
Other platforms not tested so testing would be highly appreciated.
Best regards,
Krzysztof
Krzysztof Kozlowski (10):
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4210
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4x12
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos4415
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos3250
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5250
ARM: dts: exynos: Fix invalid GIC interrupt flags in
exynos5410/exynos542x
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5260
ARM: dts: exynos: Fix invalid GIC interrupt flags in exynos5440
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos3250.dtsi | 93 +++++++++++++++++-------------
arch/arm/boot/dts/exynos4.dtsi | 94 ++++++++++++++++---------------
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos4210.dtsi | 36 ++++++++----
arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos4415.dtsi | 92 +++++++++++++++++-------------
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 20 +++++--
arch/arm/boot/dts/exynos4x12.dtsi | 48 ++++++++++------
arch/arm/boot/dts/exynos5.dtsi | 60 ++++++++++++++------
arch/arm/boot/dts/exynos5250.dtsi | 80 +++++++++++++-------------
arch/arm/boot/dts/exynos5260.dtsi | 39 ++++++++-----
arch/arm/boot/dts/exynos5410.dtsi | 26 ++++-----
arch/arm/boot/dts/exynos5420.dtsi | 78 ++++++++++++-------------
arch/arm/boot/dts/exynos5440.dtsi | 48 ++++++++++------
arch/arm/boot/dts/exynos54xx.dtsi | 34 +++++------
16 files changed, 485 insertions(+), 323 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2 1/3] ipmi: add an Aspeed BT IPMI BMC driver
From: Corey Minyard @ 2016-09-16 19:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474022367-21029-2-git-send-email-clg@kaod.org>
On 09/16/2016 05:39 AM, C?dric Le Goater wrote:
> From: Alistair Popple <alistair@popple.id.au>
>
> This patch adds a simple device driver to expose the iBT interface on
> Aspeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are
> commonly used as BMCs (BaseBoard Management Controllers) and this
> driver implements the BMC side of the BT interface.
>
> The BT (Block Transfer) interface is used to perform in-band IPMI
> communication between a host and its BMC. Entire messages are buffered
> before sending a notification to the other end, host or BMC, that
> there is data to be read. Usually, the host emits requests and the BMC
> responses but the specification provides a mean for the BMC to send
> SMS Attention (BMC-to-Host attention or System Management Software
> attention) messages.
>
> For this purpose, the driver introduces a specific ioctl on the
> device: 'BT_BMC_IOCTL_SMS_ATN' that can be used by the system running
> on the BMC to signal the host of such an event.
>
> The device name defaults to '/dev/ipmi-bt-host'
Others have reviewed this for style and such, and I have looked
at it from a protocol point of view. it looks to be sound for the
most part. I have some higher level concerns:
There appears to be no handling for multiple simultaneous users.
This interface can only be used by one task at a time, so you should
probably only allow one opener. Well, I guess the BMC could be split
into a reader and a writer task, so I'm not really sure about that, but
I would think in most situations having more than one opener is a
bug. You do call clr_b_busy() on open, for instance, which might be
an issue for multiple openers. Maybe a module parameter for
maximum number of openers? Just want to make sure this was
thought about, at least.
There is also no mutex protecting reading or writing. If multiple
threads call read or write at the same time, it probably wouldn't
work correctly. I think you need a read and a write mutex on the
interface to protect against this.
The spec says:
The BMC must not return a given response once the corresponding
Request-to-Response interval has passed. The BMC can ensure this
by maintaining its own internal list of outstanding requests through
the interface. The BMC could age and expire the entries in the list
by expiring the entries at an interval that is somewhat shorter than
the specified Request-to-Response interval....
On the write side, though, there doesn't seem to be a way to handle a
situation where the host side doesn't respond for a while and the
pending message would need to be discarded.
The spec doesn't mention much about error recovery on this interface,
but the way this is written should be fine, I think.
I'm copying Rocky Craig, who wrote the host side driver for Linux, in
case he wants to comment on this.
This is easy to read and understand, so I think v3 should be good.
Thanks,
-corey
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> [clg: - checkpatch fixes
> - added a devicetree binding documentation
> - replace 'bt_host' by 'bt_bmc' to reflect that the driver is
> the BMC side of the IPMI BT interface
> - renamed the device to 'ipmi-bt-host'
> - introduced a temporary buffer to copy_{to,from}_user
> - used platform_get_irq()
> - moved the driver under drivers/char/ipmi/ but kept it as a misc
> device
> - changed the compatible cell to "aspeed,ast2400-bt-bmc"
> ]
> Signed-off-by: C?dric Le Goater <clg@kaod.org>
> ---
>
> Changes since v1:
>
> - replace 'bt_host' by 'bt_bmc' to reflect that the driver is
> the BMC side of the IPMI BT interface
> - renamed the device to 'ipmi-bt-host'
> - introduced a temporary buffer to copy_{to,from}_user
> - used platform_get_irq()
> - moved the driver under drivers/char/ipmi/ but kept it as a misc
> device
> - changed the compatible cell to "aspeed,ast2400-bt-bmc"
>
> .../bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt | 23 +
> drivers/Makefile | 2 +-
> drivers/char/ipmi/Kconfig | 7 +
> drivers/char/ipmi/Makefile | 1 +
> drivers/char/ipmi/bt-bmc.c | 486 +++++++++++++++++++++
> include/uapi/linux/Kbuild | 1 +
> include/uapi/linux/bt-bmc.h | 18 +
> 7 files changed, 537 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
> create mode 100644 drivers/char/ipmi/bt-bmc.c
> create mode 100644 include/uapi/linux/bt-bmc.h
>
> diff --git a/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt b/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
> new file mode 100644
> index 000000000000..fbbacd958240
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/char/ipmi/aspeed,ast2400-bt-bmc.txt
> @@ -0,0 +1,23 @@
> +* Aspeed BT (Block Transfer) IPMI interface
> +
> +The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
> +(BaseBoard Management Controllers) and the BT interface can be used to
> +perform in-band IPMI communication with their host.
> +
> +Required properties:
> +
> +- compatible : should be "aspeed,ast2400-bt-bmc"
> +- reg: physical address and size of the registers
> +
> +Optional properties:
> +
> +- interrupts: interrupt generated by the BT interface. without an
> + interrupt, the driver will operate in poll mode.
> +
> +Example:
> +
> + ibt at 1e789140 {
> + compatible = "aspeed,ast2400-bt-bmc";
> + reg = <0x1e789140 0x18>;
> + interrupts = <8>;
> + };
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 53abb4a5f736..5a9e7b6b7928 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -21,7 +21,7 @@ obj-y += video/
> obj-y += idle/
>
> # IPMI must come before ACPI in order to provide IPMI opregion support
> -obj-$(CONFIG_IPMI_HANDLER) += char/ipmi/
> +obj-y += char/ipmi/
>
> obj-$(CONFIG_ACPI) += acpi/
> obj-$(CONFIG_SFI) += sfi/
> diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
> index 5a9350b1069a..2c234e3e7513 100644
> --- a/drivers/char/ipmi/Kconfig
> +++ b/drivers/char/ipmi/Kconfig
> @@ -76,3 +76,10 @@ config IPMI_POWEROFF
> the IPMI management controller is capable of this.
>
> endif # IPMI_HANDLER
> +
> +config ASPEED_BT_IPMI_BMC
> + tristate "BT IPMI bmc driver"
> + help
> + Provides a driver for the BT (Block Transfer) IPMI interface
> + found on Aspeed SOCs (AST2400 and AST2500). The driver
> + implements the BMC side of the BT interface.
> diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile
> index f3ffde1f5f1f..0d98cd91def1 100644
> --- a/drivers/char/ipmi/Makefile
> +++ b/drivers/char/ipmi/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_IPMI_SSIF) += ipmi_ssif.o
> obj-$(CONFIG_IPMI_POWERNV) += ipmi_powernv.o
> obj-$(CONFIG_IPMI_WATCHDOG) += ipmi_watchdog.o
> obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o
> +obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o
> diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c
> new file mode 100644
> index 000000000000..b96cb421e1c2
> --- /dev/null
> +++ b/drivers/char/ipmi/bt-bmc.c
> @@ -0,0 +1,486 @@
> +/*
> + * Copyright (c) 2015-2016, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/errno.h>
> +#include <linux/poll.h>
> +#include <linux/sched.h>
> +#include <linux/spinlock.h>
> +#include <linux/slab.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/miscdevice.h>
> +#include <linux/timer.h>
> +#include <linux/jiffies.h>
> +#include <linux/bt-bmc.h>
> +
> +/*
> + * This is a BMC device used to communicate to the host
> + */
> +#define DEVICE_NAME "ipmi-bt-host"
> +
> +#define BT_IO_BASE 0xe4
> +#define BT_IRQ 10
> +
> +#define BT_CR0 0x0
> +#define BT_CR0_IO_BASE 16
> +#define BT_CR0_IRQ 12
> +#define BT_CR0_EN_CLR_SLV_RDP 0x8
> +#define BT_CR0_EN_CLR_SLV_WRP 0x4
> +#define BT_CR0_ENABLE_IBT 0x1
> +#define BT_CR1 0x4
> +#define BT_CR1_IRQ_H2B 0x01
> +#define BT_CR1_IRQ_HBUSY 0x40
> +#define BT_CR2 0x8
> +#define BT_CR2_IRQ_H2B 0x01
> +#define BT_CR2_IRQ_HBUSY 0x40
> +#define BT_CR3 0xc
> +#define BT_CTRL 0x10
> +#define BT_CTRL_B_BUSY 0x80
> +#define BT_CTRL_H_BUSY 0x40
> +#define BT_CTRL_OEM0 0x20
> +#define BT_CTRL_SMS_ATN 0x10
> +#define BT_CTRL_B2H_ATN 0x08
> +#define BT_CTRL_H2B_ATN 0x04
> +#define BT_CTRL_CLR_RD_PTR 0x02
> +#define BT_CTRL_CLR_WR_PTR 0x01
> +#define BT_BMC2HOST 0x14
> +#define BT_INTMASK 0x18
> +#define BT_INTMASK_B2H_IRQEN 0x01
> +#define BT_INTMASK_B2H_IRQ 0x02
> +#define BT_INTMASK_BMC_HWRST 0x80
> +
> +struct bt_bmc {
> + struct device dev;
> + struct miscdevice miscdev;
> + void __iomem *base;
> + int open_count;
> + int irq;
> + wait_queue_head_t queue;
> + struct timer_list poll_timer;
> +};
> +
> +static u8 bt_inb(struct bt_bmc *bt_bmc, int reg)
> +{
> + return ioread8(bt_bmc->base + reg);
> +}
> +
> +static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg)
> +{
> + iowrite8(data, bt_bmc->base + reg);
> +}
> +
> +static void clr_rd_ptr(struct bt_bmc *bt_bmc)
> +{
> + bt_outb(bt_bmc, BT_CTRL_CLR_RD_PTR, BT_CTRL);
> +}
> +
> +static void clr_wr_ptr(struct bt_bmc *bt_bmc)
> +{
> + bt_outb(bt_bmc, BT_CTRL_CLR_WR_PTR, BT_CTRL);
> +}
> +
> +static void clr_h2b_atn(struct bt_bmc *bt_bmc)
> +{
> + bt_outb(bt_bmc, BT_CTRL_H2B_ATN, BT_CTRL);
> +}
> +
> +static void set_b_busy(struct bt_bmc *bt_bmc)
> +{
> + if (!(bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY))
> + bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
> +}
> +
> +static void clr_b_busy(struct bt_bmc *bt_bmc)
> +{
> + if (bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_B_BUSY)
> + bt_outb(bt_bmc, BT_CTRL_B_BUSY, BT_CTRL);
> +}
> +
> +static void set_b2h_atn(struct bt_bmc *bt_bmc)
> +{
> + bt_outb(bt_bmc, BT_CTRL_B2H_ATN, BT_CTRL);
> +}
> +
> +static u8 bt_read(struct bt_bmc *bt_bmc)
> +{
> + return bt_inb(bt_bmc, BT_BMC2HOST);
> +}
> +
> +static ssize_t bt_readn(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
> +{
> + int i;
> +
> + for (i = 0; i < n; i++)
> + buf[i] = bt_read(bt_bmc);
> + return n;
> +}
> +
> +static void bt_write(struct bt_bmc *bt_bmc, u8 c)
> +{
> + bt_outb(bt_bmc, c, BT_BMC2HOST);
> +}
> +
> +static ssize_t bt_writen(struct bt_bmc *bt_bmc, u8 *buf, size_t n)
> +{
> + int i;
> +
> + for (i = 0; i < n; i++)
> + bt_write(bt_bmc, buf[i]);
> + return n;
> +}
> +
> +static void set_sms_atn(struct bt_bmc *bt_bmc)
> +{
> + bt_outb(bt_bmc, BT_CTRL_SMS_ATN, BT_CTRL);
> +}
> +
> +static struct bt_bmc *file_bt_bmc(struct file *file)
> +{
> + return container_of(file->private_data, struct bt_bmc, miscdev);
> +}
> +
> +static int bt_bmc_open(struct inode *inode, struct file *file)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> +
> + clr_b_busy(bt_bmc);
> +
> + return 0;
> +}
> +
> +#define BT_BMC_BUFFER_SIZE 256
> +
> +/*
> + * The BT (Block Transfer) interface means that entire messages are
> + * buffered by the host before a notification is sent to the BMC that
> + * there is data to be read. The first byte is the length and the
> + * message data follows. The read operation just tries to capture the
> + * whole before returning it to userspace.
> + */
> +static ssize_t bt_bmc_read(struct file *file, char __user *buf,
> + size_t count, loff_t *ppos)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> + u8 len;
> + int len_byte = 1;
> + u8 kbuffer[BT_BMC_BUFFER_SIZE];
> + ssize_t ret = 0;
> + ssize_t nread;
> +
> + if (!access_ok(VERIFY_WRITE, buf, count))
> + return -EFAULT;
> +
> + WARN_ON(*ppos);
> +
> + if (wait_event_interruptible(bt_bmc->queue,
> + bt_inb(bt_bmc, BT_CTRL) & BT_CTRL_H2B_ATN))
> + return -ERESTARTSYS;
> +
> + set_b_busy(bt_bmc);
> + clr_h2b_atn(bt_bmc);
> + clr_rd_ptr(bt_bmc);
> +
> + /*
> + * The BT frames start with the message length, which does not
> + * include the length byte.
> + */
> + kbuffer[0] = bt_read(bt_bmc);
> + len = kbuffer[0];
> +
> + /* We pass the length back to userspace as well */
> + if (len + 1 > count)
> + len = count - 1;
> +
> + while (len) {
> + nread = min_t(ssize_t, len, sizeof(kbuffer) - len_byte);
> +
> + bt_readn(bt_bmc, kbuffer + len_byte, nread);
> +
> + if (copy_to_user(buf, kbuffer, nread + len_byte)) {
> + ret = -EFAULT;
> + break;
> + }
> + len -= nread;
> + buf += nread + len_byte;
> + ret += nread + len_byte;
> + len_byte = 0;
> + }
> +
> + clr_b_busy(bt_bmc);
> +
> + return ret;
> +}
> +
> +static ssize_t bt_bmc_write(struct file *file, const char __user *buf,
> + size_t count, loff_t *ppos)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> + u8 kbuffer[BT_BMC_BUFFER_SIZE];
> + ssize_t ret = 0;
> + ssize_t nwritten;
> +
> + if (!access_ok(VERIFY_READ, buf, count))
> + return -EFAULT;
> +
> + WARN_ON(*ppos);
> +
> + /* There's no interrupt for clearing bmc busy so we have to
> + * poll
> + */
> + if (wait_event_interruptible(bt_bmc->queue,
> + !(bt_inb(bt_bmc, BT_CTRL) &
> + (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN))))
> + return -ERESTARTSYS;
> +
> + clr_wr_ptr(bt_bmc);
> +
> + while (count) {
> + nwritten = min_t(ssize_t, count, sizeof(kbuffer));
> + if (copy_from_user(&kbuffer, buf, nwritten)) {
> + ret = -EFAULT;
> + break;
> + }
> +
> + bt_writen(bt_bmc, kbuffer, nwritten);
> +
> + count -= nwritten;
> + buf += nwritten;
> + ret += nwritten;
> + }
> +
> + set_b2h_atn(bt_bmc);
> +
> + return ret;
> +}
> +
> +static long bt_bmc_ioctl(struct file *file, unsigned int cmd,
> + unsigned long param)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> +
> + switch (cmd) {
> + case BT_BMC_IOCTL_SMS_ATN:
> + set_sms_atn(bt_bmc);
> + return 0;
> + }
> + return -EINVAL;
> +}
> +
> +static int bt_bmc_release(struct inode *inode, struct file *file)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> +
> + set_b_busy(bt_bmc);
> + return 0;
> +}
> +
> +static unsigned int bt_bmc_poll(struct file *file, poll_table *wait)
> +{
> + struct bt_bmc *bt_bmc = file_bt_bmc(file);
> + unsigned int mask = 0;
> + uint8_t ctrl;
> +
> + poll_wait(file, &bt_bmc->queue, wait);
> +
> + ctrl = bt_inb(bt_bmc, BT_CTRL);
> +
> + if (ctrl & BT_CTRL_H2B_ATN)
> + mask |= POLLIN;
> +
> + if (!(ctrl & (BT_CTRL_H_BUSY | BT_CTRL_B2H_ATN)))
> + mask |= POLLOUT;
> +
> + return mask;
> +}
> +
> +static const struct file_operations bt_bmc_fops = {
> + .owner = THIS_MODULE,
> + .open = bt_bmc_open,
> + .read = bt_bmc_read,
> + .write = bt_bmc_write,
> + .release = bt_bmc_release,
> + .poll = bt_bmc_poll,
> + .unlocked_ioctl = bt_bmc_ioctl,
> +};
> +
> +static void poll_timer(unsigned long data)
> +{
> + struct bt_bmc *bt_bmc = (void *)data;
> +
> + bt_bmc->poll_timer.expires += msecs_to_jiffies(500);
> + wake_up(&bt_bmc->queue);
> + add_timer(&bt_bmc->poll_timer);
> +}
> +
> +static irqreturn_t bt_bmc_irq(int irq, void *arg)
> +{
> + struct bt_bmc *bt_bmc = arg;
> + uint32_t reg;
> +
> + reg = ioread32(bt_bmc->base + BT_CR2);
> + reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY;
> + if (!reg)
> + return IRQ_NONE;
> +
> + /* ack pending IRQs */
> + iowrite32(reg, bt_bmc->base + BT_CR2);
> +
> + wake_up(&bt_bmc->queue);
> + return IRQ_HANDLED;
> +}
> +
> +static int bt_bmc_config_irq(struct bt_bmc *bt_bmc,
> + struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + uint32_t reg;
> + int rc;
> +
> + bt_bmc->irq = platform_get_irq(pdev, 0);
> + if (!bt_bmc->irq)
> + return -ENODEV;
> +
> + rc = devm_request_irq(dev, bt_bmc->irq, bt_bmc_irq, IRQF_SHARED,
> + DEVICE_NAME, bt_bmc);
> + if (rc < 0) {
> + dev_warn(dev, "Unable to request IRQ %d\n", bt_bmc->irq);
> + bt_bmc->irq = 0;
> + return rc;
> + }
> +
> + /* Configure IRQs on the bmc clearing the H2B and HBUSY bits;
> + * H2B will be asserted when the bmc has data for us; HBUSY
> + * will be cleared (along with B2H) when we can write the next
> + * message to the BT buffer
> + */
> + reg = ioread32(bt_bmc->base + BT_CR1);
> + reg |= BT_CR1_IRQ_H2B | BT_CR1_IRQ_HBUSY;
> + iowrite32(reg, bt_bmc->base + BT_CR1);
> +
> + return 0;
> +}
> +
> +static int bt_bmc_probe(struct platform_device *pdev)
> +{
> + struct bt_bmc *bt_bmc;
> + struct device *dev;
> + struct resource *res;
> + int rc;
> +
> + if (!pdev || !pdev->dev.of_node)
> + return -ENODEV;
> +
> + dev = &pdev->dev;
> + dev_info(dev, "Found bt bmc device\n");
> +
> + bt_bmc = devm_kzalloc(dev, sizeof(*bt_bmc), GFP_KERNEL);
> + if (!bt_bmc)
> + return -ENOMEM;
> +
> + dev_set_drvdata(&pdev->dev, bt_bmc);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Unable to find resources\n");
> + rc = -ENXIO;
> + goto out_free;
> + }
> +
> + bt_bmc->base = devm_ioremap_resource(&pdev->dev, res);
> + if (!bt_bmc->base) {
> + rc = -ENOMEM;
> + goto out_free;
> + }
> +
> + init_waitqueue_head(&bt_bmc->queue);
> +
> + bt_bmc->miscdev.minor = MISC_DYNAMIC_MINOR,
> + bt_bmc->miscdev.name = DEVICE_NAME,
> + bt_bmc->miscdev.fops = &bt_bmc_fops,
> + bt_bmc->miscdev.parent = dev;
> + rc = misc_register(&bt_bmc->miscdev);
> + if (rc) {
> + dev_err(dev, "Unable to register device\n");
> + goto out_unmap;
> + }
> +
> + bt_bmc_config_irq(bt_bmc, pdev);
> +
> + if (bt_bmc->irq) {
> + dev_info(dev, "Using IRQ %d\n", bt_bmc->irq);
> + } else {
> + dev_info(dev, "No IRQ; using timer\n");
> + setup_timer(&bt_bmc->poll_timer, poll_timer,
> + (unsigned long)bt_bmc);
> + bt_bmc->poll_timer.expires = jiffies + msecs_to_jiffies(10);
> + add_timer(&bt_bmc->poll_timer);
> + }
> +
> + iowrite32((BT_IO_BASE << BT_CR0_IO_BASE) |
> + (BT_IRQ << BT_CR0_IRQ) |
> + BT_CR0_EN_CLR_SLV_RDP |
> + BT_CR0_EN_CLR_SLV_WRP |
> + BT_CR0_ENABLE_IBT,
> + bt_bmc->base + BT_CR0);
> +
> + clr_b_busy(bt_bmc);
> +
> + return 0;
> +
> +out_unmap:
> + devm_iounmap(&pdev->dev, bt_bmc->base);
> +
> +out_free:
> + devm_kfree(dev, bt_bmc);
> + return rc;
> +
> +}
> +
> +static int bt_bmc_remove(struct platform_device *pdev)
> +{
> + struct bt_bmc *bt_bmc = dev_get_drvdata(&pdev->dev);
> +
> + misc_deregister(&bt_bmc->miscdev);
> + if (!bt_bmc->irq)
> + del_timer_sync(&bt_bmc->poll_timer);
> + devm_iounmap(&pdev->dev, bt_bmc->base);
> + devm_kfree(&pdev->dev, bt_bmc);
> + bt_bmc = NULL;
> +
> + return 0;
> +}
> +
> +static const struct of_device_id bt_bmc_match[] = {
> + { .compatible = "aspeed,ast2400-bt-bmc" },
> + { },
> +};
> +
> +static struct platform_driver bt_bmc_driver = {
> + .driver = {
> + .name = DEVICE_NAME,
> + .of_match_table = bt_bmc_match,
> + },
> + .probe = bt_bmc_probe,
> + .remove = bt_bmc_remove,
> +};
> +
> +module_platform_driver(bt_bmc_driver);
> +
> +MODULE_DEVICE_TABLE(of, bt_bmc_match);
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Alistair Popple <alistair@popple.id.au>");
> +MODULE_DESCRIPTION("Linux device interface to the BT interface");
> diff --git a/include/uapi/linux/Kbuild b/include/uapi/linux/Kbuild
> index 185f8ea2702f..17b12942c67d 100644
> --- a/include/uapi/linux/Kbuild
> +++ b/include/uapi/linux/Kbuild
> @@ -74,6 +74,7 @@ header-y += bpf_common.h
> header-y += bpf.h
> header-y += bpqether.h
> header-y += bsg.h
> +header-y += bt-bmc.h
> header-y += btrfs.h
> header-y += can.h
> header-y += capability.h
> diff --git a/include/uapi/linux/bt-bmc.h b/include/uapi/linux/bt-bmc.h
> new file mode 100644
> index 000000000000..d9ec766a63d0
> --- /dev/null
> +++ b/include/uapi/linux/bt-bmc.h
> @@ -0,0 +1,18 @@
> +/*
> + * Copyright (c) 2015-2016, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#ifndef _UAPI_LINUX_BT_BMC_H
> +#define _UAPI_LINUX_BT_BMC_H
> +
> +#include <linux/ioctl.h>
> +
> +#define __BT_BMC_IOCTL_MAGIC 0xb1
> +#define BT_BMC_IOCTL_SMS_ATN _IO(__BT_BMC_IOCTL_MAGIC, 0x00)
> +
> +#endif /* _UAPI_LINUX_BT_BMC_H */
^ permalink raw reply
* [PATCH v6 1/2] sdhci-of-arasan: Add device tree parameter xlnx-fails-without-test-cd bit
From: Rob Herring @ 2016-09-16 19:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1473363766-12652-1-git-send-email-zach.brown@ni.com>
On Thu, Sep 08, 2016 at 02:42:45PM -0500, Zach Brown wrote:
> The sdhci controller on xilinx zynq devices will not function unless
> the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
> In cases where it is impossible to provide the CD bit in hardware,
> setting the controller to test mode and then setting inserted to true
> will get the controller to function without the CD bit.
>
> The device property "xlnx-fails-without-test-cd" will let the arasan
> driver know the controller does not have the CD line wired and that the
> controller does not function without it.
>
> Signed-off-by: Zach Brown <zach.brown@ni.com>
> ---
> v2:
> * improved commit messages
> * removed fake-cd device property
> * removed fake-cd quirk
> * use broken-cd device property
> * documented new usage of broken-cd
> v3:
> * removed new usage of broken-cd
> * created fails-without-test-cd device property
> * created arasan controller specific quirk
> v4:
> * changed fails-without-test-cd to xlnx-fails-without-test-cd
> * removed extra blank line
> v5:
> * Fixed style mistake
> * Changed (1 << 0 ) to BIT(0)
> v6:
> * Fixed style mistakes
> * Condensed unnecessarily long variable names
> * Removed line wraps that were no longer necessary.
> * Rebased changes off Ulf's mmc tree's next branch.
>
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> df --gt /Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 3404afa..e71f043 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -21,6 +21,10 @@ Required Properties:
> - interrupts: Interrupt specifier
> - interrupt-parent: Phandle for the interrupt controller that services
> interrupts for this device.
> +Optional Properties:
> +- xlnx-fails-without-test-cd: when present, the controller doesn't work when
xlnx,fails...
With that,
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 0/2] KVM: ARM: Enable vtimers with user space gic
From: Alexander Graf @ 2016-09-16 19:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916134619.jjiaplhxgkkl5qri@kamzik.localdomain>
> Am 16.09.2016 um 15:46 schrieb Andrew Jones <drjones@redhat.com>:
>
>> On Fri, Sep 16, 2016 at 03:30:27PM +0200, Christoffer Dall wrote:
>>> On Fri, Sep 16, 2016 at 02:31:42PM +0200, Paolo Bonzini wrote:
>>>
>>>
>>> On 16/09/2016 14:30, Christoffer Dall wrote:
>>>>>>> This patch set allows user space to receive vtimer events as well as mask
>>>>>>> them, so that we can handle all vtimer related interrupt injection from user
>>>>>>> space, enabling us to use architected timer with user space gic emulation.
>>>>>>
>>>>>> I have already voiced my concerns in the past, including face to face,
>>>>>> and I'm going to repeat it: I not keen at all on adding a new userspace
>>>>>> interface that is going to bitrot extremely quickly.
>>>>>
>>>>> You don't have automated tests set up? It's not going to bitrot if you
>>>>> test it, either with kvm-unit-tests or just by smoke-testing Linux.
>>>>> It's _for_ the raspi, but it's not limited to it.
>>>>
>>>> Our automated testing situation is not great, no. Something we're
>>>> looking at, but have resource problems with.
>>>
>>> But it's not a good reason to hold back a feature...
>>
>> I didn't say that exactly, but choosing not to merge something we cannot
>> maintain and which we're not paid to look after and where there's a
>> minimal interest, is not entirely unreasonable.
>>
>> That being said, I'm not categorically against these patches, but I
>> share Marc's view that we've already seen that non-vgic support had been
>> broken for multiple versions without anyone complaining, and without
>> automated testing or substantial interest in the work, the patches
>> really are likely to bit-rot.
>>
>> But I haven't even looked at the patches in detail, I was just replying
>> to the comment about testing.
>
> This may be a great time to start encouraging feature writers to submit
> kvm-unit-tests patches at the same time as the feature (Hi Alex :-)
I actually started off implementing this with the help of kvm-unit-tests. It's awesome!
I'm lacking actual irq support to make the test reasonable though and wanted to get the kernel bits out first :). But I'll sit down on that again soon I hope.
Alex
^ permalink raw reply
* [PATCH v2] input: touchscreen: Add support for Elan eKTF2127 touchscreen controller
From: Dmitry Torokhov @ 2016-09-16 18:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160902140935.GA19453@rob-hp-laptop>
On Fri, Sep 02, 2016 at 09:09:35AM -0500, Rob Herring wrote:
> On Sun, Aug 28, 2016 at 06:00:05PM +0200, Hans de Goede wrote:
> > From: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
> >
> > This adds a driver for the Elan eKTF2127 touchscreen controller,
> > which speaks an i2c protocol which is distinctly different from
> > the already supported eKTH controllers.
> >
> > Signed-off-by: Michel Verlaan <michel.verl@gmail.com>
> > Signed-off-by: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > ---
> > Changes in v2:
> > -Improve devicetree bindings document
> > -Use touchscreen_parse_properties and touchscreen_report_pos instead of DIY
> > -Remove a bunch of unused defines (copy and paste leftover from chipone driver)
> > -Some other minor cleanups and review comments addressed
> > -Add defines for some command / address hex-values
> > -Check packet header in interrupt handler
> > ---
> > .../bindings/input/touchscreen/ektf2127.txt | 27 ++
>
> Acked-by: Rob Herring <robh@kernel.org>
I'd like to merge the version below (factored out querying dimensions
and parsing/reporting touch), can you please give it a spin?
Thanks!
--
Dmitry
Input: touchscreen - add support for Elan eKTF2127 touchscreen controller
From: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
This adds a driver for the Elan eKTF2127 touchscreen controller,
which speaks an i2c protocol which is distinctly different from
the already supported eKTH controllers.
Signed-off-by: Michel Verlaan <michel.verl@gmail.com>
Signed-off-by: Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
---
.../bindings/input/touchscreen/ektf2127.txt | 27 ++
drivers/input/touchscreen/Kconfig | 12 +
drivers/input/touchscreen/Makefile | 1
drivers/input/touchscreen/ektf2127.c | 336 ++++++++++++++++++++
4 files changed, 376 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt
create mode 100644 drivers/input/touchscreen/ektf2127.c
diff --git a/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt b/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt
new file mode 100644
index 0000000..5a19f4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/ektf2127.txt
@@ -0,0 +1,27 @@
+* Elan eKTF2127 I2C touchscreen controller
+
+Required properties:
+ - compatible : "elan,ektf2127"
+ - reg : I2C slave address of the chip (0x40)
+ - interrupt-parent : a phandle pointing to the interrupt controller
+ serving the interrupt for this chip
+ - interrupts : interrupt specification for the ektf2127 interrupt
+ - power-gpios : GPIO specification for the pin connected to the
+ ektf2127's wake input. This needs to be driven high
+ to take ektf2127 out of it's low power state
+
+For additional optional properties see: touchscreen.txt
+
+Example:
+
+i2c at 00000000 {
+ ektf2127: touchscreen at 15 {
+ compatible = "elan,ektf2127";
+ reg = <0x15>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>
+ power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ };
+};
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 3b3d07a..880aa50 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -396,6 +396,18 @@ config TOUCHSCREEN_ELAN
To compile this driver as a module, choose M here: the
module will be called elants_i2c.
+config TOUCHSCREEN_EKTF2127
+ tristate "Elan eKTF2127 I2C touchscreen"
+ depends on I2C
+ help
+ Say Y here if you have an Elan eKTF2127 touchscreen
+ connected to your system.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ektf2127.
+
config TOUCHSCREEN_ELO
tristate "Elo serial touchscreens"
select SERIO
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 57a1c09..e26ff38 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o
obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o
obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
obj-$(CONFIG_TOUCHSCREEN_ELAN) += elants_i2c.o
+obj-$(CONFIG_TOUCHSCREEN_EKTF2127) += ektf2127.o
obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o
obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
obj-$(CONFIG_TOUCHSCREEN_EGALAX_SERIAL) += egalax_ts_serial.o
diff --git a/drivers/input/touchscreen/ektf2127.c b/drivers/input/touchscreen/ektf2127.c
new file mode 100644
index 0000000..31a2dd7
--- /dev/null
+++ b/drivers/input/touchscreen/ektf2127.c
@@ -0,0 +1,336 @@
+/*
+ * Driver for ELAN eKTF2127 i2c touchscreen controller
+ *
+ * For this driver the layout of the Chipone icn8318 i2c
+ * touchscreencontroller is used.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Author:
+ * Michel Verlaan <michel.verl@gmail.com>
+ * Siebren Vroegindeweij <siebren.vroegindeweij@hotmail.com>
+ *
+ * Original chipone_icn8318 driver:
+ * Hans de Goede <hdegoede@redhat.com>
+ */
+
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/input/mt.h>
+#include <linux/input/touchscreen.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+
+/* Packet header defines (first byte of data send / received) */
+#define EKTF2127_NOISE 0x40
+#define EKTF2127_RESPONSE 0x52
+#define EKTF2127_REQUEST 0x53
+#define EKTF2127_HELLO 0x55
+#define EKTF2127_REPORT 0x5d
+#define EKTF2127_CALIB_DONE 0x66
+
+/* Register defines (second byte of data send / received) */
+#define EKTF2127_ENV_NOISY 0x41
+#define EKTF2127_HEIGHT 0x60
+#define EKTF2127_WIDTH 0x63
+
+/* 2 bytes header + 5 * 3 bytes coordinates + 3 bytes pressure info + footer */
+#define EKTF2127_TOUCH_REPORT_SIZE 21
+#define EKTF2127_MAX_TOUCHES 5
+
+struct ektf2127_ts {
+ struct i2c_client *client;
+ struct input_dev *input;
+ struct gpio_desc *power_gpios;
+ struct touchscreen_properties prop;
+};
+
+static void ektf2127_parse_coordinates(const u8* buf, unsigned int touch_count,
+ struct input_mt_pos *touches)
+{
+ int index = 0;
+ int i;
+
+ for (i = 0; i < touch_count; i++) {
+ index = 2 + i * 3;
+
+ touches[i].x = (buf[index] & 0x0f);
+ touches[i].x <<= 8;
+ touches[i].x |= buf[index + 2];
+
+ touches[i].y = (buf[index] & 0xf0);
+ touches[i].y <<= 4;
+ touches[i].y |= buf[index + 1];
+ }
+}
+
+static void ektf2127_report_event(struct ektf2127_ts *ts, const u8 *buf)
+{
+ struct input_mt_pos touches[EKTF2127_MAX_TOUCHES];
+ int slots[EKTF2127_MAX_TOUCHES];
+ unsigned int touch_count, i;
+
+ touch_count = buf[1] & 0x07;
+ if (touch_count > EKTF2127_MAX_TOUCHES) {
+ dev_err(&ts->client->dev,
+ "Too many touches %d > %d\n",
+ touch_count, EKTF2127_MAX_TOUCHES);
+ touch_count = EKTF2127_MAX_TOUCHES;
+ }
+
+ ektf2127_parse_coordinates(buf, touch_count, touches);
+ input_mt_assign_slots(ts->input, slots, touches,
+ touch_count, 0);
+
+ for (i = 0; i < touch_count; i++) {
+ input_mt_slot(ts->input, slots[i]);
+ input_mt_report_slot_state(ts->input, MT_TOOL_FINGER, true);
+ touchscreen_report_pos(ts->input, &ts->prop,
+ touches[i].x, touches[i].y, true);
+ }
+
+ input_mt_sync_frame(ts->input);
+ input_sync(ts->input);
+}
+
+static irqreturn_t ektf2127_irq(int irq, void *dev_id)
+{
+ struct ektf2127_ts *ts = dev_id;
+ struct device *dev = &ts->client->dev;
+ char buf[EKTF2127_TOUCH_REPORT_SIZE];
+ int ret;
+
+ ret = i2c_master_recv(ts->client, buf, EKTF2127_TOUCH_REPORT_SIZE);
+ if (ret != EKTF2127_TOUCH_REPORT_SIZE) {
+ dev_err(dev, "Error reading touch data: %d\n", ret);
+ goto out;
+ }
+
+ switch (buf[0]) {
+ case EKTF2127_REPORT:
+ ektf2127_report_event(ts, buf);
+ break;
+
+ case EKTF2127_NOISE:
+ if (buf[1] == EKTF2127_ENV_NOISY)
+ dev_dbg(dev, "Environment is electrically noisy\n");
+ break;
+
+ case EKTF2127_HELLO:
+ case EKTF2127_CALIB_DONE:
+ break;
+
+ default:
+ dev_err(dev, "Unexpected packet header byte %#02x\n", buf[0]);
+ break;
+ }
+
+out:
+ return IRQ_HANDLED;
+}
+
+static int ektf2127_start(struct input_dev *dev)
+{
+ struct ektf2127_ts *ts = input_get_drvdata(dev);
+
+ enable_irq(ts->client->irq);
+ gpiod_set_value_cansleep(ts->power_gpios, 1);
+
+ return 0;
+}
+
+static void ektf2127_stop(struct input_dev *dev)
+{
+ struct ektf2127_ts *ts = input_get_drvdata(dev);
+
+ disable_irq(ts->client->irq);
+ gpiod_set_value_cansleep(ts->power_gpios, 0);
+}
+
+static int ektf2127_suspend(struct device *dev)
+{
+ struct ektf2127_ts *ts = i2c_get_clientdata(to_i2c_client(dev));
+
+ mutex_lock(&ts->input->mutex);
+ if (ts->input->users)
+ ektf2127_stop(ts->input);
+ mutex_unlock(&ts->input->mutex);
+
+ return 0;
+}
+
+static int ektf2127_resume(struct device *dev)
+{
+ struct ektf2127_ts *ts = i2c_get_clientdata(to_i2c_client(dev));
+
+ mutex_lock(&ts->input->mutex);
+ if (ts->input->users)
+ ektf2127_start(ts->input);
+ mutex_unlock(&ts->input->mutex);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(ektf2127_pm_ops, ektf2127_suspend,
+ ektf2127_resume);
+
+static int ektf2127_query_dimension(struct i2c_client *client, bool width)
+{
+ struct device *dev = &client->dev;
+ const char *what = width ? "width" : "height";
+ u8 what_code = width ? EKTF2127_WIDTH : EKTF2127_HEIGHT;
+ u8 buf[4];
+ int ret;
+ int error;
+
+ /* Request dimension */
+ buf[0] = EKTF2127_REQUEST;
+ buf[1] = width ? EKTF2127_WIDTH : EKTF2127_HEIGHT;
+ buf[2] = 0x00;
+ buf[3] = 0x00;
+ ret = i2c_master_send(client, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ error = ret < 0 ? ret : -EIO;
+ dev_err(dev, "Failed to request %s: %d\n", what, error);
+ return error;
+ }
+
+ msleep(20);
+
+ /* Read response */
+ ret = i2c_master_recv(client, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ error = ret < 0 ? ret : -EIO;
+ dev_err(dev, "Failed to receive %s data: %d\n", what, error);
+ return error;
+ }
+
+ if (buf[0] != EKTF2127_RESPONSE || buf[1] != what_code) {
+ dev_err(dev, "Unexpected %s data: %#02x %#02x\n",
+ what, buf[0], buf[1]);
+ return -EIO;
+ }
+
+ return (((buf[3] & 0xf0) << 4) | buf[2]) - 1;
+}
+
+static int ektf2127_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct ektf2127_ts *ts;
+ struct input_dev *input;
+ u8 buf[4];
+ int max_x, max_y;
+ int error;
+
+ if (!client->irq) {
+ dev_err(dev, "Error no irq specified\n");
+ return -EINVAL;
+ }
+
+ ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
+ if (!ts)
+ return -ENOMEM;
+
+ /* This requests the gpio *and* turns on the touchscreen controller */
+ ts->power_gpios = devm_gpiod_get(dev, "power", GPIOD_OUT_HIGH);
+ if (IS_ERR(ts->power_gpios)) {
+ error = PTR_ERR(ts->power_gpios);
+ if (error != -EPROBE_DEFER)
+ dev_err(dev, "Error getting power gpio: %d\n", error);
+ return error;
+ }
+
+ input = devm_input_allocate_device(dev);
+ if (!input)
+ return -ENOMEM;
+
+ input->name = client->name;
+ input->id.bustype = BUS_I2C;
+ input->open = ektf2127_start;
+ input->close = ektf2127_stop;
+
+ ts->client = client;
+
+ /* Read hello (ignore result, depends on initial power state) */
+ msleep(20);
+ i2c_master_recv(ts->client, buf, sizeof(buf));
+
+ /* Read resolution from chip */
+ max_x = ektf2127_query_dimension(client, true);
+ if (max_x < 0)
+ return max_x;
+
+ max_y = ektf2127_query_dimension(client, false);
+ if (max_y < 0)
+ return max_y;
+
+ input_set_abs_params(input, ABS_MT_POSITION_X, 0, max_x, 0, 0);
+ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, max_y, 0, 0);
+ touchscreen_parse_properties(input, true, &ts->prop);
+
+ error = input_mt_init_slots(input, EKTF2127_MAX_TOUCHES,
+ INPUT_MT_DIRECT |
+ INPUT_MT_DROP_UNUSED |
+ INPUT_MT_TRACK);
+ if (error)
+ return error;
+
+ ts->input = input;
+ input_set_drvdata(input, ts);
+
+ error = devm_request_threaded_irq(dev, client->irq,
+ NULL, ektf2127_irq,
+ IRQF_ONESHOT, client->name, ts);
+ if (error) {
+ dev_err(dev, "Error requesting irq: %d\n", error);
+ return error;
+ }
+
+ /* Stop device till opened */
+ ektf2127_stop(ts->input);
+
+ error = input_register_device(input);
+ if (error)
+ return error;
+
+ i2c_set_clientdata(client, ts);
+
+ return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id ektf2127_of_match[] = {
+ { .compatible = "elan,ektf2127" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ektf2127_of_match);
+#endif
+
+static const struct i2c_device_id ektf2127_i2c_id[] = {
+ { "ektf2127", 0 },
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, ektf2127_i2c_id);
+
+static struct i2c_driver ektf2127_driver = {
+ .driver = {
+ .name = "elan_ektf2127",
+ .pm = &ektf2127_pm_ops,
+ .of_match_table = of_match_ptr(ektf2127_of_match),
+ },
+ .probe = ektf2127_probe,
+ .id_table = ektf2127_i2c_id,
+};
+module_i2c_driver(ektf2127_driver);
+
+MODULE_DESCRIPTION("ELAN eKTF2127 I2C Touchscreen Driver");
+MODULE_AUTHOR("Michel Verlaan, Siebren Vroegindeweij");
+MODULE_LICENSE("GPL");
^ permalink raw reply related
* [PATCH] ARM: dts: msm8974: Add definitions for QCE & cryptobam
From: Andy Gross @ 2016-09-16 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916173800.r264xg5wqmer77wr@localhost>
On Fri, Sep 16, 2016 at 08:38:01PM +0300, Iaroslav Gridin wrote:
> On Thu, Sep 15, 2016 at 04:18:42PM -0500, Andy Gross wrote:
>
> > Actually, on thinking about this more, the bam block itself only requires the
> > single clock. The peripheral it is attached to has to keep its sanity during
> > the duration of the transfer (crypto). The crypto requires 3 clocks, one of
> > which is the same clk the bam requires.
> >
> > You can access the BAM registers with the bam_clk only, correct?
>
> Not preparing bam_clk degrades QCE performance about 3x, though.
If the CE2_CLK is the only required clk, that makes it the "bam_clk". I see the
crypto requires getting all three clocks: AXI (bus), AHB (iface), and CE2 (core)
If the crypto is active during DMA transfers, which it has to be, then the
performance shouldn't degrade due to the BAM not preparing the AHB.
Regards,
Andy
^ permalink raw reply
* [PATCH v6 2/3] ARM: dts: add TOPEET itop elite based board
From: Javier Martinez Canillas @ 2016-09-16 18:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160916172110.GA7511@kozik-lap>
Hello Randy,
On 09/16/2016 01:21 PM, Krzysztof Kozlowski wrote:
[snip]
>>>> +
>>>> + beep {
>>>> + compatible = "pwm-beeper";
>>>> + pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
>>> I have serious doubts that you run this code... if it does not even
>>> compile. Sorry, I cannot accept code that does not compile and was not
>>> tested.
>>>
>>> Please, test your DTS on top of current Linux tree, which would be one of:
>>> 1. Linus' master branch: v4.8-rc6,
>>> 2. one of my branches (for-next, next/dt etc),
>> When I sent those patches, I tested in "Add linux-next specific files for
>> 20160907"
>
> OK, good, but please tell me why kbuild reported that build error?
>
I agree with Krzysztof, it doesn't seem that you tested the exact version
that was posted. You will need the following change to make the DTS build
in latest linux-next:
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index dd83689892ff..8559f891a740 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -14,6 +14,7 @@
*/
/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos4412-itop-scp-core.dtsi"
So please squash that change and resend.
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply related
* [PATCH v9 08/10] arm64: pmu: Detect and enable multiple PMUs in an ACPI system
From: Jeremy Linton @ 2016-09-16 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87bmznu61q.fsf@e105922-lin.cambridge.arm.com>
On 09/16/2016 12:07 PM, Punit Agrawal wrote:
> Jeremy Linton <jeremy.linton@arm.com> writes:
>
>> Hi,
>>
>> On 09/16/2016 08:33 AM, Punit Agrawal wrote:
>>> Jeremy Linton <jeremy.linton@arm.com> writes:
>>>
>>>> Its possible that an ACPI system has multiple CPU types in it
>>>> with differing PMU counters. Iterate the CPU's and make a determination
>>>> about how many of each type exist in the system. Then take and create
>>>> a PMU platform device for each type, and assign it the interrupts parsed
>>>> from the MADT. Creating a platform device is necessary because the PMUs
>>>> are not described as devices in the DSDT table.
>>>>
>>>> This code is loosely based on earlier work by Mark Salter.
>>
>> (trimming)
>>
>>>> +
>>>> + list_for_each_entry_safe(pmu, safe_temp, &pmus, list) {
>>>> + if (unused_madt_entries)
>>>> + pmu->cpu_count = num_possible_cpus();
>>>
>>> So if there is any unbooted cpu ...
>>>
>>>> +
>>>> + res = kcalloc(pmu->cpu_count,
>>>> + sizeof(struct resource), GFP_KERNEL);
>>>
>>> ... we allocate potentially large number (num_possible_cpus()) of
>>> resources for each PMU.
>>>
>>> This is needlessly wasteful. Under what conditions have you found
>>> reg_midr to be 0?
>>
>> Unused MADT entries, in place for potentially unbooted/hotplug
>> CPUs.
>
> Is linux able to deal with booting secondaries that have unused MADT
> entries?
Uh, yah I think so, that is how i've been testing it, maybe we are
saying different things. When i'm talking about "unused" I mean MADT
entries that don't have started/running cpus. Obviously they stop being
unused when a cpu is booted.
>
>> In those cases you don't know for sure which PMU the CPU belongs
>> to until it comes online and the MIDR can be read. I'm open to
>> suggestions on how to deal with this, outside of pushing my luck and
>> further breaking the platform device encapsulation by trying to
>> reallocate the resource structure while its active. Besides its only
>> wasteful for ACPI+big.little, which at the moment only applies to a
>> development platform.
>
> I don't have any ideas to solve this problem, but in the interest of
> helping review, please move all the changes arising from hotplug/unused
> MADT entries in this patch to the next one.
Which is sort of the opposite of the last 3 months, of complaints about
how hard it was to review this module with multiple patches adding
features to the code...
^ permalink raw reply
* [PATCH 2/2] dts: arm64: db820c: add pmic pins specific dts file
From: Srinivas Kandagatla @ 2016-09-16 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474047681-6821-1-git-send-email-srinivas.kandagatla@linaro.org>
This patch adds pmic specific dts which are configured specially
for db820c. One of such pin is GPIO_F on the Low Speed expansion
which has default output voltage of 2.7v. This patch fixes setup
for that pin to have an output voltage of 1.8v to comply with
96boards LS expansion specs.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 ++
2 files changed, 17 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
new file mode 100644
index 0000000..0938191
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
@@ -0,0 +1,15 @@
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+&pm8994_gpios {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ls_exp_gpio_f>;
+
+ ls_exp_gpio_f: pm8916_mpp4 {
+ pinconf {
+ pins = "gpio5";
+ output-low;
+ power-source = <PM8994_GPIO_S4>; // 1.8V
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index afb218c..422959b 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -12,7 +12,9 @@
*/
#include "msm8996.dtsi"
+#include "pm8994.dtsi"
#include "apq8096-db820c-pins.dtsi"
+#include "apq8096-db820c-pmic-pins.dtsi"
/ {
aliases {
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] pinctrl: pm8994: add pad voltage regulator defines
From: Srinivas Kandagatla @ 2016-09-16 17:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1474047681-6821-1-git-send-email-srinivas.kandagatla@linaro.org>
This patch adds defines for internal voltage regulators used
to switch voltage levels on gpio/mpp pads.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 4 ++++
include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
index aafa76c..d33f17c 100644
--- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
+++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h
@@ -89,6 +89,10 @@
#define PMA8084_GPIO_S4 2
#define PMA8084_GPIO_L6 3
+#define PM8994_GPIO_VPH 0
+#define PM8994_GPIO_S4 2
+#define PM8994_GPIO_L12 3
+
/* To be used with "function" */
#define PMIC_GPIO_FUNC_NORMAL "normal"
#define PMIC_GPIO_FUNC_PAIRED "paired"
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
index a15c170..2e360d8f 100644
--- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -65,6 +65,12 @@
#define PMA8084_MPP_S4 2
#define PMA8084_MPP_L6 3
+#define PM8994_MPP_VPH 0
+/* Only supported for MPP_05-MPP_08 */
+#define PM8994_MPP_L19 1
+#define PM8994_MPP_S4 2
+#define PM8994_MPP_L12 3
+
/*
* Analog Input - Set the source for analog input.
* To be used with "qcom,amux-route" property
--
2.7.4
^ permalink raw reply related
* [PATCH 0/2] dts: arm64: db820c: adds support to pmic pins
From: Srinivas Kandagatla @ 2016-09-16 17:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi Andy/Linus W,
This patchset adds support to pm8994 gpios/mpps on db820c board.
DB820c board Low Speed expansion GPIO_F is connected to PM8994_GPIO5
Its better if we take this patchset from single tree, as dts patch has
dependency on the dt-bindings include file.
Without this patchset GPIO_F on LS expansion would be at 2.7v
instead of 1.8v.
Thanks,
srini
Srinivas Kandagatla (2):
pinctrl: pm8994: add pad voltage regulator defines
dts: arm64: db820c: add pmic pins specific dts file
arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 ++
include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 4 ++++
include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 6 ++++++
4 files changed, 27 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi
--
2.7.4
^ permalink raw reply
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