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* [PATCH V3 0/8] IOMMU probe deferral support
From: Sricharan @ 2016-10-12  6:24 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <12cfb59f-f7ca-d4df-eb7f-42348e357979@samsung.com>

Hi Marek,

>Hi Sricharan,
>
>
>On 2016-10-04 19:03, Sricharan R wrote:
>> Initial post from Laurent Pinchart[1]. This is
>> series calls the dma ops configuration for the devices
>> at a generic place so that it works for all busses.
>> The dma_configure_ops for a device is now called during
>> the device_attach callback just before the probe of the
>> bus/driver is called. Similarly dma_deconfigure is called during
>> device/driver_detach path.
>>
>>
>> pci_bus_add_devices    (platform/amba)(_device_create/driver_register)
>>         |                         |
>> pci_bus_add_device     (device_add/driver_register)
>>         |                         |
>> device_attach           device_initial_probe
>>         |                         |
>> __device_attach_driver    __device_attach_driver
>>         |
>> driver_probe_device
>>         |
>> really_probe
>>         |
>> dma_configure
>>
>>   Similarly on the device/driver_unregister path __device_release_driver is
>>   called which inturn calls dma_deconfigure.
>>
>>   If the ACPI bus code follows the same, we can add acpi_dma_configure
>>   at the same place as of_dma_configure.
>>
>>   This series is based on the recently merged Generic DT bindings for
>>   PCI IOMMUs and ARM SMMU from Robin Murphy robin.murphy at arm.com [2]
>>
>>   This time tested this with platform and pci device for probe deferral
>>   and reprobe on arm64 based platform. There is an issue on the cleanup
>>   path for arm64 though, where there is WARN_ON if the dma_ops is reset while
>>   device is attached to an domain in arch_teardown_dma_ops.
>>   But with iommu_groups created from the iommu driver, the device is always
>>   attached to a domain/default_domain. So so the WARN has to be removed/handled
>>   probably.
>
>Thanks for continuing work on this feature! Your can add my:
>
>Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
>
  Thanks for testing this. So the for the below fix, the remove_device callback
  gets called on the dma_ops cleanup path, so would it be easy to remove the
  data for the device there ?

Regards,
 Sricharan


>It works fine with Exynos SYSMMU driver, although a patch is needed to fix
>infinite loop due to list corruption (same element is added twice if master
>device fails with deferred probe):
>
>From: Marek Szyprowski <m.szyprowski@samsung.com>
>Date: Mon, 10 Oct 2016 14:22:42 +0200
>Subject: [PATCH] iommu/exynos: ensure that sysmmu is added only once to its
>  master
>
>Since adding IOMMU deferred probing support, of_xlate() callback might
>be called more than once for given master device (for example it happens
>when masters device driver fails with EPROBE_DEFER), so ensure that
>SYSMMU controller is added to its master device (owner) only once.
>
>Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>---
>  drivers/iommu/exynos-iommu.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
>index 30808e91b775..1525a86eb829 100644
>--- a/drivers/iommu/exynos-iommu.c
>+++ b/drivers/iommu/exynos-iommu.c
>@@ -1253,7 +1253,7 @@ static int exynos_iommu_of_xlate(struct device *dev,
>  {
>      struct exynos_iommu_owner *owner = dev->archdata.iommu;
>      struct platform_device *sysmmu = of_find_device_by_node(spec->np);
>-    struct sysmmu_drvdata *data;
>+    struct sysmmu_drvdata *data, *entry;
>
>      if (!sysmmu)
>          return -ENODEV;
>@@ -1271,6 +1271,10 @@ static int exynos_iommu_of_xlate(struct device *dev,
>          dev->archdata.iommu = owner;
>      }
>
>+    list_for_each_entry(entry, &owner->controllers, owner_node)
>+        if (entry == data)
>+            return 0;
>+
>      list_add_tail(&data->owner_node, &owner->controllers);
>      return 0;
>  }
>--
>1.9.1
>

^ permalink raw reply

* [patch] serial: stm32: fix a type issue
From: Dan Carpenter @ 2016-10-12  6:21 UTC (permalink / raw)
  To: linux-arm-kernel

We store UNDEF_REG in a u8.  It causes a problem in functions like
stm32_tx_dma_complete() where we check "if (ofs->icr == UNDEF_REG)".

Fixes: 3489187204eb ('serial: stm32: adding dma support')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>

diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index 41d9749..f9887cc 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -31,7 +31,7 @@ struct stm32_usart_info {
 	struct stm32_usart_config cfg;
 };
 
-#define UNDEF_REG ~0
+#define UNDEF_REG 0xFF
 
 /* Register offsets */
 struct stm32_usart_info stm32f4_info = {

^ permalink raw reply related

* [PATCH 4/4] selftests: arm64: add test for unaligned watchpoint address handling
From: Pratyush Anand @ 2016-10-12  5:58 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1476251587.git.panand@redhat.com>

ARM64 hardware expects 64bit aligned address for watchpoint invocation.
However, it provides byte selection method to select any number of
consecutive byte set within the range of 1-8.

This patch adds support to test all such byte selection option for
different memory write sizes.

Signed-off-by: Pratyush Anand <panand@redhat.com>
---
 tools/testing/selftests/breakpoints/Makefile       |   5 +-
 .../selftests/breakpoints/breakpoint_test_arm64.c  | 223 +++++++++++++++++++++
 2 files changed, 227 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

diff --git a/tools/testing/selftests/breakpoints/Makefile b/tools/testing/selftests/breakpoints/Makefile
index 74e533fd4bc5..61b79e8df1f4 100644
--- a/tools/testing/selftests/breakpoints/Makefile
+++ b/tools/testing/selftests/breakpoints/Makefile
@@ -5,6 +5,9 @@ ARCH ?= $(shell echo $(uname_M) | sed -e s/i.86/x86/ -e s/x86_64/x86/)
 ifeq ($(ARCH),x86)
 TEST_PROGS := breakpoint_test
 endif
+ifeq ($(ARCH),aarch64)
+TEST_PROGS := breakpoint_test_arm64
+endif
 
 TEST_PROGS += step_after_suspend_test
 
@@ -13,4 +16,4 @@ all: $(TEST_PROGS)
 include ../lib.mk
 
 clean:
-	rm -fr breakpoint_test step_after_suspend_test
+	rm -fr breakpoint_test breakpoint_test_arm64 step_after_suspend_test
diff --git a/tools/testing/selftests/breakpoints/breakpoint_test_arm64.c b/tools/testing/selftests/breakpoints/breakpoint_test_arm64.c
new file mode 100644
index 000000000000..f56331831182
--- /dev/null
+++ b/tools/testing/selftests/breakpoints/breakpoint_test_arm64.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Original Code by Pavel Labath <test.tberghammer@gmail.com>
+ *
+ * Code modified by Pratyush Anand <panand@redhat.com>
+ * for testing different byte select for each access size.
+ *
+ */
+
+#define _GNU_SOURCE
+
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <sys/ptrace.h>
+#include <sys/param.h>
+#include <sys/uio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <elf.h>
+#include <errno.h>
+#include <signal.h>
+
+#include "../kselftest.h"
+
+static volatile uint8_t var[96] __attribute__((__aligned__(32)));
+
+static void child(int size, int wr)
+{
+	volatile uint8_t *addr = &var[32 + wr];
+
+	if (ptrace(PTRACE_TRACEME, 0, NULL, NULL) != 0) {
+		perror("ptrace(PTRACE_TRACEME) failed");
+		_exit(1);
+	}
+
+	if (raise(SIGSTOP) != 0) {
+		perror("raise(SIGSTOP) failed");
+		_exit(1);
+	}
+
+	if ((uintptr_t) addr % size) {
+		perror("Wrong address write for the given size\n");
+		_exit(1);
+	}
+	switch (size) {
+	case 1:
+		*addr = 47;
+		break;
+	case 2:
+		*(uint16_t *)addr = 47;
+		break;
+	case 4:
+		*(uint32_t *)addr = 47;
+		break;
+	case 8:
+		*(uint64_t *)addr = 47;
+		break;
+	case 16:
+		__asm__ volatile ("stp x29, x30, %0" : "=m" (addr[0]));
+		break;
+	case 32:
+		__asm__ volatile ("stp q29, q30, %0" : "=m" (addr[0]));
+		break;
+	}
+
+	_exit(0);
+}
+
+static bool set_watchpoint(pid_t pid, int size, int wp)
+{
+	const volatile uint8_t *addr = &var[32 + wp];
+	const int offset = (uintptr_t)addr % 8;
+	const unsigned int byte_mask = ((1 << size) - 1) << offset;
+	const unsigned int type = 2; /* Write */
+	const unsigned int enable = 1;
+	const unsigned int control = byte_mask << 5 | type << 3 | enable;
+	struct user_hwdebug_state dreg_state;
+	struct iovec iov;
+
+	memset(&dreg_state, 0, sizeof(dreg_state));
+	dreg_state.dbg_regs[0].addr = (uintptr_t)(addr - offset);
+	dreg_state.dbg_regs[0].ctrl = control;
+	iov.iov_base = &dreg_state;
+	iov.iov_len = offsetof(struct user_hwdebug_state, dbg_regs) +
+				sizeof(dreg_state.dbg_regs[0]);
+	if (ptrace(PTRACE_SETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0)
+		return true;
+
+	if (errno == EIO) {
+		printf("ptrace(PTRACE_SETREGSET, NT_ARM_HW_WATCH) "
+			"not supported on this hardware\n");
+		ksft_exit_skip();
+	}
+	perror("ptrace(PTRACE_SETREGSET, NT_ARM_HW_WATCH) failed");
+	return false;
+}
+
+static bool run_test(int size, int wr, int wp)
+{
+	int status;
+	siginfo_t siginfo;
+	pid_t pid = fork();
+	pid_t wpid;
+
+	if (pid < 0) {
+		perror("fork() failed");
+		return false;
+	}
+	if (pid == 0)
+		child(size, wr);
+
+	wpid = waitpid(pid, &status, __WALL);
+	if (wpid != pid) {
+		perror("waitpid() failed");
+		return false;
+	}
+	if (!WIFSTOPPED(status)) {
+		printf("child did not stop\n");
+		return false;
+	}
+	if (WSTOPSIG(status) != SIGSTOP) {
+		printf("child did not stop with SIGSTOP\n");
+		return false;
+	}
+
+	if (!set_watchpoint(pid, MIN(size, 8), wp))
+		return false;
+
+	if (ptrace(PTRACE_CONT, pid, NULL, NULL) < 0) {
+		perror("ptrace(PTRACE_SINGLESTEP) failed");
+		return false;
+	}
+
+	alarm(3);
+	wpid = waitpid(pid, &status, __WALL);
+	if (wpid != pid) {
+		perror("waitpid() failed");
+		return false;
+	}
+	alarm(0);
+	if (WIFEXITED(status)) {
+		printf("child did not single-step\t");
+		return false;
+	}
+	if (!WIFSTOPPED(status)) {
+		printf("child did not stop\n");
+		return false;
+	}
+	if (WSTOPSIG(status) != SIGTRAP) {
+		printf("child did not stop with SIGTRAP\n");
+		return false;
+	}
+	if (ptrace(PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) {
+		perror("ptrace(PTRACE_GETSIGINFO)");
+		return false;
+	}
+	if (siginfo.si_code != TRAP_HWBKPT) {
+		printf("Unexpected si_code %d\n", siginfo.si_code);
+		return false;
+	}
+
+	kill(pid, SIGKILL);
+	wpid = waitpid(pid, &status, 0);
+	if (wpid != pid) {
+		perror("waitpid() failed");
+		return false;
+	}
+	return true;
+}
+
+static void sigalrm(int sig)
+{
+}
+
+int main(int argc, char **argv)
+{
+	int opt;
+	bool succeeded = true;
+	struct sigaction act;
+	int wr, wp, size;
+	bool result;
+
+	act.sa_handler = sigalrm;
+	sigemptyset(&act.sa_mask);
+	act.sa_flags = 0;
+	sigaction(SIGALRM, &act, NULL);
+	for (size = 1; size <= 32; size = size*2) {
+		for (wr = 0; wr <= 32; wr = wr + size) {
+			for (wp = wr - size; wp <= wr + size; wp = wp + size) {
+				printf("Test size = %d write offset = %d watchpoint offset = %d\t", size, wr, wp);
+				result = run_test(size, wr, wp);
+				if ((result && wr == wp) || (!result && wr != wp)) {
+					printf("[OK]\n");
+					ksft_inc_pass_cnt();
+				} else {
+					printf("[FAILED]\n");
+					ksft_inc_fail_cnt();
+					succeeded = false;
+				}
+			}
+		}
+	}
+
+	ksft_print_cnts();
+	if (succeeded)
+		ksft_exit_pass();
+	else
+		ksft_exit_fail();
+}
-- 
2.7.4

^ permalink raw reply related

* [PATCH 3/4] arm64: Allow hw watchpoint of length 3,5,6 and 7
From: Pratyush Anand @ 2016-10-12  5:58 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1476251587.git.panand@redhat.com>

Since, arm64 can support all offset within a double word limit. Therefore,
now support other lengths within that range as well.

Signed-off-by: Pratyush Anand <panand@redhat.com>
---
 arch/arm64/include/asm/hw_breakpoint.h |  4 ++++
 arch/arm64/kernel/hw_breakpoint.c      | 36 ++++++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index 4f4e58bee9bc..7a18c8520588 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -76,7 +76,11 @@ static inline void decode_ctrl_reg(u32 reg,
 /* Lengths */
 #define ARM_BREAKPOINT_LEN_1	0x1
 #define ARM_BREAKPOINT_LEN_2	0x3
+#define ARM_BREAKPOINT_LEN_3	0x7
 #define ARM_BREAKPOINT_LEN_4	0xf
+#define ARM_BREAKPOINT_LEN_5	0x1f
+#define ARM_BREAKPOINT_LEN_6	0x3f
+#define ARM_BREAKPOINT_LEN_7	0x7f
 #define ARM_BREAKPOINT_LEN_8	0xff
 
 /* Kernel stepping */
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index c888c23149ad..7ff2c3cfeb46 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -317,9 +317,21 @@ static int get_hbp_len(u8 hbp_len)
 	case ARM_BREAKPOINT_LEN_2:
 		len_in_bytes = 2;
 		break;
+	case ARM_BREAKPOINT_LEN_3:
+		len_in_bytes = 3;
+		break;
 	case ARM_BREAKPOINT_LEN_4:
 		len_in_bytes = 4;
 		break;
+	case ARM_BREAKPOINT_LEN_5:
+		len_in_bytes = 5;
+		break;
+	case ARM_BREAKPOINT_LEN_6:
+		len_in_bytes = 6;
+		break;
+	case ARM_BREAKPOINT_LEN_7:
+		len_in_bytes = 7;
+		break;
 	case ARM_BREAKPOINT_LEN_8:
 		len_in_bytes = 8;
 		break;
@@ -379,9 +391,21 @@ int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 	case ARM_BREAKPOINT_LEN_2:
 		*gen_len = HW_BREAKPOINT_LEN_2;
 		break;
+	case ARM_BREAKPOINT_LEN_3:
+		*gen_len = HW_BREAKPOINT_LEN_3;
+		break;
 	case ARM_BREAKPOINT_LEN_4:
 		*gen_len = HW_BREAKPOINT_LEN_4;
 		break;
+	case ARM_BREAKPOINT_LEN_5:
+		*gen_len = HW_BREAKPOINT_LEN_5;
+		break;
+	case ARM_BREAKPOINT_LEN_6:
+		*gen_len = HW_BREAKPOINT_LEN_6;
+		break;
+	case ARM_BREAKPOINT_LEN_7:
+		*gen_len = HW_BREAKPOINT_LEN_7;
+		break;
 	case ARM_BREAKPOINT_LEN_8:
 		*gen_len = HW_BREAKPOINT_LEN_8;
 		break;
@@ -425,9 +449,21 @@ static int arch_build_bp_info(struct perf_event *bp)
 	case HW_BREAKPOINT_LEN_2:
 		info->ctrl.len = ARM_BREAKPOINT_LEN_2;
 		break;
+	case HW_BREAKPOINT_LEN_3:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_3;
+		break;
 	case HW_BREAKPOINT_LEN_4:
 		info->ctrl.len = ARM_BREAKPOINT_LEN_4;
 		break;
+	case HW_BREAKPOINT_LEN_5:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_5;
+		break;
+	case HW_BREAKPOINT_LEN_6:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_6;
+		break;
+	case HW_BREAKPOINT_LEN_7:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_7;
+		break;
 	case HW_BREAKPOINT_LEN_8:
 		info->ctrl.len = ARM_BREAKPOINT_LEN_8;
 		break;
-- 
2.7.4

^ permalink raw reply related

* [PATCH 2/4] arm64: Allow hw watchpoint at varied offset from base address
From: Pratyush Anand @ 2016-10-12  5:58 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1476251587.git.panand@redhat.com>

ARM64 hardware supports watchpoint at any double word aligned address.
However, it can select any consecutive bytes from offset 0 to 7 from that
base address. For example, if base address is programmed as 0x420030 and
byte select is 0x1C, then access of 0x420032,0x420033 and 0x420034 will
generate a watchpoint exception.

Currently, we do not have such modularity. We can only program byte,
halfword, word and double word access exception from any base address.

This patch adds support to overcome above limitations.

Signed-off-by: Pratyush Anand <panand@redhat.com>
---
 arch/arm64/include/asm/hw_breakpoint.h |  2 +-
 arch/arm64/kernel/hw_breakpoint.c      | 43 +++++++++++++++++-----------------
 arch/arm64/kernel/ptrace.c             |  5 ++--
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index 115ea2a64520..4f4e58bee9bc 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -118,7 +118,7 @@ struct perf_event;
 struct pmu;
 
 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
-				  int *gen_len, int *gen_type);
+				  int *gen_len, int *gen_type, int *offset);
 extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
 extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index 26a6bf77d272..c888c23149ad 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -349,7 +349,7 @@ int arch_check_bp_in_kernelspace(struct perf_event *bp)
  * to generic breakpoint descriptions.
  */
 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
-			   int *gen_len, int *gen_type)
+			   int *gen_len, int *gen_type, int *offset)
 {
 	/* Type */
 	switch (ctrl.type) {
@@ -369,8 +369,10 @@ int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 		return -EINVAL;
 	}
 
+	*offset = ffs(ctrl.len) - 1;
+
 	/* Len */
-	switch (ctrl.len) {
+	switch (ctrl.len >> *offset) {
 	case ARM_BREAKPOINT_LEN_1:
 		*gen_len = HW_BREAKPOINT_LEN_1;
 		break;
@@ -517,18 +519,17 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 		default:
 			return -EINVAL;
 		}
-
-		info->address &= ~alignment_mask;
-		info->ctrl.len <<= offset;
 	} else {
 		if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE)
 			alignment_mask = 0x3;
 		else
 			alignment_mask = 0x7;
-		if (info->address & alignment_mask)
-			return -EINVAL;
+		offset = info->address & alignment_mask;
 	}
 
+	info->address &= ~alignment_mask;
+	info->ctrl.len <<= offset;
+
 	/*
 	 * Disallow per-task kernel breakpoints since these would
 	 * complicate the stepping code.
@@ -671,6 +672,7 @@ static int watchpoint_handler(unsigned long addr, unsigned int esr,
 	struct debug_info *debug_info;
 	struct arch_hw_breakpoint *info;
 	struct arch_hw_breakpoint_ctrl ctrl;
+	u32 lens, lene;
 
 	slots = this_cpu_ptr(wp_on_reg);
 	debug_info = &current->thread.debug;
@@ -684,25 +686,22 @@ static int watchpoint_handler(unsigned long addr, unsigned int esr,
 			goto unlock;
 
 		info = counter_arch_bp(wp);
-		/* AArch32 watchpoints are either 4 or 8 bytes aligned. */
-		if (is_compat_task()) {
-			if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
-				alignment_mask = 0x7;
-			else
-				alignment_mask = 0x3;
-		} else {
-			alignment_mask = 0x7;
-		}
 
-		/* Check if the watchpoint value matches. */
+		/* Check if the watchpoint value and byte select match. */
 		val = read_wb_reg(AARCH64_DBG_REG_WVR, i);
-		if (val != (addr & ~alignment_mask))
-			goto unlock;
-
-		/* Possible match, check the byte address select to confirm. */
 		ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i);
 		decode_ctrl_reg(ctrl_reg, &ctrl);
-		if (!((1 << (addr & alignment_mask)) & ctrl.len))
+		lens = ffs(ctrl.len) - 1;
+		lene = fls(ctrl.len) - 1;
+		/*
+		 * Ideally, a read/write type information such as
+		 * byte/hw/word/dw would have provided a good check. But
+		 * I do not see such possibility. So, considering that max
+		 * rd/wr size as 8, i.e. this watchpoint interrupt would
+		 * have generated because any of the address from `addr` to
+		 * `addr + 7` would have been accessed.
+		 */
+		if (addr + 7 < val + lens || addr > val + lene)
 			goto unlock;
 
 		/*
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index e0c81da60f76..0eb366a94382 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -327,13 +327,13 @@ static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type,
 				     struct arch_hw_breakpoint_ctrl ctrl,
 				     struct perf_event_attr *attr)
 {
-	int err, len, type, disabled = !ctrl.enabled;
+	int err, len, type, offset, disabled = !ctrl.enabled;
 
 	attr->disabled = disabled;
 	if (disabled)
 		return 0;
 
-	err = arch_bp_generic_fields(ctrl, &len, &type);
+	err = arch_bp_generic_fields(ctrl, &len, &type, &offset);
 	if (err)
 		return err;
 
@@ -352,6 +352,7 @@ static int ptrace_hbp_fill_attr_ctrl(unsigned int note_type,
 
 	attr->bp_len	= len;
 	attr->bp_type	= type;
+	attr->bp_addr	+= offset;
 
 	return 0;
 }
-- 
2.7.4

^ permalink raw reply related

* [PATCH 1/4] hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
From: Pratyush Anand @ 2016-10-12  5:58 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1476251587.git.panand@redhat.com>

We only support breakpoint/watchpoint of length 1, 2, 4 and 8. If we can
support other length as well, then user may watch more data with less
number of watchpoints (provided hardware supports it). For example: if we
have to watch only 4th, 5th and 6th byte from a 64 bit aligned address, we
will have to use two slots to implement it currently. One slot will watch a
half word at offset 4 and other a byte at offset 6. If we can have a
watchpoint of length 3 then we can watch it with single slot as well.

ARM64 hardware does support such functionality, therefore adding these new
definitions in generic layer.

Signed-off-by: Pratyush Anand <panand@redhat.com>
---
 include/uapi/linux/hw_breakpoint.h       | 4 ++++
 tools/include/uapi/linux/hw_breakpoint.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/include/uapi/linux/hw_breakpoint.h b/include/uapi/linux/hw_breakpoint.h
index b04000a2296a..2b65efd19a46 100644
--- a/include/uapi/linux/hw_breakpoint.h
+++ b/include/uapi/linux/hw_breakpoint.h
@@ -4,7 +4,11 @@
 enum {
 	HW_BREAKPOINT_LEN_1 = 1,
 	HW_BREAKPOINT_LEN_2 = 2,
+	HW_BREAKPOINT_LEN_3 = 3,
 	HW_BREAKPOINT_LEN_4 = 4,
+	HW_BREAKPOINT_LEN_5 = 5,
+	HW_BREAKPOINT_LEN_6 = 6,
+	HW_BREAKPOINT_LEN_7 = 7,
 	HW_BREAKPOINT_LEN_8 = 8,
 };
 
diff --git a/tools/include/uapi/linux/hw_breakpoint.h b/tools/include/uapi/linux/hw_breakpoint.h
index b04000a2296a..2b65efd19a46 100644
--- a/tools/include/uapi/linux/hw_breakpoint.h
+++ b/tools/include/uapi/linux/hw_breakpoint.h
@@ -4,7 +4,11 @@
 enum {
 	HW_BREAKPOINT_LEN_1 = 1,
 	HW_BREAKPOINT_LEN_2 = 2,
+	HW_BREAKPOINT_LEN_3 = 3,
 	HW_BREAKPOINT_LEN_4 = 4,
+	HW_BREAKPOINT_LEN_5 = 5,
+	HW_BREAKPOINT_LEN_6 = 6,
+	HW_BREAKPOINT_LEN_7 = 7,
 	HW_BREAKPOINT_LEN_8 = 8,
 };
 
-- 
2.7.4

^ permalink raw reply related

* [PATCH 0/4] ARM64: More flexible HW watchpoint
From: Pratyush Anand @ 2016-10-12  5:58 UTC (permalink / raw)
  To: linux-arm-kernel

Currently, we do not support all the byte select option provided by ARM64
specs for a HW watchpoint.

This patch set will help user to instrument a watchpoint with all possible
byte select options.

Pratyush Anand (4):
  hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
  arm64: Allow hw watchpoint at varied offset from base address
  arm64: Allow hw watchpoint of length 3,5,6 and 7
  selftests: arm64: add test for unaligned watchpoint address handling

 arch/arm64/include/asm/hw_breakpoint.h             |   6 +-
 arch/arm64/kernel/hw_breakpoint.c                  |  79 ++++++--
 arch/arm64/kernel/ptrace.c                         |   5 +-
 include/uapi/linux/hw_breakpoint.h                 |   4 +
 tools/include/uapi/linux/hw_breakpoint.h           |   4 +
 tools/testing/selftests/breakpoints/Makefile       |   5 +-
 .../selftests/breakpoints/breakpoint_test_arm64.c  | 223 +++++++++++++++++++++
 7 files changed, 300 insertions(+), 26 deletions(-)
 create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_arm64.c

-- 
2.7.4

^ permalink raw reply

* [PATCH net-next 0/2] drivers: net: xgene: fix: Use GPIO to get link status
From: David Miller @ 2016-10-12  5:54 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1475789758-5196-1-git-send-email-isubramanian@apm.com>

From: Iyappan Subramanian <isubramanian@apm.com>
Date: Thu,  6 Oct 2016 14:35:56 -0700

> Since the link value reported by the link status register is not
> reliable if no SPF module inserted, this patchset fixes the issue by
> using GPIO to determine the link status when no module inserted.
> 
> Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
> Signed-off-by: Quan Nguyen <qnguyen@apm.com>

Series applied, thanks.

^ permalink raw reply

* [PATCH 2/2] arm64: dts: zx: Add clock controller nodes
From: Shawn Guo @ 2016-10-12  2:39 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1476238456-20420-2-git-send-email-jun.nie@linaro.org>

On Wed, Oct 12, 2016 at 10:14:16AM +0800, Jun Nie wrote:
> Add clock controller nodes, including one top controller
> two low speed controllers and one audio controller.
> 
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
>  arch/arm64/boot/dts/zte/zx296718.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
> index 6b239a3..33e42d5 100644
> --- a/arch/arm64/boot/dts/zte/zx296718.dtsi
> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
> @@ -279,9 +279,33 @@
>  			dma-requests = <32>;
>  		};
>  
> +		lsp0crm: clock-controller at 01420000 {

Please drop the leading zeros from unit-address in node name.

Shawn

> +			compatible = "zte,zx296718-lsp0crm";
> +			reg = <0x01420000 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		lsp1crm: clock-controller at 01430000 {
> +			compatible = "zte,zx296718-lsp1crm";
> +			reg = <0x01430000 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
> +		topcrm: clock-controller at 01461000 {
> +			compatible = "zte,zx296718-topcrm";
> +			reg = <0x01461000 0x1000>;
> +			#clock-cells = <1>;
> +		};
> +
>  		sysctrl: sysctrl at 1463000 {
>  			compatible = "zte,zx296718-sysctrl", "syscon";
>  			reg = <0x1463000 0x1000>;
>  		};
> +
> +		audiocrm: clock-controller at 01480000 {
> +			compatible = "zte,zx296718-audiocrm";
> +			reg = <0x01480000 0x1000>;
> +			#clock-cells = <1>;
> +		};
>  	};
>  };
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [PATCH 1/2] arm64: dts: zx: Change gic node to fix boot failure
From: Shawn Guo @ 2016-10-12  2:37 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1476238456-20420-1-git-send-email-jun.nie@linaro.org>

On Wed, Oct 12, 2016 at 10:14:15AM +0800, Jun Nie wrote:
> GICR for multiple CPU can be described with start address and stride,
> or with multiple address. Current multiple address and stride are
> both used. Fix it.

I think we need to tell the full story about this boot failure in commit
log, i.e. it boots fine on v4.8-rc and fails on linux-next because of
the mm/vmalloc.c changes.

Shawn

> 
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
>  arch/arm64/boot/dts/zte/zx296718.dtsi | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
> index a223066..6b239a3 100644
> --- a/arch/arm64/boot/dts/zte/zx296718.dtsi
> +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
> @@ -239,16 +239,11 @@
>  		compatible = "arm,gic-v3";
>  		#interrupt-cells = <3>;
>  		#address-cells = <0>;
> -		#redistributor-regions = <6>;
> -		redistributor-stride = <0x0 0x40000>;
> +		#redistributor-regions = <1>;
> +		redistributor-stride = <0x20000>;
>  		interrupt-controller;
>  		reg = <0x02a00000 0x10000>,
> -		      <0x02b00000 0x20000>,
> -		      <0x02b20000 0x20000>,
> -		      <0x02b40000 0x20000>,
> -		      <0x02b60000 0x20000>,
> -		      <0x02b80000 0x20000>,
> -		      <0x02ba0000 0x20000>;
> +		      <0x02b00000 0xc0000>;
>  		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>  	};
>  
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply

* [PATCH 2/2] arm64: dts: zx: Add clock controller nodes
From: Jun Nie @ 2016-10-12  2:14 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1476238456-20420-1-git-send-email-jun.nie@linaro.org>

Add clock controller nodes, including one top controller
two low speed controllers and one audio controller.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index 6b239a3..33e42d5 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -279,9 +279,33 @@
 			dma-requests = <32>;
 		};
 
+		lsp0crm: clock-controller at 01420000 {
+			compatible = "zte,zx296718-lsp0crm";
+			reg = <0x01420000 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		lsp1crm: clock-controller at 01430000 {
+			compatible = "zte,zx296718-lsp1crm";
+			reg = <0x01430000 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		topcrm: clock-controller at 01461000 {
+			compatible = "zte,zx296718-topcrm";
+			reg = <0x01461000 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		sysctrl: sysctrl at 1463000 {
 			compatible = "zte,zx296718-sysctrl", "syscon";
 			reg = <0x1463000 0x1000>;
 		};
+
+		audiocrm: clock-controller at 01480000 {
+			compatible = "zte,zx296718-audiocrm";
+			reg = <0x01480000 0x1000>;
+			#clock-cells = <1>;
+		};
 	};
 };
-- 
1.9.1

^ permalink raw reply related

* [PATCH 1/2] arm64: dts: zx: Change gic node to fix boot failure
From: Jun Nie @ 2016-10-12  2:14 UTC (permalink / raw)
  To: linux-arm-kernel

GICR for multiple CPU can be described with start address and stride,
or with multiple address. Current multiple address and stride are
both used. Fix it.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
 arch/arm64/boot/dts/zte/zx296718.dtsi | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index a223066..6b239a3 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -239,16 +239,11 @@
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
 		#address-cells = <0>;
-		#redistributor-regions = <6>;
-		redistributor-stride = <0x0 0x40000>;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x20000>;
 		interrupt-controller;
 		reg = <0x02a00000 0x10000>,
-		      <0x02b00000 0x20000>,
-		      <0x02b20000 0x20000>,
-		      <0x02b40000 0x20000>,
-		      <0x02b60000 0x20000>,
-		      <0x02b80000 0x20000>,
-		      <0x02ba0000 0x20000>;
+		      <0x02b00000 0xc0000>;
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-- 
1.9.1

^ permalink raw reply related

* [PATCH] ARM: multi_v7_defconfig: Enable Intel e1000e driver
From: Scott Branden @ 2016-10-11 22:38 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <8265935.TobkRj9BnG@wuerfel>

Hi Arnd,

On 16-10-10 12:47 AM, Arnd Bergmann wrote:
> On Saturday, October 8, 2016 1:41:04 PM CEST Scott Branden wrote:
>> Enable support for the Intel e1000e driver
>>
>> Signed-off-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
>>
>
> Can we make this a loadable module and group it with the other
> ethernet drivers?
>
We use a fixed rootfs image to test the kernel.  For simplicity we don't 
construct a rootfs or load any modules.  We just test the kernel image. 
So for us every defconfig we use needs to be set to y to use the 
upstreamed kernel.

Plus, how do you NFS mount a rootfs if the ethernet driver is a loadable 
module?
> 	Arnd
>

Regards,
  Scott

^ permalink raw reply

* [PATCH] arm64: defconfig: enable EEPROM_AT25 config option
From: Scott Branden @ 2016-10-11 22:33 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1503155.onL8VV3RJv@wuerfel>

Hi Arnd,

On 16-10-10 02:20 AM, Arnd Bergmann wrote:
> On Monday, October 10, 2016 2:08:05 AM CEST Florian Fainelli wrote:
>> On 10/07/2016 02:23 PM, Scott Branden wrote:
>>> Enable support for on board SPI EEPROM by turning on
>>> CONFIG_EEPROM_AT25.
>>>
>>> Signed-off-by: Scott Branden <scott.branden@broadcom.com>
>>
>> Looks fine to me, unless this needs to be a module, Arnd, what do you think?
>
> Please either make it a module or explain in the patch description
> why it should be built-in.

We use a fixed rootfs image to test the kernel.  For simplicity we don't 
construct a rootfs or load any modules.  We just test the kernel image. 
So for us every defconfig we use needs to be set to y to use the 
upstreamed kernel.

>
> 	Arnd
>

Regards,
  Scott

^ permalink raw reply

* [PATCH v1 1/2] include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl
From: Heiko Stuebner @ 2016-10-11 22:00 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1473210053-23743-1-git-send-email-andy.yan@rock-chips.com>

Am Mittwoch, 7. September 2016, 09:00:53 CEST schrieb Andy Yan:
> Add gpio pin index definition to make it easier to describe
> GPIO in dts.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

just as a heads up, as I didn't respond yet:

Looks good and I'll take them, I just want to wait for the merge-window to 
close (should be the coming sunday), to be able to put the header change in a 
shared branch for the case that other users appear during the 4.10 cycle.


Heiko

> ---
> 
> Changes in v1:
> - remove gpio bank definition RK_GPIO7/8
> - redefine GPIO PIN as RK_PA/B/C/Dx
> 
>  include/dt-bindings/pinctrl/rockchip.h | 33
> +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
> 
> diff --git a/include/dt-bindings/pinctrl/rockchip.h
> b/include/dt-bindings/pinctrl/rockchip.h index 743e66a..aaec8ba 100644
> --- a/include/dt-bindings/pinctrl/rockchip.h
> +++ b/include/dt-bindings/pinctrl/rockchip.h
> @@ -25,6 +25,39 @@
>  #define RK_GPIO4	4
>  #define RK_GPIO6	6
> 
> +#define RK_PA0		0
> +#define RK_PA1		1
> +#define RK_PA2		2
> +#define RK_PA3		3
> +#define RK_PA4		4
> +#define RK_PA5		5
> +#define RK_PA6		6
> +#define RK_PA7		7
> +#define RK_PB0		8
> +#define RK_PB1		9
> +#define RK_PB2		10
> +#define RK_PB3		11
> +#define RK_PB4		12
> +#define RK_PB5		13
> +#define RK_PB6		14
> +#define RK_PB7		15
> +#define RK_PC0		16
> +#define RK_PC1		17
> +#define RK_PC2		18
> +#define RK_PC3		19
> +#define RK_PC4		20
> +#define RK_PC5		21
> +#define RK_PC6		22
> +#define RK_PC7		23
> +#define RK_PD0		24
> +#define RK_PD1		25
> +#define RK_PD2		26
> +#define RK_PD3		27
> +#define RK_PD4		28
> +#define RK_PD5		29
> +#define RK_PD6		30
> +#define RK_PD7		31
> +
>  #define RK_FUNC_GPIO	0
>  #define RK_FUNC_1	1
>  #define RK_FUNC_2	2

^ permalink raw reply

* [PATCH V2 0/3] ACPI,PCI,IRQ: revert penalty calculation for SCI
From: Rafael J. Wysocki @ 2016-10-11 21:55 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1475615720-31047-1-git-send-email-okaya@codeaurora.org>

On Tuesday, October 04, 2016 05:15:16 PM Sinan Kaya wrote:
> Restoring the old behavior for IRQ < 256 and the dynamic penalty behavior
> will remain effective for IRQ >= 256.
> 
> By the time ACPI gets initialized, this code tries to determine an
> IRQ number based on penalty values in this array. It will try to locate
> the IRQ with the least penalty assignment so that interrupt sharing is
> avoided if possible.
> 
> A couple of notes about the external APIs:
> 1. These API can be called before the ACPI is started. Therefore, one
> cannot assume that the PCI link objects are initialized for calculating
> penalties.
> 2. The polarity and trigger information passed via the
> acpi_penalize_sci_irq from the BIOS may not match what the IRQ subsystem
> is reporting as the call might have been placed before the IRQ is
> registered by the interrupt subsystem.
> 
> The reverted changes were in the direction to remove these external API and
> try to calculate the penalties at runtime for the ISA, SCI as well as PCI
> IRQS. This didn't work out well with the existing platforms.
> 
> Changes from V1 (https://lkml.org/lkml/2016/10/1/106):
> * Commit message updates
> 
> Sinan Kaya (3):
>   Revert "ACPI,PCI,IRQ: reduce static IRQ array size to 16"
>   ACPI, PCI IRQ: add PCI_USING penalty for ISA interrupts
>   Revert "ACPI,PCI,IRQ: remove SCI penalize function"
> 
>  arch/x86/kernel/acpi/boot.c |  1 +
>  drivers/acpi/pci_link.c     | 71 ++++++++++++++++++++++-----------------------
>  include/linux/acpi.h        |  1 +
>  3 files changed, 37 insertions(+), 36 deletions(-)
> 

I've queued up the series, but still waiting on Bjorn's response.

Thanks,
Rafael

^ permalink raw reply

* [PATCH] MAINTAINERS: Add ARM64-specific ACPI maintainers entry
From: Rafael J. Wysocki @ 2016-10-11 21:52 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161005112540.22189-1-lorenzo.pieralisi@arm.com>

On Wednesday, October 05, 2016 12:25:40 PM Lorenzo Pieralisi wrote:
> The ARM64 architecture defines ARM64 specific ACPI bindings to
> configure and set-up arch specific components. To simplify
> code reviews/updates and streamline the maintainership structure
> supporting the arch specific code, a new arm64 directory was created in
> /drivers/acpi, to contain ACPI code that is specific to ARM64
> architecture.
> 
> Add the ARM64-specific ACPI maintainers entry in MAINTAINERS for
> the newly created subdirectory and respective code content.
> 
> Lorenzo Pieralisi will be in charge of submitting and managing
> the pull requests on behalf of all maintainers listed.
> 
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Link: http://lkml.kernel.org/r/1603704.EGiVTcCxLR at vostro.rjw.lan
> ---
>  MAINTAINERS | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f593300..2a70dd9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -316,6 +316,14 @@ W:	https://01.org/linux-acpi
>  S:	Supported
>  F:	drivers/acpi/fan.c
>  
> +ACPI FOR ARM64 (ACPI/arm64)
> +M:	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> +M:	Hanjun Guo <hanjun.guo@linaro.org>
> +M:	Sudeep Holla <sudeep.holla@arm.com>
> +L:	linux-acpi at vger.kernel.org
> +S:	Maintained
> +F:	drivers/acpi/arm64
> +
>  ACPI THERMAL DRIVER
>  M:	Zhang Rui <rui.zhang@intel.com>
>  L:	linux-acpi at vger.kernel.org
> 

Applied (with tags).

Thanks,
Rafael

^ permalink raw reply

* latest version of bluetooth for n950?
From: Sebastian Reichel @ 2016-10-11 21:41 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161011145140.cq3jex2r23wuayph@earth>

Hi,

On Tue, Oct 11, 2016 at 04:51:40PM +0200, Sebastian Reichel wrote:
> On Tue, Oct 11, 2016 at 09:47:04AM +0200, Pavel Machek wrote:
> > I got some free cycles to play with n900 and bluetooth. There's still
> > some unrelated config option that breaks even the old vesion of
> > patches, but I'm ready for more debugging now.
> > 
> > Could I have the latest version of the (clean) bluetooth patch? I have
> > feeling it might work with the right config option, and would like to
> > try.
> > 
> > For the record, here's working .config and the tricky tricky oneliner
> > that took me week to figure out.
> 
> https://git.kernel.org/cgit/linux/kernel/git/sre/linux-n900.git/log/?h=n950-bluetooth
> 
> My local branch is based on 4.8 and fixes a few of Marcel's
> comments. I'm currently at ELCE, but I will push my local
> stuff later in the hotel after verifying, that it works as
> expected (luckily I brought N950 with me :)).

It does not. Rebasing the pushed branch to v4.8 works, so the
problem is somewhere in my new changes. I will try to have a
look at it tomorrow.

The changes shouldn't affect you for any tests, though. Just
take the branch from above (and optionally rebase to v4.8).

-- Sebastian


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^ permalink raw reply

* [PATCH v19 01/12] fpga: add bindings document for fpga region
From: atull @ 2016-10-11 19:31 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161008204928.GB11595@rob-hp-laptop>

On Sat, 8 Oct 2016, Rob Herring wrote:

> On Wed, Sep 28, 2016 at 01:21:49PM -0500, Alan Tull wrote:
> > New bindings document for FPGA Region to support programming
> > FPGA's under Device Tree control
> > 
> > Signed-off-by: Alan Tull <atull@opensource.altera.com>
> > Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> > ---
> > v9:  initial version added to this patchset
> > v10: s/fpga/FPGA/g
> >      replace DT overlay example with slightly more complicated example
> >      move to staging/simple-fpga-bus
> > v11: No change in this patch for v11 of the patch set
> > v12: Moved out of staging.
> >      Changed to use FPGA bridges framework instead of resets
> >      for bridges.
> > v13: bridge at 0xff20000 -> bridge at ff200000, etc
> >      Leave out directly talking about overlays
> >      Remove regs and clocks directly under simple-fpga-bus in example
> >      Use common "firmware-name" binding instead of "fpga-firmware"
> > v14: Use firmware-name in bindings description
> >      Call it FPGA Area
> >      Remove bindings that specify FPGA Manager and FPGA Bridges
> > v15: Cleanup as per Rob's comments
> >      Combine usage doc with bindings document
> >      Document as being Altera specific
> >      Additions and changes to add FPGA Bus
> > v16: Reworked to document FPGA Regions
> >      rename altera-fpga-bus-fpga-area.txt -> fpga-region.txt
> >      Remove references that made it sound exclusive to Altera
> >      Remove altr, prefix from fpga-bus and fpga-area compatible strings
> >      Added Moritz' usage example with Xilinx
> >      Cleaned up unit addresses
> > v17: Lots of rewrites to try to make things clearer
> >      Clarify that overlay can be rejected if FPGA isn't programmed
> >      Add external-fpga-config binding already used in u-boot
> >      Change partial-reconfig binding to partial-fpga-config to align
> >        with existing u-boot binding format *-fpga-config
> >      Add a document from Xilinx' website
> > v18: Fix node names underscores to be hyphens
> >      Fix copy/pasted duplicate nodes in diagram
> > v19: Fix more underscores
> >      Make FPGA regions to be children of bridges
> >      General cleanup and clarification
> > ---
> >  .../devicetree/bindings/fpga/fpga-region.txt       | 494 +++++++++++++++++++++
> >  1 file changed, 494 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/fpga/fpga-region.txt
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> Nice job.
> 
> Rob
> 

Thanks, Rob!  I'll add your reviewed-by in v20 just
to make it even.  

Besides that, squashing some patches and some
minor changes for the Arria10 FPGA manager support.

Alan

^ permalink raw reply

* [PATCH V3 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1
From: Russell King - ARM Linux @ 2016-10-11 18:52 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1475875882-2604-3-git-send-email-tbaicar@codeaurora.org>

On Fri, Oct 07, 2016 at 03:31:14PM -0600, Tyler Baicar wrote:
> +static void cper_estatus_print_section_v300(const char *pfx,
> +	const struct acpi_hest_generic_data_v300 *gdata)
> +{
> +	__u8 hour, min, sec, day, mon, year, century, *timestamp;
> +
> +	if (gdata->validation_bits & ACPI_HEST_GEN_VALID_TIMESTAMP) {
> +		timestamp = (__u8 *)&(gdata->time_stamp);
> +		memcpy(&sec, timestamp, 1);
> +		memcpy(&min, timestamp + 1, 1);
> +		memcpy(&hour, timestamp + 2, 1);
> +		memcpy(&day, timestamp + 4, 1);
> +		memcpy(&mon, timestamp + 5, 1);
> +		memcpy(&year, timestamp + 6, 1);
> +		memcpy(&century, timestamp + 7, 1);

This is utterly silly.  Why are you using memcpy() to access individual
bytes of a u8 pointer?  What's wrong with:

		sec = timestamp[0];
		min = timestamp[1];
		hour = timestamp[2];
		day = timestamp[4];
		mon = timestamp[5];
		year = timestamp[6];
		century = timestamp[7];

or even do the conversion here:

		sec = bcd2bin(timestamp[0]);
... etc ...

> +		printk("%stime: ", pfx);
> +		printk("%7s", 0x01 & *(timestamp + 3) ? "precise" : "");
> +		printk(" %02d:%02d:%02d %02d%02d-%02d-%02d\n",
> +			bcd2bin(hour), bcd2bin(min), bcd2bin(sec),
> +			bcd2bin(century), bcd2bin(year), bcd2bin(mon),
> +			bcd2bin(day));
> +	}

It's also a good idea to (as much as possible) keep to single printk()
statements - which makes the emission of the string more atomic wrt
other CPUs and contexts.  So, this should probably become (with the
conversion being done at the assignment of sec etc):

		printk("%stime: %7s %02d:%02d:%02d %02d%02d-%02d-%02d\n",
			pfx, 0x01 & timestamp[3] ? "precise" : "",
			hour, min, sec, century, year, mon, day);

which, IMHO, looks a lot nicer and doesn't risk some other printk()
getting between each individual part of the line.

> +}
> +
>  static void cper_estatus_print_section(
> -	const char *pfx, const struct acpi_hest_generic_data *gdata, int sec_no)
> +	const char *pfx, struct acpi_hest_generic_data *gdata, int sec_no)
>  {
>  	uuid_le *sec_type = (uuid_le *)gdata->section_type;
>  	__u16 severity;
>  	char newpfx[64];
>  
> +	if ((gdata->revision >> 8) >= 0x03)
> +		cper_estatus_print_section_v300(pfx,
> +			(const struct acpi_hest_generic_data_v300 *)gdata);
> +
>  	severity = gdata->error_severity;
>  	printk("%s""Error %d, type: %s\n", pfx, sec_no,
>  	       cper_severity_str(severity));

Not sure why you have the "" here - %sError works just as well and the
"" is just obfuscation - the compiler will eliminate the double-double
quote and merge the strings anyway.

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

^ permalink raw reply

* [PATCH 3/5] Input: add driver for Ilitek ili2139 touch IC
From: Dmitry Torokhov @ 2016-10-11 18:51 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <220181476210841@web5j.yandex.ru>

On Wed, Oct 12, 2016 at 02:34:01AM +0800, Icenowy Zheng wrote:
> 
> 
> 12.10.2016, 01:40, "Dmitry Torokhov" <dmitry.torokhov@gmail.com>:
> > Hi Icenowy,
> >
> > On Tue, Oct 11, 2016 at 08:33:57AM +0800, Icenowy Zheng wrote:
> >> ?This driver adds support for Ilitek ili2139 touch IC, which is used in
> >> ?several Colorfly tablets (for example, Colorfly E708 Q1, which is an
> >> ?Allwinner A31s tablet with mainline kernel support).
> >>
> >> ?Theortically it may support more Ilitek touch ICs, however, only ili2139
> >> ?is used in any mainlined device.
> >>
> >> ?It supports device tree enumeration, with screen resolution and axis
> >> ?quirks configurable.
> >>
> >> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > Please extend ili210x.c instead of adding brand new driver, they look
> > very similar.
> >
> > Thanks.
> 
> The driver is too old, lack of maintaince and needs some platform data hacks.
> (At least makes it not capable to be used on current ARM devices, as they're
> described with device tree)

There are many drivers that can do both platform and dt-setup.

> 
> Maybe I will rename the new driver modified by me to ili210x, add support for
> the old protocol (but I have no chips to test it), and drop the old ili210x.
> (This driver is capable of dt probing, and uses devm_ functions)

You can add "racy on removal" to the list (you need to take care your
work is canceled at right times, and canceling it before interrupt is
freed is not the right time as interrupt might fire and the work get
scheduled again). Also I think your driver is essentially working in
polling mode because you always reschedule the delayed work.

No, like I said, please work with existing driver, adding DT support and
support for the newer version of the protocol.

Thanks.

-- 
Dmitry

^ permalink raw reply

* The possible regression in kernel 4.8 - clk: imx: correct AV PLL rate formula
From: Otavio Salvador @ 2016-10-11 18:34 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CAOMZO5CVggufx2U0pZUXd1o=i36Jo-c1B=hgFcSaWeM+=oagaQ@mail.gmail.com>

On Tue, Oct 11, 2016 at 3:00 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Ken,
>
> On Tue, Oct 11, 2016 at 2:49 PM, Ken.Lin <ken.lin@advantech.com> wrote:
>
>> With the patches applied, the pixel clock (148500000 required for 1920x1080 at 60) is correct as we checked in kernel 4.7 and the actual measurement result looked good as we expected.
>> I think the patches should fix the issue.
>
> That's good news. Thanks for testing.
>
> Emil is working on a v3 version of the patch series.
>
> Emil,
>
> Please add Ken Lin on Cc when you submit v3.

And what will be done regarding 4.8? Is the faulty change to be
reverted or this patches will be backported?

-- 
Otavio Salvador                             O.S. Systems
http://www.ossystems.com.br        http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854            Mobile: +1 (347) 903-9750

^ permalink raw reply

* [PATCH 3/5] Input: add driver for Ilitek ili2139 touch IC
From: Icenowy Zheng @ 2016-10-11 18:34 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161011174046.GA27925@dtor-ws>



12.10.2016, 01:40, "Dmitry Torokhov" <dmitry.torokhov@gmail.com>:
> Hi Icenowy,
>
> On Tue, Oct 11, 2016 at 08:33:57AM +0800, Icenowy Zheng wrote:
>> ?This driver adds support for Ilitek ili2139 touch IC, which is used in
>> ?several Colorfly tablets (for example, Colorfly E708 Q1, which is an
>> ?Allwinner A31s tablet with mainline kernel support).
>>
>> ?Theortically it may support more Ilitek touch ICs, however, only ili2139
>> ?is used in any mainlined device.
>>
>> ?It supports device tree enumeration, with screen resolution and axis
>> ?quirks configurable.
>>
>> ?Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Please extend ili210x.c instead of adding brand new driver, they look
> very similar.
>
> Thanks.

The driver is too old, lack of maintaince and needs some platform data hacks.
(At least makes it not capable to be used on current ARM devices, as they're
described with device tree)

Maybe I will rename the new driver modified by me to ili210x, add support for
the old protocol (but I have no chips to test it), and drop the old ili210x.
(This driver is capable of dt probing, and uses devm_ functions)

>
>> ?---
>> ??drivers/input/touchscreen/Kconfig | 14 ++
>> ??drivers/input/touchscreen/Makefile | 1 +
>> ??drivers/input/touchscreen/ili2139.c | 320 ++++++++++++++++++++++++++++++++++++
>> ??3 files changed, 335 insertions(+)
>> ??create mode 100644 drivers/input/touchscreen/ili2139.c
>>
>> ?diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
>> ?index 5079813..bb4d9d2 100644
>> ?--- a/drivers/input/touchscreen/Kconfig
>> ?+++ b/drivers/input/touchscreen/Kconfig
>> ?@@ -348,6 +348,20 @@ config TOUCHSCREEN_ILI210X
>> ????????????To compile this driver as a module, choose M here: the
>> ????????????module will be called ili210x.
>>
>> ?+config TOUCHSCREEN_ILI2139
>> ?+ tristate "Ilitek ILI2139 based touchscreen"
>> ?+ depends on I2C
>> ?+ depends on OF
>> ?+ help
>> ?+ Say Y here if you have a ILI2139 based touchscreen
>> ?+ controller. Such kind of chipsets can be found in several
>> ?+ Colorfly tablets.
>> ?+
>> ?+ If unsure, say N.
>> ?+
>> ?+ To compile this driver as a module, choose M here; the
>> ?+ module will be called ili2139.
>> ?+
>> ??config TOUCHSCREEN_IPROC
>> ??????????tristate "IPROC touch panel driver support"
>> ??????????depends on ARCH_BCM_IPROC || COMPILE_TEST
>> ?diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
>> ?index 81b8645..930b5e2 100644
>> ?--- a/drivers/input/touchscreen/Makefile
>> ?+++ b/drivers/input/touchscreen/Makefile
>> ?@@ -40,6 +40,7 @@ obj-$(CONFIG_TOUCHSCREEN_EGALAX_SERIAL) += egalax_ts_serial.o
>> ??obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
>> ??obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o
>> ??obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
>> ?+obj-$(CONFIG_TOUCHSCREEN_ILI2139) += ili2139.o
>> ??obj-$(CONFIG_TOUCHSCREEN_IMX6UL_TSC) += imx6ul_tsc.o
>> ??obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o
>> ??obj-$(CONFIG_TOUCHSCREEN_INTEL_MID) += intel-mid-touch.o
>> ?diff --git a/drivers/input/touchscreen/ili2139.c b/drivers/input/touchscreen/ili2139.c
>> ?new file mode 100644
>> ?index 0000000..65c2dea
>> ?--- /dev/null
>> ?+++ b/drivers/input/touchscreen/ili2139.c
>> ?@@ -0,0 +1,320 @@
>> ?+/* -------------------------------------------------------------------------
>> ?+ * Copyright (C) 2016, Icenowy Zheng <icenowy@aosc.xyz>
>> ?+ *
>> ?+ * Derived from:
>> ?+ * ili210x.c
>> ?+ * Copyright (C) Olivier Sobrie <olivier@sobrie.be>
>> ?+ *
>> ?+ * This program is free software; you can redistribute it and/or modify
>> ?+ * it under the terms of the GNU General Public License as published by
>> ?+ * the Free Software Foundation; either version 2 of the License, or
>> ?+ * (at your option) any later version.
>> ?+ *
>> ?+ * This program is distributed in the hope that it will be useful,
>> ?+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> ?+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> ?+ * GNU General Public License for more details.
>> ?+ * -------------------------------------------------------------------------
>> ?+ */
>> ?+
>> ?+#include <linux/module.h>
>> ?+#include <linux/i2c.h>
>> ?+#include <linux/interrupt.h>
>> ?+#include <linux/slab.h>
>> ?+#include <linux/input.h>
>> ?+#include <linux/input/mt.h>
>> ?+#include <linux/input/touchscreen.h>
>> ?+#include <linux/delay.h>
>> ?+#include <linux/workqueue.h>
>> ?+
>> ?+#define DEFAULT_POLL_PERIOD 20
>> ?+
>> ?+#define MAX_TOUCHES 10
>> ?+#define COMPATIBLE_TOUCHES 2
>> ?+
>> ?+/* Touchscreen commands */
>> ?+#define REG_TOUCHDATA 0x10
>> ?+#define REG_TOUCHSUBDATA 0x11
>> ?+#define REG_PANEL_INFO 0x20
>> ?+#define REG_FIRMWARE_VERSION 0x40
>> ?+#define REG_PROTO_VERSION 0x42
>> ?+
>> ?+#define SUBDATA_STATUS_TOUCH_POINT 0x80
>> ?+#define SUBDATA_STATUS_RELEASE_POINT 0x00
>> ?+
>> ?+struct finger {
>> ?+ u8 x_low;
>> ?+ u8 x_high;
>> ?+ u8 y_low;
>> ?+ u8 y_high;
>> ?+} __packed;
>> ?+
>> ?+struct touchdata {
>> ?+ u8 length;
>> ?+ struct finger finger[COMPATIBLE_TOUCHES];
>> ?+} __packed;
>> ?+
>> ?+struct touch_subdata {
>> ?+ u8 status;
>> ?+ struct finger finger;
>> ?+} __packed;
>> ?+
>> ?+struct panel_info {
>> ?+ struct finger finger_max;
>> ?+ u8 xchannel_num;
>> ?+ u8 ychannel_num;
>> ?+} __packed;
>> ?+
>> ?+struct firmware_version {
>> ?+ u8 id;
>> ?+ u8 major;
>> ?+ u8 minor;
>> ?+} __packed;
>> ?+
>> ?+struct ili2139 {
>> ?+ struct i2c_client *client;
>> ?+ struct input_dev *input;
>> ?+ unsigned int poll_period;
>> ?+ struct delayed_work dwork;
>> ?+ struct touchscreen_properties prop;
>> ?+ int slots[MAX_TOUCHES];
>> ?+ int ids[MAX_TOUCHES];
>> ?+ struct input_mt_pos pos[MAX_TOUCHES];
>> ?+};
>> ?+
>> ?+static int ili2139_read_reg(struct i2c_client *client, u8 reg, void *buf,
>> ?+ size_t len)
>> ?+{
>> ?+ struct i2c_msg msg[2] = {
>> ?+ {
>> ?+ .addr = client->addr,
>> ?+ .flags = 0,
>> ?+ .len = 1,
>> ?+ .buf = &reg,
>> ?+ },
>> ?+ {
>> ?+ .addr = client->addr,
>> ?+ .flags = I2C_M_RD,
>> ?+ .len = len,
>> ?+ .buf = buf,
>> ?+ }
>> ?+ };
>> ?+
>> ?+ if (i2c_transfer(client->adapter, msg, 2) != 2) {
>> ?+ dev_err(&client->dev, "i2c transfer failed\n");
>> ?+ return -EIO;
>> ?+ }
>> ?+
>> ?+ return 0;
>> ?+}
>> ?+
>> ?+static void ili2139_work(struct work_struct *work)
>> ?+{
>> ?+ int id;
>> ?+ struct ili2139 *priv = container_of(work, struct ili2139,
>> ?+ dwork.work);
>> ?+ struct i2c_client *client = priv->client;
>> ?+ struct touchdata touchdata;
>> ?+ struct touch_subdata subdata;
>> ?+ int error;
>> ?+
>> ?+ error = ili2139_read_reg(client, REG_TOUCHDATA,
>> ?+ &touchdata, sizeof(touchdata));
>> ?+ if (error) {
>> ?+ dev_err(&client->dev,
>> ?+ "Unable to get touchdata, err = %d\n", error);
>> ?+ return;
>> ?+ }
>> ?+
>> ?+ for (id = 0; id < touchdata.length; id++) {
>> ?+ error = ili2139_read_reg(client, REG_TOUCHSUBDATA, &subdata,
>> ?+ sizeof(subdata));
>> ?+ if (error) {
>> ?+ dev_err(&client->dev,
>> ?+ "Unable to get touch subdata, err = %d\n",
>> ?+ error);
>> ?+ return;
>> ?+ }
>> ?+
>> ?+ priv->ids[id] = subdata.status & 0x3F;
>> ?+
>> ?+ /* The sequence changed in the v2 subdata protocol. */
>> ?+ touchscreen_set_mt_pos(&priv->pos[id], &priv->prop,
>> ?+ (subdata.finger.x_high | (subdata.finger.x_low << 8)),
>> ?+ (subdata.finger.y_high | (subdata.finger.y_low << 8)));
>> ?+ }
>> ?+
>> ?+ input_mt_assign_slots(priv->input, priv->slots, priv->pos,
>> ?+ touchdata.length, 0);
>> ?+
>> ?+ for (id = 0; id < touchdata.length; id++) {
>> ?+ input_mt_slot(priv->input, priv->slots[id]);
>> ?+ input_mt_report_slot_state(priv->input, MT_TOOL_FINGER,
>> ?+ subdata.status &
>> ?+ SUBDATA_STATUS_TOUCH_POINT);
>> ?+ input_report_abs(priv->input, ABS_MT_POSITION_X,
>> ?+ priv->pos[id].x);
>> ?+ input_report_abs(priv->input, ABS_MT_POSITION_Y,
>> ?+ priv->pos[id].y);
>> ?+ }
>> ?+
>> ?+ input_mt_sync_frame(priv->input);
>> ?+ input_sync(priv->input);
>> ?+
>> ?+ schedule_delayed_work(&priv->dwork,
>> ?+ msecs_to_jiffies(priv->poll_period));
>> ?+}
>> ?+
>> ?+static irqreturn_t ili2139_irq(int irq, void *irq_data)
>> ?+{
>> ?+ struct ili2139 *priv = irq_data;
>> ?+
>> ?+ schedule_delayed_work(&priv->dwork, 0);
>> ?+
>> ?+ return IRQ_HANDLED;
>> ?+}
>> ?+
>> ?+static int ili2139_i2c_probe(struct i2c_client *client,
>> ?+ const struct i2c_device_id *id)
>> ?+{
>> ?+ struct device *dev = &client->dev;
>> ?+ struct ili2139 *priv;
>> ?+ struct input_dev *input;
>> ?+ struct panel_info panel;
>> ?+ struct firmware_version firmware;
>> ?+ int xmax, ymax;
>> ?+ int error;
>> ?+
>> ?+ dev_dbg(dev, "Probing for ILI2139 I2C Touschreen driver");
>> ?+
>> ?+ if (client->irq <= 0) {
>> ?+ dev_err(dev, "No IRQ!\n");
>> ?+ return -ENODEV;
>> ?+ }
>> ?+
>> ?+ /* Get firmware version */
>> ?+ error = ili2139_read_reg(client, REG_FIRMWARE_VERSION,
>> ?+ &firmware, sizeof(firmware));
>> ?+ if (error) {
>> ?+ dev_err(dev, "Failed to get firmware version, err: %d\n",
>> ?+ error);
>> ?+ return error;
>> ?+ }
>> ?+
>> ?+ /* get panel info */
>> ?+ error = ili2139_read_reg(client, REG_PANEL_INFO, &panel, sizeof(panel));
>> ?+ if (error) {
>> ?+ dev_err(dev, "Failed to get panel information, err: %d\n",
>> ?+ error);
>> ?+ return error;
>> ?+ }
>> ?+
>> ?+ xmax = panel.finger_max.x_low | (panel.finger_max.x_high << 8);
>> ?+ ymax = panel.finger_max.y_low | (panel.finger_max.y_high << 8);
>> ?+
>> ?+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> ?+ input = devm_input_allocate_device(dev);
>> ?+ if (!priv || !input)
>> ?+ return -ENOMEM;
>> ?+
>> ?+ priv->client = client;
>> ?+ priv->input = input;
>> ?+ priv->poll_period = DEFAULT_POLL_PERIOD;
>> ?+ INIT_DELAYED_WORK(&priv->dwork, ili2139_work);
>> ?+
>> ?+ /* Setup input device */
>> ?+ input->name = "ILI2139 Touchscreen";
>> ?+ input->id.bustype = BUS_I2C;
>> ?+ input->dev.parent = dev;
>> ?+
>> ?+ __set_bit(EV_SYN, input->evbit);
>> ?+ __set_bit(EV_KEY, input->evbit);
>> ?+ __set_bit(EV_ABS, input->evbit);
>> ?+
>> ?+ /* Multi touch */
>> ?+ input_mt_init_slots(input, MAX_TOUCHES, INPUT_MT_DIRECT |
>> ?+ INPUT_MT_DROP_UNUSED | INPUT_MT_TRACK);
>> ?+ input_set_abs_params(input, ABS_MT_POSITION_X, 0, xmax, 0, 0);
>> ?+ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, ymax, 0, 0);
>> ?+
>> ?+ touchscreen_parse_properties(input, true, &priv->prop);
>> ?+
>> ?+ input_set_drvdata(input, priv);
>> ?+ i2c_set_clientdata(client, priv);
>> ?+
>> ?+ error = devm_request_irq(dev, client->irq, ili2139_irq,
>> ?+ IRQF_TRIGGER_FALLING, client->name, priv);
>> ?+ if (error) {
>> ?+ dev_err(dev, "Unable to request touchscreen IRQ, err: %d\n",
>> ?+ error);
>> ?+ return error;
>> ?+ }
>> ?+
>> ?+ error = input_register_device(priv->input);
>> ?+ if (error) {
>> ?+ dev_err(dev, "Cannot register input device, err: %d\n", error);
>> ?+ return error;
>> ?+ }
>> ?+
>> ?+ device_init_wakeup(&client->dev, 1);
>> ?+
>> ?+ dev_dbg(dev,
>> ?+ "ILI2139 initialized (IRQ: %d), firmware version %d.%d.%d",
>> ?+ client->irq, firmware.id, firmware.major, firmware.minor);
>> ?+
>> ?+ return 0;
>> ?+}
>> ?+
>> ?+static int ili2139_i2c_remove(struct i2c_client *client)
>> ?+{
>> ?+ struct ili2139 *priv = i2c_get_clientdata(client);
>> ?+
>> ?+ cancel_delayed_work_sync(&priv->dwork);
>> ?+
>> ?+ return 0;
>> ?+}
>> ?+
>> ?+static int __maybe_unused ili2139_i2c_suspend(struct device *dev)
>> ?+{
>> ?+ struct i2c_client *client = to_i2c_client(dev);
>> ?+
>> ?+ if (device_may_wakeup(&client->dev))
>> ?+ enable_irq_wake(client->irq);
>> ?+
>> ?+ return 0;
>> ?+}
>> ?+
>> ?+static int __maybe_unused ili2139_i2c_resume(struct device *dev)
>> ?+{
>> ?+ struct i2c_client *client = to_i2c_client(dev);
>> ?+
>> ?+ if (device_may_wakeup(&client->dev))
>> ?+ disable_irq_wake(client->irq);
>> ?+
>> ?+ return 0;
>> ?+}
>> ?+
>> ?+static SIMPLE_DEV_PM_OPS(ili2139_i2c_pm,
>> ?+ ili2139_i2c_suspend, ili2139_i2c_resume);
>> ?+
>> ?+static const struct i2c_device_id ili2139_i2c_id[] = {
>> ?+ { "ili2139", 0 },
>> ?+ { }
>> ?+};
>> ?+MODULE_DEVICE_TABLE(i2c, ili2139_i2c_id);
>> ?+
>> ?+static struct i2c_driver ili2139_ts_driver = {
>> ?+ .driver = {
>> ?+ .name = "ili2139_i2c",
>> ?+ .pm = &ili2139_i2c_pm,
>> ?+ },
>> ?+ .id_table = ili2139_i2c_id,
>> ?+ .probe = ili2139_i2c_probe,
>> ?+ .remove = ili2139_i2c_remove,
>> ?+};
>> ?+
>> ?+module_i2c_driver(ili2139_ts_driver);
>> ?+
>> ?+MODULE_AUTHOR("Olivier Sobrie <olivier@sobrie.be>");
>> ?+MODULE_DESCRIPTION("ILI2139 I2C Touchscreen Driver");
>> ?+MODULE_LICENSE("GPL");
>> ?--
>> ?2.10.1
>
> --
> Dmitry

^ permalink raw reply

* [PATCH v2 8/8] crypto: arm/aes-ce - fix for big endian
From: Ard Biesheuvel @ 2016-10-11 18:15 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1476209720-21114-1-git-send-email-ard.biesheuvel@linaro.org>

The AES key schedule generation is mostly endian agnostic, with the
exception of the rotation and the incorporation of the round constant
at the start of each round. So implement a big endian specific version
of that part to make the whole routine big endian compatible.

Fixes: 86464859cc77 ("crypto: arm - AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm/crypto/aes-ce-glue.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/crypto/aes-ce-glue.c b/arch/arm/crypto/aes-ce-glue.c
index aef022a87c53..04410d9f5e72 100644
--- a/arch/arm/crypto/aes-ce-glue.c
+++ b/arch/arm/crypto/aes-ce-glue.c
@@ -88,8 +88,13 @@ static int ce_aes_expandkey(struct crypto_aes_ctx *ctx, const u8 *in_key,
 		u32 *rki = ctx->key_enc + (i * kwords);
 		u32 *rko = rki + kwords;
 
+#ifndef CONFIG_CPU_BIG_ENDIAN
 		rko[0] = ror32(ce_aes_sub(rki[kwords - 1]), 8);
 		rko[0] = rko[0] ^ rki[0] ^ rcon[i];
+#else
+		rko[0] = rol32(ce_aes_sub(rki[kwords - 1]), 8);
+		rko[0] = rko[0] ^ rki[0] ^ (rcon[i] << 24);
+#endif
 		rko[1] = rko[0] ^ rki[1];
 		rko[2] = rko[1] ^ rki[2];
 		rko[3] = rko[2] ^ rki[3];
-- 
2.7.4

^ permalink raw reply related

* [PATCH v2 7/8] crypto: arm64/aes-xts-ce: fix for big endian
From: Ard Biesheuvel @ 2016-10-11 18:15 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1476209720-21114-1-git-send-email-ard.biesheuvel@linaro.org>

Emit the XTS tweak literal constants in the appropriate order for a
single 128-bit scalar literal load.

Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 arch/arm64/crypto/aes-ce.S    | 1 +
 arch/arm64/crypto/aes-modes.S | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/crypto/aes-ce.S b/arch/arm64/crypto/aes-ce.S
index 78f3cfe92c08..b46093d567e5 100644
--- a/arch/arm64/crypto/aes-ce.S
+++ b/arch/arm64/crypto/aes-ce.S
@@ -10,6 +10,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #define AES_ENTRY(func)		ENTRY(ce_ ## func)
 #define AES_ENDPROC(func)	ENDPROC(ce_ ## func)
diff --git a/arch/arm64/crypto/aes-modes.S b/arch/arm64/crypto/aes-modes.S
index f6e372c528eb..c53dbeae79f2 100644
--- a/arch/arm64/crypto/aes-modes.S
+++ b/arch/arm64/crypto/aes-modes.S
@@ -386,7 +386,8 @@ AES_ENDPROC(aes_ctr_encrypt)
 	.endm
 
 .Lxts_mul_x:
-	.word		1, 0, 0x87, 0
+CPU_LE(	.quad		1, 0x87		)
+CPU_BE(	.quad		0x87, 1		)
 
 AES_ENTRY(aes_xts_encrypt)
 	FRAME_PUSH
-- 
2.7.4

^ permalink raw reply related


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