* [PATCH] ARM: davinci: enable PM for DT boot
From: Sekhar Nori @ 2016-11-14 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <m2mvh6km8d.fsf@baylibre.com>
On Friday 11 November 2016 10:06 PM, Kevin Hilman wrote:
> Sekhar Nori <nsekhar@ti.com> writes:
>
>> On Tuesday 08 November 2016 11:43 PM, Kevin Hilman wrote:
>>> Hi Sekhar,
>>>
>>> Sekhar Nori <nsekhar@ti.com> writes:
>>>
>>>> On Wednesday 26 October 2016 03:17 AM, Kevin Hilman wrote:
>>>>> Currently system PM is only enabled for legacy (non-DT) boot. Enable
>>>>> for DT boot also.
>>>>>
>>>>> Tested on da850-lcdk using "rtcwake -m mem -s5 -d rtc0".
>>>>>
>>>>> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
>>>>> ---
>>>>> arch/arm/mach-davinci/da8xx-dt.c | 18 ++++++++++++++++++
>>>>> 1 file changed, 18 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
>>>>> index c9f7e9274aa8..a8089fa40d86 100644
>>>>> --- a/arch/arm/mach-davinci/da8xx-dt.c
>>>>> +++ b/arch/arm/mach-davinci/da8xx-dt.c
>>>>> @@ -43,8 +43,26 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
>>>>>
>>>>> #ifdef CONFIG_ARCH_DAVINCI_DA850
>>>>>
>>>>> +static struct davinci_pm_config da850_pm_pdata = {
>>>>> + .sleepcount = 128,
>>>>> +};
>>>>> +
>>>>> +static struct platform_device da850_pm_device = {
>>>>> + .name = "pm-davinci",
>>>>> + .dev = {
>>>>> + .platform_data = &da850_pm_pdata,
>>>>> + },
>>>>> + .id = -1,
>>>>> +};
>>>>> +
>>>>> static void __init da850_init_machine(void)
>>>>> {
>>>>> + int ret;
>>>>> +
>>>>> + ret = da850_register_pm(&da850_pm_device);
>>>>
>>>> I am not sure if it makes sense to keep the "pm device" around anymore.
>>>> I think for both DT and non-DT boot, we can get rid of the fake PM
>>>> device and combine da850_register_pm() and davinci_pm_probe() into a
>>>> single davinci_init_suspend() function which can then be called both for
>>>> DT and non-DT boot.
>>>
>>> Looking closer at this, where do you propose the pdata comes from for
>>> the non-DT boot?
>>>
>>> It seems to me that we can't currently remove the pdata dependency
>>> without breaking the non-DT platforms, so the approach proposed here is
>>> the least invasive.
>>
>> There is a single value of sleep count that is used today (128). So I
>> was thinking we can hardcode that in pm.c. We are not going to add more
>> board files anyway so there is no risk here.
>>
>> For future, if a different sleepcount value is needed, it will need to
>> be a new DT property.
>
> Right, but getting rid of the pdata is more than just hard-coding the
> sleep count. There are a bunch of other fields in the pdata, which are
> filled out to some standard defaults in da850.c. Are you proposing to
> hard-code those in pm.c also?
Yeah. When I wrote the code for pm.c, I wrote it hoping that it can be
used on other davinci devices too. But since then, no other DaVinci
device has gained PM support. DM365 could support PM, but its not
supported even on TI's internal releases.
Even if in future PM does get supported on DM365, platform data will not
be used for sure. And besides, the sequence in sleep.S has only ever
been tested on DA850 and pretty sure will need some tweaks for running
on DM365.
>
> An intermediate step might be to start by removing the
> platform_device/pdata from the board files, but keep it in da850.c for
> now. Then, a follow-up cleanup could be done to either move all of that
> into pm.c, or use DT.
I think keeping it in pm.c is fine. We could have called pm.c da850-pm.c
but thats not really required I guess since thats the only device in
mach-davinci which supports suspend-to-RAM anyway.
Thanks,
Sekhar
^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Jacek Anaszewski @ 2016-11-14 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9b476f85-d45e-deb6-335d-fc56f6d90350@redhat.com>
Hi,
On 11/13/2016 02:52 PM, Hans de Goede wrote:
> Hi,
>
> On 13-11-16 12:44, Jacek Anaszewski wrote:
>> Hi,
>>
>> On 11/12/2016 10:14 PM, Hans de Goede wrote:
>
> <snip>
>
>>>>> So I would like to propose creating a new read-write
>>>>> user_brightness file.
>>>>>
>>>>> The write behavior would be 100% identical to the brightness
>>>>> file (in code terms it will call the same store function).
>>>>>
>>>>> The the read behavior otoh will be different: it will shows
>>>>> the last brightness as set by the user, this would show the
>>>>> read behavior we really want of brightness: show the real
>>>>> brightness when not blinking / triggers are active and show
>>>>> the brightness used when on when blinking / triggers are active.
>>>>>
>>>>> We could then add poll support on this new user_brightness
>>>>> file, thus avoiding the problem with the extra cpu-load on
>>>>> notifications on blinking / triggers.
>>>>
>>>> I agree that user_brightness allows to solve the issues you raised
>>>> about inconsistent write and read brightness' semantics
>>>> (which is not that painful IMHO).
>>>>
>>>> Reporting non-user brightness changes on user_brightness file
>>>> doesn't sound reasonable though.
>>>
>>> The changes I'm interested in are user brightness changes they
>>> are just not done through sysfs, but through a hardwired hotkey,
>>> they are however very much done by the user.
>>
>> Ah, so this file name would be misleading especially taking into account
>> the context in which "user" is used in kernel, which predominantly
>> means "userspace", e.g. copy_to_user(), copy_from_user().
>>
>>>> Also, how would we read the
>>>> brightness set by the firmware? We'd have to read brightness
>>>> file, so still two files would have to be opened which is
>>>> a second drawback of this approach.
>>>
>>> No, look carefully at the definition of the read behavior
>>> I plan to put in the ABI doc:
>>
>> OK, "user" was what confused me. So in this case changes made
>> by the firmware even if in a result of user activity
>> (pressing hardware key) obviously cannot be treated similarly
>> to the changes made from the userspace context.
>
> In the end both result on the brightness of the device
> changing, so any userspace process interested in monitoring
> the brightness will want to know about both type of changes.
>
>> Unless you're able to give references to the kernel code which
>> contradict my judgement.
>
> AFAIK the audio code will signal volume changes done by
> hardwired buttons the same way as audio changes done
> by userspace calling into the kernel. This also makes
> sense because in the end, what is interesting for a
> mixer app, is that the volume changed, and what the
> new volume is.
OK, so it is indeed similar to your LED use case. Nonetheless
in case of LED controllers it is also possible that hardware
adjusts LED brightness in case of low battery voltage.
If a device is able e.g. to generate an interrupt to notify this
kind of event, then we would like also to be able to notify the client
about that. It wouldn't be user generated brightness change though.
>>> "Reading this file will return the actual led brightness
>>> when not blinking and no triggers are active; reading this
>>> file will return the brightness used when the led is on
>>> when blinking or triggers are active."
>>
>> This is unnecessarily entangled. Blinking means timer trigger
>> is active.
>
> Ok.
>
>>> So for e.g. the backlit keyboard case reading this single
>>> file will return the actual brightness of the backlight,
>>> since this does not involve blinking or triggers.
>>>
>>> Basically the idea is that the user_brightness file
>>> will have the semantics which IMHO the brightness file
>>> itself should have had from the beginning, but which
>>> we can't change now due to ABI reasons.
>>
>> And in fact introducing user_brightness file would indeed
>> fix that shortcoming. However without providing notifications
>> of hw brightness changes on it.
>
> See above, I believe such a file should report any
> changes in brightness, except those caused by triggers,
> so it would report hw brightness changes.
>
> Anyways if you're not interested in fixing the
> shortcomings of the current read behavior on the
> brightness file (I'm fine with that, I can live
> with the shortcomings) I suggest that we simply go
> with v2 of my poll() patch.
v2 entails power consumption related issues.
Generally I think that we could add the file you proposed,
however it would be good to devise a name which will cover
also the cases when brightness is changed by firmware without
user interaction.
>>>> Having no difference in this area between the two approaches
>>>> I'm still in favour of the read-only file for notifying
>>>> brightness changes procured by hardware.
>>>
>>> That brings back the needing 2 fds problem; and does
>>> not solve userspace not being able to reliably read
>>> the led on brightness when blinking or using triggers.
>>>
>>> And this also has the issue that one is doing poll() on
>>> one fd to detect changes on another fd,
>>
>> It is not necessarily true. We can treat the polling on
>> hw_brightness_change file as a means to detect brightness
>> changes procured by hardware and we can read that brightness
>> by executing read on this same fd. It could return -ENODATA
>> if no such an event has occurred so far.
>
> That would still require 2 fds as userspace also wants to
> be able to set the keyboard backlight, but allowing read()
> on the hw_brightness_change file at least fixes the weirdness
> where userspace gets woken from poll() without being able to
> read. So if you insist on going the hw_brightness_change file
> route, then I can live with that (and upower will simply
> need to open 2 fds, that is doable).
>
> But, BUT, I would greatly prefer to just go for v4 of my
> patch, which fixes the only real problem we've seen with
> my patch as original merged without adding a new, somewhat
> convoluted sysfs attribute.
Hmm, v4 still calls led_notify_brightness_change(led_cdev)
from both __led_set_brightness() and __led_set_brightness_blocking().
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* [PATCH 3/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Chen-Yu Tsai @ 2016-11-14 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114085839.qzu7ebeghoqlqygn@lukather>
On Mon, Nov 14, 2016 at 4:58 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sat, Nov 12, 2016 at 12:46:54AM +0800, Icenowy Zheng wrote:
>> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>>
>> Add a device tree file for it.
>>
>> As there's still no mainline-compatible driver for the SDIO WLAN card on
>> board (a new card by Allwinner), the mmc1 controller is not enabled yet.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 148 +++++++++++++++++++++++
>> 2 files changed, 149 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index befcd26..9843fb0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -818,6 +818,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>> sun8i-a33-sinlinx-sina33.dtb \
>> sun8i-a83t-allwinner-h8homlet-v2.dtb \
>> sun8i-a83t-cubietruck-plus.dtb \
>> + sun8i-h2plus-orangepi-zero.dtb \
>> sun8i-h3-bananapi-m2-plus.dtb \
>> sun8i-h3-nanopi-neo.dtb \
>> sun8i-h3-orangepi-2.dtb \
>> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>> new file mode 100644
>> index 0000000..581f56e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>> @@ -0,0 +1,148 @@
>> +/*
>> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
>> + *
>> + * Based on sun8i-h3-orangepi-one.dts, which is:
>> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +/dts-v1/;
>> +#include "sun8i-h2plus.dtsi"
>> +#include "sunxi-common-regulators.dtsi"
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + model = "Xunlong Orange Pi Zero";
>> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2plus",
>> + "allwinner,sun8i-h3";
>
> You don't need the H3 compatible here.
>
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&leds_opi0>, <&leds_r_opi0>;
>> +
>> + pwr_led {
>> + label = "orangepi:green:pwr";
>> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> +
>> + status_led {
>> + label = "orangepi:red:status";
>> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
>> + };
>> + };
>> +};
>> +
>> +&ehci1 {
>> + status = "okay";
>> +};
>> +
>> +&mmc0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
>> + vmmc-supply = <®_vcc3v3>;
>> + bus-width = <4>;
>> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
>> + cd-inverted;
>> + status = "okay";
>> +};
>> +
>> +&ohci1 {
>> + status = "okay";
>> +};
>> +
>> +&pio {
>> + leds_opi0: led_pins at 0 {
>> + allwinner,pins = "PA17";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +};
>> +
>> +&r_pio {
>> + leds_r_opi0: led_pins at 0 {
>> + allwinner,pins = "PL10";
>> + allwinner,function = "gpio_out";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>
> You can drop the drive and pull properties, and could you use the
> generic pins and function properties for those nodes?
Icenowy,
Given that sunxi-next is currently broken for the pinctrl stuff,
you will need this patch to test, until Linus merges it:
https://github.com/wens/linux/commit/e8ce92925a6dd1b2b38ed8699e81d0bc9804de20
>
>> + };
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins_a>;
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart1_pins>;
>> + status = "disabled";
>> +};
>> +
>> +&uart2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart2_pins>;
>> + status = "disabled";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart3_pins>;
>> + status = "disabled";
>> +};
>
> I'm guessing that those UART are exposed on headers?
>
>> +
>> +&usbphy {
>> + /* USB VBUS is always on */
>
> You can put the always on regulators (I'm guessing reg_vcc5v0 ?) here.
AFAIK the regulator properties are optional the the USB PHY.
So we probably don't need to add it. Hans (CC-ed) could explain
his original intent?
Regards
ChenYu
>
>> + status = "okay";
>> +};
>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
^ permalink raw reply
* [PATCH 1/3] soc: sunxi: make sunxi_sram explicitly non-modular
From: Maxime Ripard @ 2016-11-14 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161113190302.18099-2-paul.gortmaker@windriver.com>
On Sun, Nov 13, 2016 at 02:03:00PM -0500, Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> drivers/soc/sunxi/Kconfig:config SUNXI_SRAM
> drivers/soc/sunxi/Kconfig: bool
>
> ...meaning that it currently is not being built as a module by anyone.
>
> Lets remove the modular code that is essentially orphaned, so that
> when reading the driver there is no doubt it is builtin-only.
>
> Since module_platform_driver() uses the same init level priority as
> builtin_platform_driver() the init ordering remains unchanged with
> this commit.
>
> Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
>
> We also delete the MODULE_LICENSE tag etc. since all that information
> is already contained at the top of the file in the comments.
>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 3/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Maxime Ripard @ 2016-11-14 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111164654.15273-3-icenowy@aosc.xyz>
Hi,
On Sat, Nov 12, 2016 at 12:46:54AM +0800, Icenowy Zheng wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>
> Add a device tree file for it.
>
> As there's still no mainline-compatible driver for the SDIO WLAN card on
> board (a new card by Allwinner), the mmc1 controller is not enabled yet.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 148 +++++++++++++++++++++++
> 2 files changed, 149 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index befcd26..9843fb0 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -818,6 +818,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-sinlinx-sina33.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> + sun8i-h2plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> new file mode 100644
> index 0000000..581f56e
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> @@ -0,0 +1,148 @@
> +/*
> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * Based on sun8i-h3-orangepi-one.dts, which is:
> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h2plus.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "Xunlong Orange Pi Zero";
> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2plus",
> + "allwinner,sun8i-h3";
You don't need the H3 compatible here.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&leds_opi0>, <&leds_r_opi0>;
> +
> + pwr_led {
> + label = "orangepi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "orangepi:red:status";
> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + leds_opi0: led_pins at 0 {
> + allwinner,pins = "PA17";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +};
> +
> +&r_pio {
> + leds_r_opi0: led_pins at 0 {
> + allwinner,pins = "PL10";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
You can drop the drive and pull properties, and could you use the
generic pins and function properties for those nodes?
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>;
> + status = "disabled";
> +};
I'm guessing that those UART are exposed on headers?
> +
> +&usbphy {
> + /* USB VBUS is always on */
You can put the always on regulators (I'm guessing reg_vcc5v0 ?) here.
> + status = "okay";
> +};
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 2/3] ARM: dts: sunxi: add Allwinner H2+ dtsi
From: Maxime Ripard @ 2016-11-14 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111164654.15273-2-icenowy@aosc.xyz>
On Sat, Nov 12, 2016 at 12:46:53AM +0800, Icenowy Zheng wrote:
> Allwinner H2+ is a SoC so similar with H3 that H3 drivers and memory map
> is known to work well on H2+, with both BSP kernel/firmware or the
> mainline ones.
>
> So add a dtsi file which only include the H3 dtsi only, so we can add
> H2+-specified nodes in the dtsi file when we find any software
> difference between H2+ and H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
I don't think we need that patch at all. You can do it just like we
did for the R8 and R16, just include the H3 DTSI in your board. We'll
create it if we need it at some point.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 1/3] ARM: sunxi: add support for H2+ SoC
From: Maxime Ripard @ 2016-11-14 8:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111164654.15273-1-icenowy@aosc.xyz>
Hi,
On Sat, Nov 12, 2016 at 12:46:52AM +0800, Icenowy Zheng wrote:
> Allwinner H2+ is a quad-core Cortex-A7 SoC.
>
> It is very like H3, that they share the same SoC ID (0x1680), and H3
> memory maps as well as drivers works well on the SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Documentation/arm/sunxi/README | 4 ++++
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> arch/arm/mach-sunxi/sunxi.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
> index cd02433..1fe4d99c 100644
> --- a/Documentation/arm/sunxi/README
> +++ b/Documentation/arm/sunxi/README
> @@ -63,6 +63,10 @@ SunXi family
> + User Manual
> http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
>
> + - Allwinner H2+ (sun8i)
> + + No document available now, but is known to be working properly with
> + H3 drivers and memory map.
> +
> - Allwinner H3 (sun8i)
> + Datasheet
> http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 3975d0a..0c0f277 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -13,5 +13,6 @@ using one of the following compatible strings:
> allwinner,sun8i-a33
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> + allwinner,sun8i-h2plus
That's a nitpick, but I'd prefer to have sun8i-h2-plus.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 03/16] ARM: berlin: use generic API for enabling SCU
From: Jisheng Zhang @ 2016-11-14 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479099731-28108-4-git-send-email-pankaj.dubey@samsung.com>
Hi Pankaj,
On Mon, 14 Nov 2016 10:31:58 +0530 Pankaj Dubey wrote:
> Now as we have of_scu_enable which takes care of mapping
> scu base from DT, lets use it.
>
> CC: Jisheng Zhang <jszhang@marvell.com>
> CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> ---
> arch/arm/mach-berlin/platsmp.c | 17 +++++------------
> 1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-berlin/platsmp.c b/arch/arm/mach-berlin/platsmp.c
> index 93f9068..25a6ca5 100644
> --- a/arch/arm/mach-berlin/platsmp.c
> +++ b/arch/arm/mach-berlin/platsmp.c
> @@ -60,26 +60,21 @@ static int berlin_boot_secondary(unsigned int cpu, struct task_struct *idle)
> static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
> {
> struct device_node *np;
> - void __iomem *scu_base;
> void __iomem *vectors_base;
>
> - np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> - scu_base = of_iomap(np, 0);
> - of_node_put(np);
> - if (!scu_base)
> - return;
> -
> np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
> cpu_ctrl = of_iomap(np, 0);
> of_node_put(np);
> if (!cpu_ctrl)
> - goto unmap_scu;
> + return;
>
> vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
> if (!vectors_base)
> - goto unmap_scu;
> + return;
> +
> + if (of_scu_enable())
In err code path, we need to unmap vectors_base before return
> + return;
>
> - scu_enable(scu_base);
> flush_cache_all();
>
> /*
> @@ -95,8 +90,6 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
> writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
>
> iounmap(vectors_base);
> -unmap_scu:
> - iounmap(scu_base);
> }
>
> #ifdef CONFIG_HOTPLUG_CPU
^ permalink raw reply
* [PATCH 01/16] ARM: scu: Provide support for parsing SCU device node to enable SCU
From: Jisheng Zhang @ 2016-11-14 8:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114145459.63c23391@xhacker>
Hi Pankaj,
On Mon, 14 Nov 2016 14:54:59 +0800 Jisheng Zhang wrote:
> On Mon, 14 Nov 2016 14:12:51 +0800 Jisheng Zhang wrote:
>
> > Hi Pankaj,
> >
> > On Mon, 14 Nov 2016 10:31:56 +0530 Pankaj Dubey wrote:
> >
> > > Many platforms are duplicating code for enabling SCU, lets add
> > > common code to enable SCU by parsing SCU device node so the duplication
> > > in each platform can be avoided.
> > >
> > > CC: Krzysztof Kozlowski <krzk@kernel.org>
> > > CC: Jisheng Zhang <jszhang@marvell.com>
> > > CC: Russell King <linux@armlinux.org.uk>
> > > CC: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > CC: Patrice Chotard <patrice.chotard@st.com>
> > > CC: Linus Walleij <linus.walleij@linaro.org>
> > > CC: Liviu Dudau <liviu.dudau@arm.com>
> > > CC: Ray Jui <rjui@broadcom.com>
> > > CC: Stephen Warren <swarren@wwwdotorg.org>
> > > CC: Heiko Stuebner <heiko@sntech.de>
> > > CC: Shawn Guo <shawnguo@kernel.org>
> > > CC: Michal Simek <michal.simek@xilinx.com>
> > > CC: Wei Xu <xuwei5@hisilicon.com>
> > > CC: Andrew Lunn <andrew@lunn.ch>
> > > CC: Jun Nie <jun.nie@linaro.org>
> > > Suggested-by: Arnd Bergmann <arnd@arndb.de>
> > > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > > ---
> > > arch/arm/include/asm/smp_scu.h | 4 +++
> > > arch/arm/kernel/smp_scu.c | 56 ++++++++++++++++++++++++++++++++++++++++++
> > > 2 files changed, 60 insertions(+)
> > >
> > > diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
> > > index bfe163c..fdeec07 100644
> > > --- a/arch/arm/include/asm/smp_scu.h
> > > +++ b/arch/arm/include/asm/smp_scu.h
> > > @@ -39,8 +39,12 @@ static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode)
> > >
> > > #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)
> > > void scu_enable(void __iomem *scu_base);
> > > +void __iomem *of_scu_get_base(void);
> > > +int of_scu_enable(void);
> > > #else
> > > static inline void scu_enable(void __iomem *scu_base) {}
> > > +static inline void __iomem *of_scu_get_base(void) {return NULL; }
> > > +static inline int of_scu_enable(void) {return 0; }
> > > #endif
> > >
> > > #endif
> > > diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
> > > index 72f9241..d0ac3ed 100644
> > > --- a/arch/arm/kernel/smp_scu.c
> > > +++ b/arch/arm/kernel/smp_scu.c
> > > @@ -10,6 +10,7 @@
> > > */
> > > #include <linux/init.h>
> > > #include <linux/io.h>
> > > +#include <linux/of_address.h>
> > >
> > > #include <asm/smp_plat.h>
> > > #include <asm/smp_scu.h>
> > > @@ -70,6 +71,61 @@ void scu_enable(void __iomem *scu_base)
> > > */
> > > flush_cache_all();
> > > }
> > > +
> > > +static const struct of_device_id scu_match[] = {
> > > + { .compatible = "arm,cortex-a9-scu", },
> > > + { .compatible = "arm,cortex-a5-scu", },
> > > + { }
> > > +};
> > > +
> > > +/*
> > > + * Helper API to get SCU base address
> > > + * In case platform DT do not have SCU node, or iomap fails
> > > + * this call will fallback and will try to map via call to
> > > + * scu_a9_get_base.
> > > + * This will return ownership of scu_base to the caller
> > > + */
> > > +void __iomem *of_scu_get_base(void)
> > > +{
> > > + unsigned long base = 0;
> > > + struct device_node *np;
> > > + void __iomem *scu_base;
> > > +
> > > + np = of_find_matching_node(NULL, scu_match);
> >
> > could we check np before calling of_iomap()?
> >
> > > + scu_base = of_iomap(np, 0);
> > > + of_node_put(np);
> > > + if (!scu_base) {
> > > + pr_err("%s failed to map scu_base via DT\n", __func__);
> >
> > For non-ca5, non-ca9 based SoCs, we'll see this error msg. We understand
> > what does it mean, but it may confuse normal users. In current version,
> > berlin doesn't complain like this for non-ca9 SoCs
>
> oops, I just realized that the non-ca9 berlin arm SoC version isn't upstreamed.
> Below is the draft version I planed. Basically speaking, the code tries to
> find "arm,cortex-a9-scu" node from DT, if can't, we think we don't need to
> worry about SCU. Is there any elegant solution for my situation?
I just realized that (another realized :D) we uses PSCI enable method for
non-ca9 base SoCs, so "marvell,berlin-smp" enable method is only for the SoCs
which have CA9 compatible SCU. Sorry for the noise, your patch looks good to me.
^ permalink raw reply
* [PATCH 01/16] ARM: scu: Provide support for parsing SCU device node to enable SCU
From: pankaj.dubey @ 2016-11-14 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114141251.7ea86e7a@xhacker>
Hi Jisheng,
On Monday 14 November 2016 11:42 AM, Jisheng Zhang wrote:
> Hi Pankaj,
>
> On Mon, 14 Nov 2016 10:31:56 +0530 Pankaj Dubey wrote:
<snip>
>> +
>> + np = of_find_matching_node(NULL, scu_match);
>
> could we check np before calling of_iomap()?
>
of_iomap takes care of that, and will return NULL if np is NULL.
So additional check of np is not required here.
>> + scu_base = of_iomap(np, 0);
>> + of_node_put(np);
>> + if (!scu_base) {
>> + pr_err("%s failed to map scu_base via DT\n", __func__);
>
> For non-ca5, non-ca9 based SoCs, we'll see this error msg. We understand
> what does it mean, but it may confuse normal users. In current version,
> berlin doesn't complain like this for non-ca9 SoCs
>
OK, let me see other reviewer's comment on this. Then we will decide if
this error message is required or can be omitted.
Thanks,
Pankaj Dubey
^ permalink raw reply
* PM regression with LED changes in next-20161109
From: Pavel Machek @ 2016-11-14 8:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cb0aa3ce-ee48-66b8-510c-bd70917afec9@redhat.com>
Hi!
> >Also, how would we read the
> >brightness set by the firmware? We'd have to read brightness
> >file, so still two files would have to be opened which is
> >a second drawback of this approach.
>
> No, look carefully at the definition of the read behavior
> I plan to put in the ABI doc:
>
> "Reading this file will return the actual led brightness
> when not blinking and no triggers are active; reading this
> file will return the brightness used when the led is on
> when blinking or triggers are active."
That's not sane semantics. Userspace would have to read three files
(racy) to find out about triggers etc.
It also prevents modelling
"hardware-changes-brightness-behind-kernel's-back" as a trigger.
> So for e.g. the backlit keyboard case reading this single
> file will return the actual brightness of the backlight,
> since this does not involve blinking or triggers.
Stop obsessing about "ingle file". FDs are pretty cheap. This is sysfs.
> >Having no difference in this area between the two approaches
> >I'm still in favour of the read-only file for notifying
> >brightness changes procured by hardware.
>
> That brings back the needing 2 fds problem; and does
Actually you have turned "2 fds" into "3 fds", as userspace now needs
to check for trigger _and_ blinking _and_ actuall brightness.
fds are cheap, but that is still not nice design.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06
From: Gabriele Paoloni @ 2016-11-14 8:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161111181606.GN10219@e106497-lin.cambridge.arm.com>
Hi Liviu
> -----Original Message-----
> From: liviu.dudau at arm.com [mailto:liviu.dudau at arm.com]
> Sent: 11 November 2016 18:16
> To: Gabriele Paoloni
> Cc: Arnd Bergmann; linux-arm-kernel at lists.infradead.org; Yuanzhichang;
> mark.rutland at arm.com; devicetree at vger.kernel.org;
> lorenzo.pieralisi at arm.com; minyard at acm.org; linux-pci at vger.kernel.org;
> benh at kernel.crashing.org; John Garry; will.deacon at arm.com; linux-
> kernel at vger.kernel.org; xuwei (O); Linuxarm; zourongrong at gmail.com;
> robh+dt at kernel.org; kantyzc at 163.com; linux-serial at vger.kernel.org;
> catalin.marinas at arm.com; olof at lixom.net; bhelgaas at googl e.com;
> zhichang.yuan02 at gmail.com
> Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on
> Hip06
>
> On Fri, Nov 11, 2016 at 03:53:53PM +0000, Gabriele Paoloni wrote:
> > Hi Liviu
>
> Hi Gabriele,
>
> >
> > > -----Original Message-----
> > > From: liviu.dudau at arm.com [mailto:liviu.dudau at arm.com]
> > > Sent: 11 November 2016 14:46
> > > To: Gabriele Paoloni
> > > Cc: Arnd Bergmann; linux-arm-kernel at lists.infradead.org;
> Yuanzhichang;
> > > mark.rutland at arm.com; devicetree at vger.kernel.org;
> > > lorenzo.pieralisi at arm.com; minyard at acm.org; linux-
> pci at vger.kernel.org;
> > > benh at kernel.crashing.org; John Garry; will.deacon at arm.com; linux-
> > > kernel at vger.kernel.org; xuwei (O); Linuxarm; zourongrong at gmail.com;
> > > robh+dt at kernel.org; kantyzc at 163.com; linux-serial at vger.kernel.org;
> > > catalin.marinas at arm.com; olof at lixom.net; bhelgaas at googl e.com;
> > > zhichang.yuan02 at gmail.com
> > > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on
> > > Hip06
> > >
> > > On Fri, Nov 11, 2016 at 01:39:35PM +0000, Gabriele Paoloni wrote:
> > > > Hi Arnd
> > > >
> > > > > -----Original Message-----
> > > > > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > > > > Sent: 10 November 2016 16:07
> > > > > To: Gabriele Paoloni
> > > > > Cc: linux-arm-kernel at lists.infradead.org; Yuanzhichang;
> > > > > mark.rutland at arm.com; devicetree at vger.kernel.org;
> > > > > lorenzo.pieralisi at arm.com; minyard at acm.org; linux-
> > > pci at vger.kernel.org;
> > > > > benh at kernel.crashing.org; John Garry; will.deacon at arm.com;
> linux-
> > > > > kernel at vger.kernel.org; xuwei (O); Linuxarm;
> zourongrong at gmail.com;
> > > > > robh+dt at kernel.org; kantyzc at 163.com; linux-
> serial at vger.kernel.org;
> > > > > catalin.marinas at arm.com; olof at lixom.net; liviu.dudau at arm.com;
> > > > > bhelgaas at googl e.com; zhichang.yuan02 at gmail.com
> > > > > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver
> implementation on
> > > > > Hip06
> > > > >
> > > > > On Thursday, November 10, 2016 3:36:49 PM CET Gabriele Paoloni
> > > wrote:
> > > > > >
> > > > > > Where should we get the range from? For LPC we know that it
> is
> > > going
> > > > > > Work on anything that is not used by PCI I/O space, and this
> is
> > > > > > why we use [0, PCIBIOS_MIN_IO]
> > > > >
> > > > > It should be allocated the same way we allocate PCI config
> space
> > > > > segments. This is currently done with the io_range list in
> > > > > drivers/pci/pci.c, which isn't perfect but could be extended
> > > > > if necessary. Based on what others commented here, I'd rather
> > > > > make the differences between ISA/LPC and PCI I/O ranges smaller
> > > > > than larger.
> > >
> > > Gabriele,
> > >
> > > >
> > > > I am not sure this would make sense...
> > > >
> > > > IMHO all the mechanism around io_range_list is needed to provide
> the
> > > > "mapping" between I/O tokens and physical CPU addresses.
> > > >
> > > > Currently the available tokens range from 0 to IO_SPACE_LIMIT.
> > > >
> > > > As you know the I/O memory accessors operate on whatever
> > > > __of_address_to_resource sets into the resource (start, end).
> > > >
> > > > With this special device in place we cannot know if a resource is
> > > > assigned with an I/O token or a physical address, unless we
> forbid
> > > > the I/O tokens to be in a specific range.
> > > >
> > > > So this is why we are changing the offsets of all the functions
> > > > handling io_range_list (to make sure that a range is forbidden to
> > > > the tokens and is available to the physical addresses).
> > > >
> > > > We have chosen this forbidden range to be [0, PCIBIOS_MIN_IO)
> > > > because this is the maximum physical I/O range that a non PCI
> device
> > > > can operate on and because we believe this does not impose much
> > > > restriction on the available I/O token range; that now is
> > > > [PCIBIOS_MIN_IO, IO_SPACE_LIMIT].
> > > > So we believe that the chosen forbidden range can accommodate
> > > > any special ISA bus device with no much constraint on the rest
> > > > of I/O tokens...
> > >
> > > Your idea is a good one, however you are abusing PCIBIOS_MIN_IO and
> you
> > > actually need another variable for "reserving" an area in the I/O
> space
> > > that can be used for physical addresses rather than I/O tokens.
> > >
> > > The one good example for using PCIBIOS_MIN_IO is when your
> > > platform/architecture
> > > does not support legacy ISA operations *at all*. In that case
> someone
> > > sets the PCIBIOS_MIN_IO to a non-zero value to reserve that I/O
> range
> > > so that it doesn't get used. With Zhichang's patch you now start
> > > forcing
> > > those platforms to have a valid address below PCIBIOS_MIN_IO.
> >
> > But if PCIBIOS_MIN_IO is 0 then it means that all I/O space is to be
> used
> > by PCI controllers only...
>
> Nope, that is not what it means. It means that PCI devices can see I/O
> addresses
> on the bus that start from 0. There never was any usage for non-PCI
> controllers
So I am a bit confused...
>From http://www.firmware.org/1275/bindings/isa/isa0_4d.ps
It seems that ISA buses operate on cpu I/O address range [0, 0xFFF].
I thought that was the reason why for most architectures we have
PCIBIOS_MIN_IO equal to 0x1000 (so I thought that ISA controllers
usually use [0, PCIBIOS_MIN_IO - 1] )
For those architectures whose PCIBIOS_MIN_IO != 0x1000 probably
they are not fully compliant or they cannot fully support an ISA
controller...?
As said before this series forbid IO tokens to be in [0, PCIBIOS_MIN_IO)
to allow special ISA controllers to use that range with special
accessors.
Having a variable threshold would make life much more difficult
as there would be a probe dependency between the PCI controller and
the special ISA one (PCI to wait for the special ISA device to be
probed and set the right threshold value from DT or ACPI table).
Instead using PCIBIOS_MIN_IO is easier and should not impose much
constraint as [PCIBIOS_MIN_IO, IO_SPACE_LIMIT] is available to
the PCI controller for I/O tokens...
Thanks
Gab
> when PCIBIOS_MIN_IO != 0. That is what Zhichang is trying to do now and
> what
> I think is not the right thing (and not enough anyway).
>
> > so if you have a special bus device using
> > an I/O range in this case should be a PCI controller...
>
> That has always been the case. It is this series that wants to
> introduce the
> new meaning.
>
> > i.e. I would
> > expect it to fall back into the case of I/O tokens redirection rather
> than
> > physical addresses redirection (as mentioned below from my previous
> reply).
> > What do you think?
>
> I think you have looked too much at the code *with* Zhichang's patches
> applied.
> Take a step back and look at how PCIBIOS_MIN_IO is used now, before you
> apply
> the patches. It is all about PCI addresses and there is no notion of
> non-PCI
> busses using PCI framework. Only platforms and architectures that try
> to work
> around some legacy standards (ISA) or HW restrictions.
>
> Best regards,
> Liviu
>
> >
> > Thanks
> >
> > Gab
> >
> >
> > >
> > > For the general case you also have to bear in mind that
> PCIBIOS_MIN_IO
> > > could
> > > be zero. In that case, what is your "forbidden" range? [0, 0) ? So
> it
> > > makes
> > > sense to add a new #define that should only be defined by those
> > > architectures/
> > > platforms that want to reserve on top of PCIBIOS_MIN_IO another
> region
> > > where I/O tokens can't be generated for.
> > >
> > > Best regards,
> > > Liviu
> > >
> > > >
> > > > >
> > > > > > > Your current version has
> > > > > > >
> > > > > > > if (arm64_extio_ops->pfout)
> > > \
> > > > > > > arm64_extio_ops->pfout(arm64_extio_ops-
> > > >devpara,\
> > > > > > > addr, value, sizeof(type));
> > > \
> > > > > > >
> > > > > > > Instead, just subtract the start of the range from the
> logical
> > > > > > > port number to transform it back into a bus-local port
> number:
> > > > > >
> > > > > > These accessors do not operate on IO tokens:
> > > > > >
> > > > > > If (arm64_extio_ops->start > addr || arm64_extio_ops->end <
> addr)
> > > > > > addr is not going to be an I/O token; in fact patch 2/3
> imposes
> > > that
> > > > > > the I/O tokens will start at PCIBIOS_MIN_IO. So from 0 to
> > > > > PCIBIOS_MIN_IO
> > > > > > we have free physical addresses that the accessors can
> operate
> > > on.
> > > > >
> > > > > Ah, I missed that part. I'd rather not use PCIBIOS_MIN_IO to
> refer
> > > to
> > > > > the logical I/O tokens, the purpose of that macro is really
> meant
> > > > > for allocating PCI I/O port numbers within the address space of
> > > > > one bus.
> > > >
> > > > As I mentioned above, special devices operate on CPU addresses
> > > directly,
> > > > not I/O tokens. For them there is no way to distinguish....
> > > >
> > > > >
> > > > > Note that it's equally likely that whichever next platform
> needs
> > > > > non-mapped I/O access like this actually needs them for PCI I/O
> > > space,
> > > > > and that will use it on addresses registered to a PCI host
> bridge.
> > > >
> > > > Ok so here you are talking about a platform that has got an I/O
> range
> > > > under the PCI host controller, right?
> > > > And this I/O range cannot be directly memory mapped but needs
> special
> > > > redirections for the I/O tokens, right?
> > > >
> > > > In this scenario registering the I/O ranges with the forbidden
> range
> > > > implemented by the current patch would still allow to redirect
> I/O
> > > > tokens as long as arm64_extio_ops->start >= PCIBIOS_MIN_IO
> > > >
> > > > So effectively the special PCI host controller
> > > > 1) knows the physical range that needs special redirection
> > > > 2) register such range
> > > > 3) uses pci_pio_to_address() to retrieve the IO tokens for the
> > > > special accessors
> > > > 4) sets arm64_extio_ops->start/end to the IO tokens retrieved in
> 3)
> > > >
> > > > So to be honest I think this patch can fit well both with
> > > > special PCI controllers that need I/O tokens redirection and with
> > > > special non-PCI controllers that need non-PCI I/O physical
> > > > address redirection...
> > > >
> > > > Thanks (and sorry for the long reply but I didn't know how
> > > > to make the explanation shorter :) )
> > > >
> > > > Gab
> > > >
> > > > >
> > > > > If we separate the two steps:
> > > > >
> > > > > a) assign a range of logical I/O port numbers to a bus
> > > > > b) register a set of helpers for redirecting logical I/O
> > > > > port to a helper function
> > > > >
> > > > > then I think the code will get cleaner and more flexible.
> > > > > It should actually then be able to replace the powerpc
> > > > > specific implementation.
> > > > >
> > > > > Arnd
> > >
> > > --
> > > ====================
> > > | I would like to |
> > > | fix the world, |
> > > | but they're not |
> > > | giving me the |
> > > \ source code! /
> > > ---------------
> > > ?\_(?)_/?
>
> --
> ====================
> | I would like to |
> | fix the world, |
> | but they're not |
> | giving me the |
> \ source code! /
> ---------------
> ?\_(?)_/?
^ permalink raw reply
* [PATCH 01/16] ARM: scu: Provide support for parsing SCU device node to enable SCU
From: pankaj.dubey @ 2016-11-14 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161114145459.63c23391@xhacker>
Hi Jisheng,
On Monday 14 November 2016 12:24 PM, Jisheng Zhang wrote:
>
> On Mon, 14 Nov 2016 14:12:51 +0800 Jisheng Zhang wrote:
>
>> Hi Pankaj,
>>
<snip>
>>> + * Helper API to get SCU base address
>>> + * In case platform DT do not have SCU node, or iomap fails
>>> + * this call will fallback and will try to map via call to
>>> + * scu_a9_get_base.
>>> + * This will return ownership of scu_base to the caller
>>> + */
>>> +void __iomem *of_scu_get_base(void)
>>> +{
>>> + unsigned long base = 0;
>>> + struct device_node *np;
>>> + void __iomem *scu_base;
>>> +
>>> + np = of_find_matching_node(NULL, scu_match);
>>
>> could we check np before calling of_iomap()?
>>
>>> + scu_base = of_iomap(np, 0);
>>> + of_node_put(np);
>>> + if (!scu_base) {
>>> + pr_err("%s failed to map scu_base via DT\n", __func__);
>>
>> For non-ca5, non-ca9 based SoCs, we'll see this error msg. We understand
>> what does it mean, but it may confuse normal users. In current version,
>> berlin doesn't complain like this for non-ca9 SoCs
>
> oops, I just realized that the non-ca9 berlin arm SoC version isn't upstreamed.
> Below is the draft version I planed. Basically speaking, the code tries to
> find "arm,cortex-a9-scu" node from DT, if can't, we think we don't need to
> worry about SCU. Is there any elegant solution for my situation?
>
To adopt new generic API I have submitted a patch for Berlin (along with
other various platforms) here:
https://patchwork.kernel.org/patch/9426457/
Please review and if possible test and let me know feedback.
Thanks,
Pankaj Dubey
> Thanks,
> Jisheng
>
>
> ------------8<-------------------
> --- a/arch/arm/mach-berlin/platsmp.c
> +++ b/arch/arm/mach-berlin/platsmp.c
> @@ -56,22 +56,25 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
> void __iomem *vectors_base;
>
> np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> - scu_base = of_iomap(np, 0);
> - of_node_put(np);
> - if (!scu_base)
> - return;
> + if (np) {
> + scu_base = of_iomap(np, 0);
> + of_node_put(np);
> + if (!scu_base)
> + return;
> + scu_enable(scu_base);
> + iounmap(scu_base);
> + }
>
> np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
> cpu_ctrl = of_iomap(np, 0);
> of_node_put(np);
> if (!cpu_ctrl)
> - goto unmap_scu;
> + return;
>
> vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
> if (!vectors_base)
> - goto unmap_scu;
> + return;
>
> - scu_enable(scu_base);
> flush_cache_all();
>
> /*
> @@ -87,8 +90,6 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
> writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
>
> iounmap(vectors_base);
> -unmap_scu:
> - iounmap(scu_base);
> }
>
> static struct smp_operations berlin_smp_ops __initdata = {
>
>
>>
>>> + if (scu_a9_has_base()) {
>>> + base = scu_a9_get_base();
>>> + scu_base = ioremap(base, SZ_4K);
>>> + }
>>> + if (!scu_base) {
>>> + pr_err("%s failed to map scu_base\n", __func__);
>>
>> ditto
>>
>>> + return IOMEM_ERR_PTR(-ENOMEM);
>>> + }
>>> + }
>>> + return scu_base;
>>> +}
>>> +
>>> +/*
>>> + * Enable SCU via mapping scu_base DT
>>> + * If scu_base mapped successfully scu will be enabled and in case of
>>> + * failure if will return non-zero error code
>>> + */
>>> +int of_scu_enable(void)
>>> +{
>>> + void __iomem *scu_base;
>>> +
>>> + scu_base = of_scu_get_base();
>>> + if (!IS_ERR(scu_base)) {
>>> + scu_enable(scu_base);
>>> + iounmap(scu_base);
>>> + return 0;
>>> + }
>>> + return PTR_ERR(scu_base);
>>> +}
>>> +
>>> #endif
>>>
>>> /*
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
>
>
^ permalink raw reply
* [PATCH v2 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: kbuild test robot @ 2016-11-14 8:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479106911-16049-3-git-send-email-wulf@rock-chips.com>
Hi William,
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.9-rc5 next-20161114]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/William-Wu/phy-rockchip-inno-usb2-correct-clk_ops-callback/20161114-150723
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/phy/phy-rockchip-inno-usb2.c: In function 'rockchip_usb2phy_clk480m_prepare':
>> drivers/phy/phy-rockchip-inno-usb2.c:169:3: error: too few arguments to function 'usleep_range'
usleep_range(1200);
^~~~~~~~~~~~
In file included from drivers/phy/phy-rockchip-inno-usb2.c:19:0:
include/linux/delay.h:48:6: note: declared here
void usleep_range(unsigned long min, unsigned long max);
^~~~~~~~~~~~
vim +/usleep_range +169 drivers/phy/phy-rockchip-inno-usb2.c
163 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
164 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
165 if (ret)
166 return ret;
167
168 /* waitting for the clk become stable */
> 169 usleep_range(1200);
170 }
171
172 return 0;
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v3 5/6] arm64: arch_timer: apci: Introduce a generic aquirk framework for erratum
From: Hanjun Guo @ 2016-11-14 8:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478264794-14652-5-git-send-email-dingtianhong@huawei.com>
On 2016/11/4 21:06, Ding Tianhong wrote:
> From: Hanjun Guo <hanjun.guo@linaro.org>
>
> Introduce a general quirk framework for each timer erratum in ACPI,
> which use the oem information in GTDT table for platform specific erratums.
> The struct gtdt_arch_timer_fixup is introduced to record the oem
> information to match the quirk and handle the erratum.
>
> v3: Introduce a generic aquick framework for erratum in ACPI mode.
>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
> ---
> drivers/clocksource/arm_arch_timer.c | 37 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 3d59af1..9bc93e5 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -1068,6 +1068,40 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
> arch_timer_mem_init);
>
> #ifdef CONFIG_ACPI
> +struct gtdt_arch_timer_fixup {
> + char oem_id[ACPI_OEM_ID_SIZE];
> + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
> + u32 oem_revision;
> +
> + /* quirk handler for arch timer erratum */
> + void (*handler)(u32 erratum);
> + u32 erratum;
Hmm, I think we just use
void *context;
and we convert it in the platform specific handler, then this struct
can be reused for other type of quirks.
> +};
> +
> +/* note: this needs to be updated according to the doc of OEM ID
> + * and TABLE ID for different board.
> + */
> +struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = {
> +};
> +
> +void __init arch_timer_acpi_quirks_handler(char *oem_id,
> + char *oem_table_id,
> + u32 oem_revision)
> +{
> + struct gtdt_arch_timer_fixup *quirks = arch_timer_quirks;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(arch_timer_quirks); i++, quirks++) {
> + if (!memcmp(quirks->oem_id, oem_id, ACPI_OEM_ID_SIZE) &&
> + !memcmp(quirks->oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
> + quirks->oem_revision == oem_revision) {
> + if (quirks->handler && quirks->erratum)
> + quirks->handler(quirks->erratum);
> + break;
we can't just break because we have multi quirks for different handlers.
Thanks
Hanjun
^ permalink raw reply
* [RESEND PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters
From: Anurup M @ 2016-11-14 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161110191058.GE10137@leverpostej>
On Friday 11 November 2016 12:40 AM, Mark Rutland wrote:
> On Thu, Nov 03, 2016 at 01:42:03AM -0400, Anurup M wrote:
>> + do {
>> + /* Get count from individual L3C banks and sum them up */
>> + for (i = 0; i < num_banks; i++) {
>> + total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data,
>> + idx, i);
>> + }
>> + prev_raw_count = local64_read(&hwc->prev_count);
>> +
>> + /*
>> + * As prev_raw_count is updated with average value of
>> + * L3 cache banks, we multiply it by no of banks and
>> + * compute the delta
>> + */
>> + delta = (total_raw_count - (prev_raw_count * num_banks)) &
>> + HISI_MAX_PERIOD;
>> +
>> + local64_add(delta, &event->count);
>> +
>> + /*
>> + * Divide by num of banks to get average count and
>> + * update prev_count with this value
>> + */
>> + avg_raw_count = total_raw_count / num_banks;
>> + } while (local64_cmpxchg(
>> + &hwc->prev_count, prev_raw_count, avg_raw_count) !=
>> + prev_raw_count);
> Please don't aggregate like this; expose separate PMUs instead.
>
> This is racy, and by averaging and multiplying we're making up and/or
> throwing away data.
>
> [...]
I have some concerns or doubts regarding registering each L3 cache bank
as a separate PMU.
1) Each L3 cache PMU has total 22 statistics events. So if registered as
a separate PMU, will it not
create multiple entries (with same event names) in event listing for
multiple PMU's. Is there a way
I can avoid this? or this is acceptable?
Or is it acceptable to register as a single PMU and add a config
parameter in the event listing to
identify the L3 cache bank. ex: event name will appear as
"hisi_l3c2/read_allocate,bank=?/".
And user can choose count from bank 0x01 as -e
"hisi_l3c2/read_allocate,bank=0x01/"
2) The individual count from each L3 cache bank is not meaningful. Only
aggregate count is useful.
Which is the accepted way to handle such counters?
a) Register each PMU instance as in hardware and handle the aggregation
in user space.
b) Register as single PMU, handle aggregation in driver.
>> + event_value = (val -
>> + HISI_HWEVENT_L3C_READ_ALLOCATE);
>> +
>> + /* Select the appropriate Event select register */
>> + if (idx > 3)
>> + reg_offset += 4;
>> +
>> + /* Value to write to event type register */
>> + val = event_value << (8 * idx);
>> +
> Please add helpers for these, and explain *why* the transformations are
> necessary.
Ok. shall add helpers.
>> + /* Find the djtag Identifier of the Unit */
>> + client = l3c_hwmod_data->client;
>> +
>> + /*
>> + * Set the event in L3C_EVENT_TYPEx Register
>> + * for all L3C banks
>> + */
> As above, it seems like you should expose a separate PMU per bank
> instead. That applies for all the other instances where you iterate over
> banks.
>
> [...]
>
>> + for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
>> + module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
>> + cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
>> + ret = hisi_djtag_writereg(module_id,
>> + cfg_en,
>> + reg_offset,
>> + value,
>> + client);
>> + if (!ret)
>> + ret = value;
>> + }
> This is impossible to read. Please factor this into helpers such that
> you don't need this amount of indentation.
>
> Please do similarly elsewhere when you see this indentation pattern.
OK.
> [...]
>
>> +static int hisi_l3c_get_event_idx(struct hisi_pmu *pl3c_pmu)
>> +{
>> + struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
>> + int event_idx;
>> +
>> + event_idx =
>> + find_first_zero_bit(
>> + l3c_hwmod_data->hisi_l3c_event_used_mask,
>> + pl3c_pmu->num_counters);
>> +
>> + if (event_idx == HISI_MAX_CFG_L3C_CNTR)
>> + return -EAGAIN;
>> +
>> + __set_bit(event_idx,
>> + l3c_hwmod_data->hisi_l3c_event_used_mask);
>> +
>> + return event_idx;
>> +}
> Please get rid of the weird hungarian notation (i.e. don't use 'p' as a
> prefix for pointers), and use temporary variables consistently, e.g.
Ok.
> static int hisi_l3c_get_event_idx(struct hisi_pmu *l3c_pmu)
> {
> struct hisi_l3c_data *l3c_hwmod_data = l3c_pmu->hwmod_data;
> unsigned long *used_mask = l3c_hwmod_data->hisi_l3c_event_used_mask;
> int num_counters = pl3c_pmu->num_counters
> int idx;
>
> idx = find_first_zero_bit(used_mask, num_counters);
> if (idx == num_counters)
> return -EAGAIN;
>
> set_bit(idx, used_mask);
>
> return idx;
> }
>
> [...]
>
>> + if (of_property_read_u32(node, "counter-reg",
>> + &pl3c_hwcfg->counter_reg0_off)) {
>> + dev_err(dev, "DT:Couldnot read counter-reg!\n");
>> + return -EINVAL;
>> + }
> Please use spaces in these messages.
>
> Otherwise, my comments on the binding apply here.
>
> [...]
>
>> +static int init_hisi_l3c_data(struct device *dev,
>> + struct hisi_pmu *pl3c_pmu,
>> + struct hisi_djtag_client *client)
>> +{
>> + struct hisi_l3c_data *l3c_hwmod_data = NULL;
>> + int ret;
>> +
>> + l3c_hwmod_data = kzalloc(sizeof(struct hisi_l3c_data),
>> + GFP_KERNEL);
> Use:
>
> l3c_hwmod_data = kzalloc(sizeof(*l3c_hwmod_data, GFP_KERNEL):
>
> [...]
Ok.
>> +static int hisi_pmu_l3c_dev_probe(struct hisi_djtag_client *client)
>> +{
>> + struct hisi_pmu *pl3c_pmu = NULL;
>> + struct device *dev = &client->dev;
>> + int ret;
>> +
>> + pl3c_pmu = hisi_pmu_alloc(dev);
>> + if (IS_ERR(pl3c_pmu))
>> + return PTR_ERR(pl3c_pmu);
> Why use error pointers for this?
>
> hisi_pmu_alloc() only ever returns ERR_PTR(-ENOMEM) if it failed to
> allocate.
>
> It's far simpler to have it pass on NULL there, and here do:
>
> pl3c_pmu = hisi_pmu_alloc(dev);
> if (!pl3c_pmu)
> return -ENOMEM;
>
> Please also s/pl3c_pmu/l3c_pmu/ here, and elsewhere throughout the
> driver. The 'p' only serves to make this harder to read.
>
> [...]
Ok.
>> + /* Register with perf PMU */
>> + pl3c_pmu->pmu = (struct pmu) {
>> + .name = pl3c_pmu->name,
>> + .task_ctx_nr = perf_invalid_context,
>> + .event_init = hisi_uncore_pmu_event_init,
>> + .add = hisi_uncore_pmu_add,
>> + .del = hisi_uncore_pmu_del,
>> + .start = hisi_uncore_pmu_start,
>> + .stop = hisi_uncore_pmu_stop,
>> + .read = hisi_uncore_pmu_read,
>> + };
> Please remove the comment above this.
>
> [...]
Ok.
>> +int hisi_uncore_pmu_event_init(struct perf_event *event)
>> +{
>> + int err;
>> + struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
> This is undefined behaviour. This must be done *after* we check the
> event->pmu->type.
Ok. shall move it after the check.
>> +
>> + if (event->attr.type != event->pmu->type)
>> + return -ENOENT;
>> +
>> + /* we do not support sampling as the counters are all
>> + * shared by all CPU cores in a CPU die(SCCL). Also we
>> + * donot support attach to a task(per-process mode)
>> + */
>> + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
>> + return -EOPNOTSUPP;
>> +
>> + /* counters do not have these bits */
>> + if (event->attr.exclude_user ||
>> + event->attr.exclude_kernel ||
>> + event->attr.exclude_host ||
>> + event->attr.exclude_guest ||
>> + event->attr.exclude_hv ||
>> + event->attr.exclude_idle)
>> + return -EINVAL;
>> +
>> + if (event->cpu < 0)
>> + return -EINVAL;
>> +
>> + event->cpu = cpumask_first(&phisi_pmu->cpu);
> You should also check the event grouping.
>
> Take a look at what we do in arch/arm/mm/cache-l2x0-pmu.c.
>
> [...]
>
Ok. I got it. Thanks for the reference.
As you had suggested earlier I am thinking to put all these checks to a
common lib function
and every uncore driver can call it.
Where can it be placed in source tree? Please suggest. shall add it.
>> +/*
>> + * Enable counter and set the counter to count
>> + * the event that we're interested in.
>> + */
>> +void hisi_uncore_pmu_enable_event(struct perf_event *event)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
>> +
>> + /* Disable the hardware event counting */
>> + if (phisi_pmu->ops->disable_counter)
>> + phisi_pmu->ops->disable_counter(phisi_pmu, GET_CNTR_IDX(hwc));
> Why isn't the counter already disabled?
>
In Hisilicon SoC PMU for L3C, MN etc, the hip05/06/07 chips don't have
support for
stop/start individual counters.
The steps to start counting are
1) Stop counting(global control) in L3 cache AUCTRL register.
2) set event type in the event type register (Event code written to
3) Start counting (global control) in L3 cache AUCTRL register.
>> + /*
>> + * Set event (if destined for Hisilicon SoC counters).
>> + */
>> + if (phisi_pmu->ops->set_evtype)
>> + phisi_pmu->ops->set_evtype(phisi_pmu, GET_CNTR_IDX(hwc),
>> + hwc->config_base);
> Why isn't this done in the pmu::event_add callback?
hisi_uncore_pmu_enable_event is called by pmu::event_add.
The Call flow is pmu::event_add (hisi_uncore_pmu_add) -->
hisi_uncore_pmu_start --> hisi_uncore_pmu_enable_event
>> +
>> + /* Enable the hardware event counting */
>> + if (phisi_pmu->ops->enable_counter)
>> + phisi_pmu->ops->enable_counter(phisi_pmu, GET_CNTR_IDX(hwc));
> This should be the only necessary part of this function.
>
>> +}
>> +
>> +void hisi_pmu_set_event_period(struct perf_event *event)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
>> +
>> + /*
>> + * The Hisilicon PMU counters have a period of 2^32. To account for the
>> + * possiblity of extreme interrupt latency we program for a period of
>> + * half that. Hopefully we can handle the interrupt before another 2^31
>> + * events occur and the counter overtakes its previous value.
>> + */
>> + u64 val = 1ULL << 31;
>> +
>> + local64_set(&hwc->prev_count, val);
>> +
>> + /* Write to the hardware event counter */
>> + phisi_pmu->ops->write_counter(phisi_pmu, hwc, val);
>> +}
>> +
>> +void hisi_uncore_pmu_start(struct perf_event *event, int flags)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
>> + struct hisi_pmu_hw_events *hw_events;
>> +
>> + hw_events = &phisi_pmu->hw_events;
>> +
>> + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
>> + return;
>> +
>> + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
>> + hwc->state = 0;
>> +
>> + if (phisi_pmu->ops->set_event_period)
>> + phisi_pmu->ops->set_event_period(event);
> When will this differ from hisi_pmu_set_event_period() above?
On some chips like hip05 and 06, the counter overflow handling with IRQ
cannot
be supported as the Hisilicon Mbigen V1 driver cannot be upstream. So I
am thinking
to have the counters start with value 0 and handle overflow with a poll
method from
a hrtimer. So this method (hisi_pmu::set_event_period) could be changed
in hisi_uncore(l3c/mn/ddrc).c.
Also for the DDRC PMU, the method (hisi_pmu::set_event_period) override
to handle continous counting.
In DDRC PMU, the initial counter value start from 0.
Please share your comments.
>> + if (flags & PERF_EF_RELOAD) {
>> + u64 prev_raw_count = local64_read(&hwc->prev_count);
>> +
>> + phisi_pmu->ops->write_counter(phisi_pmu, hwc,
>> + (u32)prev_raw_count);
>> + }
> If we always go through hisi_pmu_set_event_period(), this looks
> redundant.
>
>> +
>> + hisi_uncore_pmu_enable_event(event);
> There's no matching disable_event() call in this function, so this looks
> suspicious.
>
The hisi_uncore_pmu_enable_event includes
1) disable counting
2) set event type
3) enable counting
Sorry. I think this lead to confusion.
I shall split then to separate functions
a) disable_counter
b) set_event_type
c) enable_counter
>> + perf_event_update_userpage(event);
>> +}
>> +
>> +void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
>> +{
>> + struct hw_perf_event *hwc = &event->hw;
>> + struct hisi_pmu *phisi_pmu = to_hisi_pmu(event->pmu);
>> +
>> + if (hwc->state & PERF_HES_UPTODATE)
>> + return;
> Why?
A mistake. Will remove it.
> [...]
>
>> +int hisi_uncore_common_fwprop_read(struct device *dev,
>> + struct hisi_pmu *phisi_pmu)
>> +{
>> + if (device_property_read_u32(dev, "num-events",
>> + &phisi_pmu->num_events)) {
>> + dev_err(dev, "Cant read num-events from DT!\n");
>> + return -EINVAL;
>> + }
> For consistency with the rest of the driver, and given there is no ACPI
> support, please use the of_property_* API here.
Ok.
Thanks,
Anurup
> Thanks,
> Mark.
^ permalink raw reply
* [PATCH v9 00/10] MT2701 DRM support
From: Bibby Hsieh @ 2016-11-14 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478865346-19043-1-git-send-email-yt.shen@mediatek.com>
Hi, YT
On Fri, 2016-11-11 at 19:55 +0800, YT Shen wrote:
> This is MT2701 DRM support PATCH v9, based on 4.9-rc1.
> We add DSI interrupt control, transfer function for MIPI DSI panel support.
> Most codes are the same, except some register changed.
>
> For example:
> - DISP_OVL address offset changed, color format definition changed.
> - DISP_RDMA fifo size changed.
> - DISP_COLOR offset changed.
> - MIPI_TX setting changed.
>
> We add a new component DDP_COMPONENT_BLS, and the connections are updated.
> OVL -> RDMA -> COLOR -> BLS -> DSI
> RDMA -> DPI
> And we have shadow register support in MT2701.
>
> We remove dts patch from the patch series, which depends on MT2701 CCF and scpsys.
>
I test this series on MT8173 platform, it looks pretty good to me,
thanks for your patches.
Tested-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Changes since v8:
> - enable 3 DSI interrupts only
> - move mtk_dsi_wait_for_irq_done() to the patch of irq control
> - use the name BLS in DRM driver part
> - move BLS declaration to a separate patch
> - update mtk_dsi_switch_to_cmd_mode()
> - update mtk_output_dsi_enable() and mtk_output_dsi_disable()
>
> Changes since v7:
> - Remove redundant codes
> - Move the definition of DDP_COMPONENT_BLS to patch of "drm/mediatek: update display module connections"
> - Move _dsi_irq_wait_queue into platform driver data
> - Move mtk_dsi_irq_data_clear() to patch of "drm/mediatek: add dsi interrupt control"
> - Add more descriptions in the commit messages
>
> Changes since v6:
> - Change data type of irq_data to u32
> - Rewrite mtk_dsi_host_transfer() for simplify
> - Move some MIPI_TX config to patch of "drm/mediatek: add *driver_data for different hardware settings".
> - Remove device tree from this patch series
>
> Changes since v5:
> - Remove DPI device tree and compatible string
> - Use one wait queue to handle interrupt status
> - Update the interrupt check flow and DSI_INT_ALL_BITS
> - Use same function for host read/write command
> - various fixes
>
> Changes since v4:
> - Add messages when timeout in mtk_disp_mutex_acquire()
> - Add descriptions for DISP_REG_MUTEX registers
> - Move connection settings for display modules to a separate patch
> - Remove 'mt2701-disp-wdma' because it is unused
> - Move cleaning up and renaming to a separate patch
> - Use wait_event_interruptible_timeout() to replace polling
> - Remove irq_num from mtk_dsi structure
> - Remove redundant and debug codes
>
> Changes since v3:
> - Add DSI support for MIPI DSI panels
> - Update BLS binding to PWM nodes
> - Remove ufoe device nodes
> - Remove redundant parentheses
> - Remove global variable initialization
>
> Changes since v2:
> - Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
> - Update mt2701_mtk_ddp_ext components
> - Changed to prefix naming
> - Reorder the patch series
> - Use of_device_get_match_data() to get driver private data
> - Use iopoll macros to implement mtk_disp_mutex_acquire()
> - Removed empty device tree nodes
>
> Changes since v1:
> - Removed BLS bindings and codes, which belong to pwm driver
> - Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
> - Split patch into smaller parts
> - Added const keyword to constant structure
> - Removed codes for special memory align
>
> Thanks,
> yt.shen
>
> YT Shen (8):
> drm/mediatek: rename macros, add chip prefix
> drm/mediatek: add *driver_data for different hardware settings
> drm/mediatek: add shadow register support
> drm/mediatek: add BLS component
> drm/mediatek: update display module connections
> drm/mediatek: cleaning up and refine
> drm/mediatek: update DSI sub driver flow for sending commands to panel
> drm/mediatek: add support for Mediatek SoC MT2701
>
> shaoming chen (2):
> drm/mediatek: add dsi interrupt control
> drm/mediatek: add dsi transfer function
>
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 ++-
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 17 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 76 +++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 138 ++++++---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 38 ++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 54 +++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +
> drivers/gpu/drm/mediatek/mtk_dsi.c | 429 ++++++++++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 70 +++--
> 11 files changed, 715 insertions(+), 166 deletions(-)
>
--
Bibby
^ permalink raw reply
* [PATCH] ARM: dts: imx: Remove skeleton.dtsi
From: Shawn Guo @ 2016-11-14 7:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478964635-12298-1-git-send-email-festevam@gmail.com>
On Sat, Nov 12, 2016 at 01:30:35PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> As explained by commit 9c0da3cc61f1233c ("ARM: dts: explicitly mark
> skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated.
>
> This fixes the following warning with W=1:
>
> Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6q-cm-fx6: fix fec pinctrl
From: Shawn Guo @ 2016-11-14 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6cd823201b9f4cde8de8eddc910f39ce@rwthex-s1-b.rwth-ad.de>
On Fri, Nov 11, 2016 at 04:59:38PM +0100, christopher.spinrath at rwth-aachen.de wrote:
> From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
>
> According to the schematics of CompuLab's sbc-fx6 baseboard and the
> vendor devicetree GPIO_16 is *not* muxed to ENET_REF_CLK but to SPDIF_IN.
>
> Remove the wrong pinctrl setting.
>
> Fixes: 682d055e6ac5 ("ARM: dts: Add initial support for cm-fx6.")
> Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Applied both, thanks.
^ permalink raw reply
* [PATCH v9 00/10] MT2701 DRM support
From: CK Hu @ 2016-11-14 7:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478865346-19043-1-git-send-email-yt.shen@mediatek.com>
Hi, YT:
On Fri, 2016-11-11 at 19:55 +0800, YT Shen wrote:
> This is MT2701 DRM support PATCH v9, based on 4.9-rc1.
> We add DSI interrupt control, transfer function for MIPI DSI panel support.
> Most codes are the same, except some register changed.
>
> For example:
> - DISP_OVL address offset changed, color format definition changed.
> - DISP_RDMA fifo size changed.
> - DISP_COLOR offset changed.
> - MIPI_TX setting changed.
>
> We add a new component DDP_COMPONENT_BLS, and the connections are updated.
> OVL -> RDMA -> COLOR -> BLS -> DSI
> RDMA -> DPI
> And we have shadow register support in MT2701.
>
> We remove dts patch from the patch series, which depends on MT2701 CCF and scpsys.
For this series, it looks good to me.
Acked-by: CK Hu <ck.hu@mediatek.com>
>
> Changes since v8:
> - enable 3 DSI interrupts only
> - move mtk_dsi_wait_for_irq_done() to the patch of irq control
> - use the name BLS in DRM driver part
> - move BLS declaration to a separate patch
> - update mtk_dsi_switch_to_cmd_mode()
> - update mtk_output_dsi_enable() and mtk_output_dsi_disable()
>
> Changes since v7:
> - Remove redundant codes
> - Move the definition of DDP_COMPONENT_BLS to patch of "drm/mediatek: update display module connections"
> - Move _dsi_irq_wait_queue into platform driver data
> - Move mtk_dsi_irq_data_clear() to patch of "drm/mediatek: add dsi interrupt control"
> - Add more descriptions in the commit messages
>
> Changes since v6:
> - Change data type of irq_data to u32
> - Rewrite mtk_dsi_host_transfer() for simplify
> - Move some MIPI_TX config to patch of "drm/mediatek: add *driver_data for different hardware settings".
> - Remove device tree from this patch series
>
> Changes since v5:
> - Remove DPI device tree and compatible string
> - Use one wait queue to handle interrupt status
> - Update the interrupt check flow and DSI_INT_ALL_BITS
> - Use same function for host read/write command
> - various fixes
>
> Changes since v4:
> - Add messages when timeout in mtk_disp_mutex_acquire()
> - Add descriptions for DISP_REG_MUTEX registers
> - Move connection settings for display modules to a separate patch
> - Remove 'mt2701-disp-wdma' because it is unused
> - Move cleaning up and renaming to a separate patch
> - Use wait_event_interruptible_timeout() to replace polling
> - Remove irq_num from mtk_dsi structure
> - Remove redundant and debug codes
>
> Changes since v3:
> - Add DSI support for MIPI DSI panels
> - Update BLS binding to PWM nodes
> - Remove ufoe device nodes
> - Remove redundant parentheses
> - Remove global variable initialization
>
> Changes since v2:
> - Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
> - Update mt2701_mtk_ddp_ext components
> - Changed to prefix naming
> - Reorder the patch series
> - Use of_device_get_match_data() to get driver private data
> - Use iopoll macros to implement mtk_disp_mutex_acquire()
> - Removed empty device tree nodes
>
> Changes since v1:
> - Removed BLS bindings and codes, which belong to pwm driver
> - Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
> - Split patch into smaller parts
> - Added const keyword to constant structure
> - Removed codes for special memory align
>
> Thanks,
> yt.shen
>
> YT Shen (8):
> drm/mediatek: rename macros, add chip prefix
> drm/mediatek: add *driver_data for different hardware settings
> drm/mediatek: add shadow register support
> drm/mediatek: add BLS component
> drm/mediatek: update display module connections
> drm/mediatek: cleaning up and refine
> drm/mediatek: update DSI sub driver flow for sending commands to panel
> drm/mediatek: add support for Mediatek SoC MT2701
>
> shaoming chen (2):
> drm/mediatek: add dsi interrupt control
> drm/mediatek: add dsi transfer function
>
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 ++-
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 17 +-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 76 +++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 138 ++++++---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 38 ++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 15 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 54 +++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +
> drivers/gpu/drm/mediatek/mtk_dsi.c | 429 ++++++++++++++++++++++++----
> drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 70 +++--
> 11 files changed, 715 insertions(+), 166 deletions(-)
>
^ permalink raw reply
* [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Shawn Guo @ 2016-11-14 7:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1478715118-12848-1-git-send-email-harninder.rai@nxp.com>
On Wed, Nov 09, 2016 at 11:41:58PM +0530, Harninder Rai wrote:
> Add the device tree support for FSL LS1012A SoC.
Can we have a brief introduction of this SoC in commit log?
> Following levels of DTSI/DTS files have been created for the LS1012A
> SoC family:
>
> - fsl-ls1012a.dtsi:
> DTS-Include file for FSL LS1012A SoC.
>
> - fsl-ls1012a-frdm.dts:
> DTS file for FSL LS1012A FRDM board.
>
> - fsl-ls1012a-qds.dts:
> DTS file for FSL LS1012A QDS board.
>
> - fsl-ls1012a-rdb.dts:
> DTS file for FSL LS1012A RDB board.
>
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 3 +
> arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 248 +++++++++++++++++++++
> 5 files changed, 553 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 6602718..39db645 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,3 +1,6 @@
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
It seems that the patch is not generated against mainline kernel. We do
not have fsl-ls1046a-qds.dtb target in mainline kernel.
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> new file mode 100644
> index 0000000..1f2da79
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> @@ -0,0 +1,115 @@
> +/*
> + * Device Tree file for Freescale LS1012A Freedom Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A Freedom Board";
> + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
> +
> + sys_mclk: clock-mclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + reg_1p8v: regulator at 0 {
Drop the unit-address from node name, and name it like regulator-1p8v.
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Speaker", "Speaker Ext",
> + "Line", "Line In Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Microphone Jack",
> + "Microphone Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT",
> + "Speaker Ext", "LINE_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + frame-master;
> + bitclock-master;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&codec>;
> + frame-master;
> + bitclock-master;
> + system-clock-frequency = <25000000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + codec: sgtl5000 at a {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,sgtl5000";
> + reg = <0xa>;
> + VDDA-supply = <®_1p8v>;
> + VDDIO-supply = <®_1p8v>;
> + clocks = <&sys_mclk>;
> + };
> +};
> +
> +&duart0 {
Please sort labeled nodes alphabetically.
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
<snip>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> new file mode 100644
> index 0000000..0bf5b64
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> @@ -0,0 +1,248 @@
> +/*
> + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "fsl,ls1012a";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Physical Secure PPI */
> + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> + /* Physical Non-Secure PPI */
> + <1 14 IRQ_TYPE_LEVEL_LOW>,
> + /* Virtual PPI */
> + <1 11 IRQ_TYPE_LEVEL_LOW>,
> + /* Hypervisor PPI */
> + <1 10 IRQ_TYPE_LEVEL_LOW>;
The following form should be easier for read.
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure PPI */
<1 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure PPI */
<1 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual PPI */
<1 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor PPI */
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <0 106 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + gic: interrupt-controller at 1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x2000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + reboot {
> + compatible = "syscon-reboot";
> + regmap = <&dcfg>;
> + offset = <0xb0>;
> + mask = <0x02>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking at 1ee1000 {
> + compatible = "fsl,ls1012a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + };
> +
> + scfg: scfg at 1570000 {
> + compatible = "fsl,ls1012a-scfg", "syscon";
> + reg = <0x0 0x1570000 0x0 0x10000>;
> + big-endian;
> + };
Please sort these nodes with unit-address in order of the address.
Shawn
> +
> + dcfg: dcfg at 1ee0000 {
> + compatible = "fsl,ls1012a-dcfg",
> + "syscon";
> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> + big-endian;
> + };
> +
> + i2c0: i2c at 2180000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2180000 0x0 0x10000>;
> + interrupts = <0 56 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 2190000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2190000 0x0 0x10000>;
> + interrupts = <0 57 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + duart0: serial at 21c0500 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0500 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + duart1: serial at 21c0600 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0600 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + gpio0: gpio at 2300000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <0 66 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio at 2310000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2310000 0x0 0x10000>;
> + interrupts = <0 67 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + wdog0: wdog at 2ad0000 {
> + compatible = "fsl,ls1012a-wdt",
> + "fsl,imx21-wdt";
> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> + interrupts = <0 83 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + big-endian;
> + };
> +
> + sai1: sai at 2b50000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b50000 0x0 0x10000>;
> + interrupts = <0 148 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 47>,
> + <&edma0 1 46>;
> + status = "disabled";
> + };
> +
> + sai2: sai at 2b60000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b60000 0x0 0x10000>;
> + interrupts = <0 149 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 45>,
> + <&edma0 1 44>;
> + status = "disabled";
> + };
> +
> + edma0: edma at 2c00000 {
> + #dma-cells = <2>;
> + compatible = "fsl,vf610-edma";
> + reg = <0x0 0x2c00000 0x0 0x10000>,
> + <0x0 0x2c10000 0x0 0x10000>,
> + <0x0 0x2c20000 0x0 0x10000>;
> + interrupts = <0 103 IRQ_TYPE_LEVEL_LOW>,
> + <0 103 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "edma-tx", "edma-err";
> + dma-channels = <32>;
> + big-endian;
> + clock-names = "dmamux0", "dmamux1";
> + clocks = <&clockgen 4 3>,
> + <&clockgen 4 3>;
> + };
> +
> + sata: sata at 3200000 {
> + compatible = "fsl,ls1012a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>;
> + interrupts = <0 69 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + };
> + };
> +};
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2 6/6] mm: hugetlb: support gigantic surplus pages
From: Huang Shijie @ 2016-11-14 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107259-2011-1-git-send-email-shijie.huang@arm.com>
When testing the gigantic page whose order is too large for the buddy
allocator, the libhugetlbfs test case "counter.sh" will fail.
The failure is caused by:
1) kernel fails to allocate a gigantic page for the surplus case.
And the gather_surplus_pages() will return NULL in the end.
2) The condition checks for "over-commit" is wrong.
This patch uses __hugetlb_alloc_gigantic_page() to allocate the
gigantic page in the __alloc_huge_page(). After this patch,
gather_surplus_pages() can return a gigantic page for the surplus case.
This patch also changes the condition checks for:
return_unused_surplus_pages()
nr_overcommit_hugepages_store()
hugetlb_overcommit_handler()
After this patch, the counter.sh can pass for the gigantic page.
Signed-off-by: Huang Shijie <shijie.huang@arm.com>
---
mm/hugetlb.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 58a59f0..08e66ca 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -1647,7 +1647,7 @@ static struct page *__alloc_huge_page(struct hstate *h,
struct page *page;
unsigned int r_nid;
- if (hstate_is_gigantic(h))
+ if (hstate_is_gigantic(h) && !gigantic_page_supported())
return NULL;
/*
@@ -1692,7 +1692,10 @@ static struct page *__alloc_huge_page(struct hstate *h,
}
spin_unlock(&hugetlb_lock);
- page = __hugetlb_alloc_buddy_huge_page(h, vma, addr, nid);
+ if (hstate_is_gigantic(h))
+ page = __hugetlb_alloc_gigantic_page(h, vma, addr, nid);
+ else
+ page = __hugetlb_alloc_buddy_huge_page(h, vma, addr, nid);
spin_lock(&hugetlb_lock);
if (page) {
@@ -1859,8 +1862,7 @@ static void return_unused_surplus_pages(struct hstate *h,
/* Uncommit the reservation */
h->resv_huge_pages -= unused_resv_pages;
- /* Cannot return gigantic pages currently */
- if (hstate_is_gigantic(h))
+ if (hstate_is_gigantic(h) && !gigantic_page_supported())
return;
nr_pages = min(unused_resv_pages, h->surplus_huge_pages);
@@ -2577,7 +2579,7 @@ static ssize_t nr_overcommit_hugepages_store(struct kobject *kobj,
unsigned long input;
struct hstate *h = kobj_to_hstate(kobj, NULL);
- if (hstate_is_gigantic(h))
+ if (hstate_is_gigantic(h) && !gigantic_page_supported())
return -EINVAL;
err = kstrtoul(buf, 10, &input);
@@ -3018,7 +3020,7 @@ int hugetlb_overcommit_handler(struct ctl_table *table, int write,
tmp = h->nr_overcommit_huge_pages;
- if (write && hstate_is_gigantic(h))
+ if (write && hstate_is_gigantic(h) && !gigantic_page_supported())
return -EINVAL;
table->data = &tmp;
--
2.5.5
^ permalink raw reply related
* [PATCH v2 5/6] mm: hugetlb: add a new function to allocate a new gigantic page
From: Huang Shijie @ 2016-11-14 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107259-2011-1-git-send-email-shijie.huang@arm.com>
There are three ways we can allocate a new gigantic page:
1. When the NUMA is not enabled, use alloc_gigantic_page() to get
the gigantic page.
2. The NUMA is enabled, but the vma is NULL.
There is no memory policy we can refer to.
So create a @nodes_allowed, initialize it with init_nodemask_of_mempolicy()
or init_nodemask_of_node(). Then use alloc_fresh_gigantic_page() to get
the gigantic page.
3. The NUMA is enabled, and the vma is valid.
We can follow the memory policy of the @vma.
Get @nodes_mask by huge_nodemask(), and use alloc_fresh_gigantic_page()
to get the gigantic page.
Signed-off-by: Huang Shijie <shijie.huang@arm.com>
---
mm/hugetlb.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 6995087..58a59f0 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -1502,6 +1502,73 @@ int dissolve_free_huge_pages(unsigned long start_pfn, unsigned long end_pfn)
/*
* There are 3 ways this can get called:
+ *
+ * 1. When the NUMA is not enabled, use alloc_gigantic_page() to get
+ * the gigantic page.
+ *
+ * 2. The NUMA is enabled, but the vma is NULL.
+ * Create a @nodes_allowed, use alloc_fresh_gigantic_page() to get
+ * the gigantic page.
+ *
+ * 3. The NUMA is enabled, and the vma is valid.
+ * Use the @vma's memory policy.
+ * Get @nodes_mask by huge_nodemask(), and use alloc_fresh_gigantic_page()
+ * to get the gigantic page.
+ */
+static struct page *__hugetlb_alloc_gigantic_page(struct hstate *h,
+ struct vm_area_struct *vma, unsigned long addr, int nid)
+{
+ struct page *page;
+ nodemask_t *nodes_mask;
+
+ /* Not NUMA */
+ if (!IS_ENABLED(CONFIG_NUMA)) {
+ if (nid == NUMA_NO_NODE)
+ nid = numa_mem_id();
+
+ page = alloc_gigantic_page(nid, huge_page_order(h));
+ if (page)
+ prep_compound_gigantic_page(page, huge_page_order(h));
+
+ return page;
+ }
+
+ /* NUMA && !vma */
+ if (!vma) {
+ NODEMASK_ALLOC(nodemask_t, nodes_allowed,
+ GFP_KERNEL | __GFP_NORETRY);
+
+ if (nid == NUMA_NO_NODE) {
+ if (!init_nodemask_of_mempolicy(nodes_allowed)) {
+ NODEMASK_FREE(nodes_allowed);
+ nodes_allowed = &node_states[N_MEMORY];
+ }
+ } else if (nodes_allowed) {
+ init_nodemask_of_node(nodes_allowed, nid);
+ } else {
+ nodes_allowed = &node_states[N_MEMORY];
+ }
+
+ page = alloc_fresh_gigantic_page(h, nodes_allowed, true);
+
+ if (nodes_allowed != &node_states[N_MEMORY])
+ NODEMASK_FREE(nodes_allowed);
+
+ return page;
+ }
+
+ /* NUMA && vma */
+ nodes_mask = huge_nodemask(vma, addr);
+ if (nodes_mask) {
+ page = alloc_fresh_gigantic_page(h, nodes_mask, true);
+ if (page)
+ return page;
+ }
+ return NULL;
+}
+
+/*
+ * There are 3 ways this can get called:
* 1. With vma+addr: we use the VMA's memory policy
* 2. With !vma, but nid=NUMA_NO_NODE: We try to allocate a huge
* page from any node, and let the buddy allocator itself figure
--
2.5.5
^ permalink raw reply related
* [PATCH v2 4/6] mm: mempolicy: intruduce a helper huge_nodemask()
From: Huang Shijie @ 2016-11-14 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107259-2011-1-git-send-email-shijie.huang@arm.com>
This patch intruduces a new helper huge_nodemask(),
we can use it to get the node mask.
This idea of the function is from the huge_zonelist().
Signed-off-by: Huang Shijie <shijie.huang@arm.com>
---
include/linux/mempolicy.h | 8 ++++++++
mm/mempolicy.c | 20 ++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 5e5b296..01173c6 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -145,6 +145,8 @@ extern void mpol_rebind_task(struct task_struct *tsk, const nodemask_t *new,
enum mpol_rebind_step step);
extern void mpol_rebind_mm(struct mm_struct *mm, nodemask_t *new);
+extern nodemask_t *huge_nodemask(struct vm_area_struct *vma,
+ unsigned long addr);
extern struct zonelist *huge_zonelist(struct vm_area_struct *vma,
unsigned long addr, gfp_t gfp_flags,
struct mempolicy **mpol, nodemask_t **nodemask);
@@ -261,6 +263,12 @@ static inline void mpol_rebind_mm(struct mm_struct *mm, nodemask_t *new)
{
}
+static inline nodemask_t *huge_nodemask(struct vm_area_struct *vma,
+ unsigned long addr)
+{
+ return NULL;
+}
+
static inline struct zonelist *huge_zonelist(struct vm_area_struct *vma,
unsigned long addr, gfp_t gfp_flags,
struct mempolicy **mpol, nodemask_t **nodemask)
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index 6d3639e..4830dd6 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1800,6 +1800,26 @@ static inline unsigned interleave_nid(struct mempolicy *pol,
#ifdef CONFIG_HUGETLBFS
/*
+ * huge_nodemask(@vma, @addr)
+ * @vma: virtual memory area whose policy is sought
+ * @addr: address in @vma for shared policy lookup and interleave policy
+ *
+ * If the effective policy is BIND, returns a pointer to the mempolicy's
+ * @nodemask.
+ */
+nodemask_t *huge_nodemask(struct vm_area_struct *vma, unsigned long addr)
+{
+ nodemask_t *nodes_mask = NULL;
+ struct mempolicy *mpol = get_vma_policy(vma, addr);
+
+ if (mpol->mode == MPOL_BIND)
+ nodes_mask = &mpol->v.nodes;
+ mpol_cond_put(mpol);
+
+ return nodes_mask;
+}
+
+/*
* huge_zonelist(@vma, @addr, @gfp_flags, @mpol)
* @vma: virtual memory area whose policy is sought
* @addr: address in @vma for shared policy lookup and interleave policy
--
2.5.5
^ permalink raw reply related
* [PATCH v2 3/6] mm: hugetlb: change the return type for alloc_fresh_gigantic_page
From: Huang Shijie @ 2016-11-14 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479107259-2011-1-git-send-email-shijie.huang@arm.com>
This patch changes the return type to "struct page*" for
alloc_fresh_gigantic_page().
This patch makes preparation for later patch.
Signed-off-by: Huang Shijie <shijie.huang@arm.com>
---
mm/hugetlb.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index db0177b..6995087 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -1142,7 +1142,7 @@ static struct page *alloc_fresh_gigantic_page_node(struct hstate *h,
return page;
}
-static int alloc_fresh_gigantic_page(struct hstate *h,
+static struct page *alloc_fresh_gigantic_page(struct hstate *h,
nodemask_t *nodes_allowed, bool no_init)
{
struct page *page = NULL;
@@ -1151,10 +1151,10 @@ static int alloc_fresh_gigantic_page(struct hstate *h,
for_each_node_mask_to_alloc(h, nr_nodes, node, nodes_allowed) {
page = alloc_fresh_gigantic_page_node(h, node, no_init);
if (page)
- return 1;
+ return page;
}
- return 0;
+ return NULL;
}
static inline bool gigantic_page_supported(void) { return true; }
@@ -1167,8 +1167,8 @@ static inline bool gigantic_page_supported(void) { return false; }
static inline void free_gigantic_page(struct page *page, unsigned int order) { }
static inline void destroy_compound_gigantic_page(struct page *page,
unsigned int order) { }
-static inline int alloc_fresh_gigantic_page(struct hstate *h,
- nodemask_t *nodes_allowed, bool no_init) { return 0; }
+static inline struct page *alloc_fresh_gigantic_page(struct hstate *h,
+ nodemask_t *nodes_allowed, bool no_init) { return NULL; }
#endif
static void update_and_free_page(struct hstate *h, struct page *page)
@@ -2315,7 +2315,7 @@ static unsigned long set_max_huge_pages(struct hstate *h, unsigned long count,
cond_resched();
if (hstate_is_gigantic(h))
- ret = alloc_fresh_gigantic_page(h, nodes_allowed,
+ ret = !!alloc_fresh_gigantic_page(h, nodes_allowed,
false);
else
ret = alloc_fresh_huge_page(h, nodes_allowed);
--
2.5.5
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