* [GIT PULL 4/4] bcm2835-defconfig-64-next-2016-11-18
From: Florian Fainelli @ 2016-11-22 5:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161118185835.14452-4-eric@anholt.net>
Le 18/11/2016 ? 10:58, Eric Anholt a ?crit :
> Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
>
> are available in the git repository at:
>
> https://github.com/anholt/linux tags/bcm2835-defconfig-64-next-2016-11-18
>
> for you to fetch changes up to ac178e4280e65f4d0d14b13a7bfec3a43ff90e66:
>
> ARM64: bcm2835: add thermal driver to default config (2016-11-11 09:00:00 -0800)
>
> ----------------------------------------------------------------
> This pull enables the BCM2837 (Pi 3) thermal driver in the defconfig.
>
> ----------------------------------------------------------------
Merged, thanks!
--
Florian
^ permalink raw reply
* [RFC PATCH net v2 2/3] dt: bindings: add ethernet phy eee-disable-advert option documentation
From: Florian Fainelli @ 2016-11-22 5:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121164733.GG1922@lunn.ch>
Le 21/11/2016 ? 08:47, Andrew Lunn a ?crit :
>> What I did not realize when doing this patch for the realtek driver is
>> that there is already 6 valid modes defined in the kernel
>>
>> #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /*
>> 100TX EEE cap */
>> #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /*
>> 1000T EEE cap */
>> #define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
>> #define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap
>> */
>> #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap
>> */
>> #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap
>> */
>>
>> I took care of only 2 in the case of realtek.c since it only support
>> MDIO_EEE_100TX and MDIO_EEE_1000T.
>>
>> Defining a property for each is certainly doable but it does not look
>> very nice either. If it extends in the future, it will get even more
>> messier, especially if you want to disable everything.
>
> Yes, agreed.
One risk with the definition a group of advertisement capabilities
(under the form of a bitmask for instance) to enable/disable is that we
end up with Device Tree contain some kind of configuration policy as
opposed to just flagging particular hardware features as broken.
Fortunately, there does not seem to be a ton of PHYs out there which
require EEE to be disabled to function properly so having individual
properties vs. bitmasks/groups is kind of speculative here.
Another approach to solving this problem could be to register a PHY
fixup which disables EEE at the PHY level, and which is only called for
specific boards affected by this problem (of_machine_is_compatible()).
This code can leave in arch/*/* when that is possible, or it can just be
somewhere where it is relevant, e.g; in the PHY driver for instance
(similarly to how PCI fixups are done).
--
Florian
^ permalink raw reply
* [GIT PULL 1/6] Broadcom soc changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/soc
for you to fetch changes up to 09f3510fb70a46c8921f2cf4a90dbcae460a6820:
ARM: BCM5301X: Add back handler ignoring external imprecise aborts (2016-11-16 12:39:05 -0800)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based SoC changes for 4.10, please pull
the following:
- Rafal adds back the abort handler hook on BCM5301x which is required to silence
errors forwared from the PCIe controller that cannot be silenced at the PCIe RC level
----------------------------------------------------------------
Rafa? Mi?ecki (1):
ARM: BCM5301X: Add back handler ignoring external imprecise aborts
arch/arm/mach-bcm/bcm_5301x.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
^ permalink raw reply
* [GIT PULL 2/6] Broadcom devicetree changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122054824.16974-1-f.fainelli@gmail.com>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/devicetree
for you to fetch changes up to 509f8342993be7ce2938edacec05b6e8d780c83e:
Merge tag 'bcm2835-dt-next-2016-11-18' into devicetree/next (2016-11-21 21:03:18 -0800)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based SoC Device Tree changes for 4.10,
please pull the following:
- Rafal adds support for the Netgear R8500 routers, adds basic support
for the Tenda AC9 router which uses the new BCM53573 SoC (single core Cortex
A7). He also enables the UART on the Netgear R8000 and restructures the
include files a bit for the BCM47094 SoC, finally he adds USB 3.0 PHY nodes
which enables USB 3.0 on BCM5301X devices that support it. Finally he adds
support for the TP-LINK Archer C9 V1 router.
- Kamal adds support for the QSPI controller on the Northstar Plus SoCs and updates
the bcm958625k reference board to have it enabled
- Dan adds support for the Luxul XAP-1510 (using a BCM4708) and XWR-3100 (using
a BCM47094)
- Scott fixes the pinctrl names in the Cygnus DTS files
- Jonathan enables the Broadcom iProc mailbox controller for Broadcom Cygnus/iProc
SoCs, he adds interrupt support for the GPIO CRMU hardware block and finally adds
the node for the OTP controller found on Cygnus SoCs
- Dhananjay enables the GPIO B controller on Norstarh Plus SoCs
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also fixes the Raspberry Pi GPIO lines names and finally
adds names for the Raspberry Zero GPIO lines
----------------------------------------------------------------
Dan Haab (2):
ARM: BCM5301X: Add DT for Luxul XAP-1510
ARM: BCM5301X: Add DT for Luxul XWR-3100
Eric Anholt (1):
ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
Florian Fainelli (1):
Merge tag 'bcm2835-dt-next-2016-11-18' into devicetree/next
Gerd Hoffmann (6):
pinctrl: bcm2835: add pull defines to dt bindings
ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: drop alt3 from &gpio
Jonathan Richardson (3):
ARM: dts: Enable Broadcom iProc mailbox controller
ARM: dts: Enable interrupt support for cygnus crmu gpio driver
ARM: dts: Add node for Broadcom OTP controller driver
Kamal Dasu (1):
ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes
Linus Walleij (1):
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
Martin Sperl (2):
dt: bindings: add thermal device driver for bcm2835
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
Rafa? Mi?ecki (7):
ARM: BCM5301X: Add DT for Netgear R8500
ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9
ARM: BCM5301X: Add separated DTS include file for BCM47094
ARM: BCM5301X: Enable UART on Netgear R8000
ARM: BCM5301X: Specify USB 3.0 PHY in DT
ARM: BCM53573: Specify PMU and its ILP clock in the DT
ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1
Scott Branden (1):
ARM: dts: cygnus: fix naming of pinctrl node
Stefan Wahren (4):
DT: binding: bcm2835-mbox: fix address typo in example
ARM: dts: bcm283x: fix typo in mailbox address
ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines
ARM: bcm2835: Add names for the RPi Zero GPIO lines
Yendapally Reddy Dhananjaya Reddy (1):
ARM: dts: enable GPIO-b for Broadcom NSP
.../bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +-
.../bindings/thermal/brcm,bcm2835-thermal.txt | 17 ++
arch/arm/boot/dts/Makefile | 6 +
arch/arm/boot/dts/bcm-cygnus.dtsi | 21 +-
arch/arm/boot/dts/bcm-nsp.dtsi | 41 +++-
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 67 ++++++-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 67 ++++++-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 15 +-
arch/arm/boot/dts/bcm2835.dtsi | 6 +
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
arch/arm/boot/dts/bcm2836.dtsi | 6 +
arch/arm/boot/dts/bcm283x.dtsi | 212 ++++++++++++++++++++-
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 64 +++++++
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 2 +-
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 2 +-
arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 2 +-
arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 6 +-
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 114 +++++++++++
arch/arm/boot/dts/bcm4709.dtsi | 11 ++
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 3 +-
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 111 +++++++++++
arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 103 ++++++++++
arch/arm/boot/dts/bcm47094.dtsi | 17 ++
arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 +++++++
arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi | 13 ++
arch/arm/boot/dts/bcm5301x.dtsi | 7 +
arch/arm/boot/dts/bcm53573.dtsi | 159 ++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 34 ++++
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 -
include/dt-bindings/pinctrl/bcm2835.h | 5 +
34 files changed, 1440 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt
create mode 100644 arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
create mode 100644 arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
create mode 100644 arch/arm/boot/dts/bcm4709.dtsi
create mode 100644 arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
create mode 100644 arch/arm/boot/dts/bcm47094-netgear-r8500.dts
create mode 100644 arch/arm/boot/dts/bcm47094.dtsi
create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts
create mode 100644 arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi
create mode 100644 arch/arm/boot/dts/bcm53573.dtsi
^ permalink raw reply
* [GIT PULL 3/6] Broadcom devicetree-arm64 changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122054824.16974-1-f.fainelli@gmail.com>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/devicetree-arm64
for you to fetch changes up to e687607116bc45afcbbcd0097129573f9729ff21:
Merge tag 'bcm2835-dt-64-next-2016-11-18' into devicetree-arm64/next (2016-11-21 21:09:19 -0800)
----------------------------------------------------------------
This pull request contains Broadcom ARM64 based SoC Device Tree changes for
4.10, please pull the following:
- Robin updates the Northstart 2 DTS to use the generic IOMMU binding
- Scott renames the Broadcom Northstar 2 binding document to use a standard name
including the brcm vendor prefix
- Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the
Northstar 2 SVK reference board DTS file with it enabled.
- Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the
Northstar 2 SoC
- Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the
Northstar 2 SoC
- Ray adds required properties NAND controller properties to make NAND work on
the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included
here to resolve DTS file merges
- Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS
- Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3)
- Eric defines standard pinctrl groups in the BCM2835 GPIO node
- Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes
to use their appropriate pinctrl functions
- Linus adds names for the Raspberry Pi GPIO lines based on the datasheet
- Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block
- Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and
Device Tree nodes he also uses the proper DTSI file to define the USB host mode
for the USB Device Tree nodes
----------------------------------------------------------------
Andrea Merello (1):
ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
Andreas F?rber (1):
ARM64: dts: bcm2835: Fix bcm2837 compatible string
Eric Anholt (2):
ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.
Merge branch 'bcm2835-dt-next' into bcm2835-dt-64-next
Florian Fainelli (1):
Merge tag 'bcm2835-dt-64-next-2016-11-18' into devicetree-arm64/next
Gerd Hoffmann (6):
pinctrl: bcm2835: add pull defines to dt bindings
ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio
ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio
ARM: dts: bcm283x: drop alt3 from &gpio
Jon Mason (2):
arm64: dts: NS2: enable sdio1
arm64: dts: NS2: Add PCI PHYs
Kamal Dasu (1):
ARM64: dts: Add QSPI Device Tree node for NS2
Linus Walleij (1):
ARM: bcm2835: Add names for the Raspberry Pi GPIO lines
Martin Sperl (3):
dt: bindings: add thermal device driver for bcm2835
ARM: bcm2835: dts: add thermal node to device-tree of bcm283x
ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837
Ray Jui (1):
arm64: dts: Updated NAND DT properties for NS2 SVK
Rob Rice (1):
arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver.
Robin Murphy (1):
arm64: dts: Update Broadcom NS2 to generic IOMMU binding
Scott Branden (1):
arm64: dts: rename ns2.txt to brcm,ns2.txt
Stefan Wahren (3):
ARM64: dts: bcm283x: Use dtsi for USB host mode
DT: binding: bcm2835-mbox: fix address typo in example
ARM: dts: bcm283x: fix typo in mailbox address
.../bindings/arm/bcm/{ns2.txt => brcm,ns2.txt} | 0
.../bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +-
.../bindings/thermal/brcm,bcm2835-thermal.txt | 17 ++
arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 67 ++++++-
arch/arm/boot/dts/bcm2835-rpi-a.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 68 ++++++-
arch/arm/boot/dts/bcm2835-rpi-b.dts | 69 ++++++-
arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +-
arch/arm/boot/dts/bcm2835-rpi.dtsi | 15 +-
arch/arm/boot/dts/bcm2835.dtsi | 6 +
arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +-
arch/arm/boot/dts/bcm2836.dtsi | 6 +
arch/arm/boot/dts/bcm283x.dtsi | 212 ++++++++++++++++++++-
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 8 +-
arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 8 +-
.../boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi | 1 +
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 40 ++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 62 +++++-
drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 -
include/dt-bindings/pinctrl/bcm2835.h | 5 +
21 files changed, 703 insertions(+), 30 deletions(-)
rename Documentation/devicetree/bindings/arm/bcm/{ns2.txt => brcm,ns2.txt} (100%)
create mode 100644 Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt
create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-usb-host.dtsi
^ permalink raw reply
* [GIT PULL 4/6] Broadcom maintainers-arm64 changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122054824.16974-1-f.fainelli@gmail.com>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/maintainers-arm64
for you to fetch changes up to 3483b163d2ac14c6e35d201b9db7dde70841a199:
MAINTAINERS: Update Broadcom Vulcan maintainer email (2016-11-05 17:25:55 -0700)
----------------------------------------------------------------
This pull request contains MAINTAINERS file updates for Broadcom ARM64 entries,
please pull:
- Jayachandran updates his email address for the Broadcom Vulcan entry
----------------------------------------------------------------
Jayachandran C (1):
MAINTAINERS: Update Broadcom Vulcan maintainer email
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply
* [GIT PULL 5/6] Broadcom defconfig changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122054824.16974-1-f.fainelli@gmail.com>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/defconfig
for you to fetch changes up to 33c037c51be5df857ae563f7fc551dc6e746d9de:
Merge tag 'bcm2835-defconfig-next-2016-11-18' into defconfig/next (2016-11-21 21:20:15 -0800)
----------------------------------------------------------------
This pull request contains Broadcom ARM-based defconfig changes for 4.10, please
pull the following:
- Florian updates the multi_v7_defconfig with the relevant basic drivers needed
for the Broadcom BCM5301x (Northstar) SoCs to reboot, have PCIe, and Ethernet
- Martin enables the Raspberry Pi thermal driver in bcm2835_defconfig
----------------------------------------------------------------
Florian Fainelli (2):
ARM: multi_v7_defconfig: Enable BCM47xx/BCM5301x drivers
Merge tag 'bcm2835-defconfig-next-2016-11-18' into defconfig/next
Martin Sperl (1):
ARM: bcm2835: add thermal driver to default config
arch/arm/configs/bcm2835_defconfig | 2 ++
arch/arm/configs/multi_v7_defconfig | 13 +++++++++++++
2 files changed, 15 insertions(+)
^ permalink raw reply
* [GIT PULL 6/6] Broadcom defconfig-arm64 changes for 4.10
From: Florian Fainelli @ 2016-11-22 5:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161122054824.16974-1-f.fainelli@gmail.com>
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.10/defconfig-arm64
for you to fetch changes up to 9efacfc80902c6ddf538a2f396e0112c1f6d1e23:
Merge tag 'bcm2835-defconfig-64-next-2016-11-18' into defconfig-arm64/next (2016-11-21 21:22:55 -0800)
----------------------------------------------------------------
This pull request contains Broadcom ARM64-based SoCs defconfig changes for 4.10,
please pull the following changes:
- Eric updates the ARMv8 defconfig to contain everything that is needed to run
a 64-bit kernel on the Raspberry Pi 3
- Scott enables the standard AT25 EEPROM driver as module for the ARM64 defconfig
- Martin enables the Raspberry Pi Thermal driver in the ARM64 defconfig
----------------------------------------------------------------
Eric Anholt (1):
arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig
Florian Fainelli (2):
Merge tag 'bcm2835-defconfig-64-next-2016-09-22' into defconfig-arm64/next
Merge tag 'bcm2835-defconfig-64-next-2016-11-18' into defconfig-arm64/next
Martin Sperl (1):
ARM64: bcm2835: add thermal driver to default config
Scott Branden (1):
arm64: defconfig: enable EEPROM_AT25 config option
arch/arm64/configs/defconfig | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
^ permalink raw reply
* [PATCH v2 2/4] spi: spi-fsl-dspi: Fix continuous selection format
From: maitysanchayan at gmail.com @ 2016-11-22 6:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <59ac10adfe92916770aa30146e958887@agner.ch>
On 16-11-21 15:15:41, Stefan Agner wrote:
> On 2016-11-20 21:54, Sanchayan Maity wrote:
> > Current DMA implementation was not handling the continuous selection
> > format viz. SPI chip select would be deasserted even between sequential
> > serial transfers. Use the cs_change variable and correctly set or
> > reset the CONT bit accordingly for case where peripherals require
> > the chip select to be asserted between sequential transfers.
> >
> > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> > ---
> > drivers/spi/spi-fsl-dspi.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
> > index b1ee1f5..41422cd 100644
> > --- a/drivers/spi/spi-fsl-dspi.c
> > +++ b/drivers/spi/spi-fsl-dspi.c
> > @@ -261,6 +261,8 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
> > dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) |
> > SPI_PUSHR_PCS(dspi->cs) |
> > SPI_PUSHR_CTAS(0);
> > + if (!dspi->cs_change)
> > + dspi->dma->tx_dma_buf[i] |= SPI_PUSHR_CONT;
> > dspi->tx += tx_word + 1;
> >
> > dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
>
> Other transfer mode use:
>
> if ((dspi->cs_change) && (!dspi->len))
>
> dspi_pushr &= ~SPI_PUSHR_CONT;
>
> which indicates that they only clear SPI_PUSHR_CONT at the very end of a
> transfer... The DMA code currently deselects after every DMA transfer if
> dspi->cs_change is set.
>
> Maybe we should use the helper dspi_data_to_pushr to fill the DMA buffer
> and _clear_ SPI_PUSHR_CONT if necessary like the other transfer modes
> do... Then we can use the for loop to fill the complete buffer and get
> rid of some code dupplication.
>
> I see that dspi_data_to_pushr does move len too, which we did not in the
> DMA case. dspi->len gets incremented only on successful DMA transfer in
> dspi_dma_xfer. However, I wonder if that is not even a bug: We increment
> dspi->tx always, but len only on success. This makes len go off sync
> with regards to the tx pointer which does not help anybody. So lets get
> rid of the update code in dspi_dma_xfer
>
Thanks for the feedback. Using dspi_data_to_pushr really cleans up that
tx path very nicely. Why didn't I see it. Will send a follow up patch
soon after testing again.
- Sanchayan.
^ permalink raw reply
* [PATCH v2 4/4] spi: spi-fsl-dspi: Minor code cleanup and error path fixes
From: maitysanchayan at gmail.com @ 2016-11-22 6:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <43b518a92352986f09b0893646ff8016@agner.ch>
On 16-11-21 15:22:09, Stefan Agner wrote:
> On 2016-11-20 21:54, Sanchayan Maity wrote:
> > Code cleanup for improving code readability and error path fixes
> > and cleanup removing use of devm_kfree.
>
> Two things in one, not very nice. Especially the dma_free_coherent is
> really a bug and the other is a cleanup. Can you make a separate patch
> for the bug?
>
> As for the cleanup, I don't like the one line conditions too, but I
> don't think it is worth a patch. At least the TX path should be solved
> with my suggestion in patch 2.
Agreed.
- Sanchayan.
>
> --
> Stefan
>
> >
> > Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
> > ---
> > drivers/spi/spi-fsl-dspi.c | 22 ++++++++++++++++------
> > 1 file changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
> > index 08882f7..2987a16 100644
> > --- a/drivers/spi/spi-fsl-dspi.c
> > +++ b/drivers/spi/spi-fsl-dspi.c
> > @@ -226,8 +226,10 @@ static void dspi_rx_dma_callback(void *arg)
> > if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
> > for (i = 0; i < dma->curr_xfer_len; i++) {
> > d = dspi->dma->rx_dma_buf[i];
> > - rx_word ? (*(u16 *)dspi->rx = d) :
> > - (*(u8 *)dspi->rx = d);
> > + if (rx_word)
> > + *(u16 *)dspi->rx = d;
> > + else
> > + *(u8 *)dspi->rx = d;
> > dspi->rx += rx_word + 1;
> > }
> > }
> > @@ -247,14 +249,20 @@ static int dspi_next_xfer_dma_submit(struct
> > fsl_dspi *dspi)
> > tx_word = is_double_byte_mode(dspi);
> >
> > for (i = 0; i < dma->curr_xfer_len - 1; i++) {
> > - val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
> > + if (tx_word)
> > + val = *(u16 *) dspi->tx;
> > + else
> > + val = *(u8 *) dspi->tx;
> > dspi->dma->tx_dma_buf[i] =
> > SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) |
> > SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT;
> > dspi->tx += tx_word + 1;
> > }
> >
> > - val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
> > + if (tx_word)
> > + val = *(u16 *) dspi->tx;
> > + else
> > + val = *(u8 *) dspi->tx;
> > dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) |
> > SPI_PUSHR_PCS(dspi->cs) |
> > SPI_PUSHR_CTAS(0);
> > @@ -430,9 +438,11 @@ static int dspi_request_dma(struct fsl_dspi
> > *dspi, phys_addr_t phy_addr)
> > return 0;
> >
> > err_slave_config:
> > - devm_kfree(dev, dma->rx_dma_buf);
> > + dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
> > + dma->rx_dma_buf, dma->rx_dma_phys);
> > err_rx_dma_buf:
> > - devm_kfree(dev, dma->tx_dma_buf);
> > + dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
> > + dma->tx_dma_buf, dma->tx_dma_phys);
> > err_tx_dma_buf:
> > dma_release_channel(dma->chan_tx);
> > err_tx_channel:
^ permalink raw reply
* [PATCH v2 1/5] ARM: memory: da8xx-ddrctl: new driver
From: Sekhar Nori @ 2016-11-22 6:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5833A2DA.40701@gmail.com>
Hi Frank,
On Tuesday 22 November 2016 07:13 AM, Frank Rowand wrote:
> On 11/21/16 08:33, Sekhar Nori wrote:
>> On Monday 31 October 2016 08:15 PM, Bartosz Golaszewski wrote:
>>> +static int da8xx_ddrctl_probe(struct platform_device *pdev)
>>> +{
>>> + const struct da8xx_ddrctl_config_knob *knob;
>>> + const struct da8xx_ddrctl_setting *setting;
>>> + struct device_node *node;
>>> + struct resource *res;
>>> + void __iomem *ddrctl;
>>> + struct device *dev;
>>> + u32 reg;
>>> +
>>> + dev = &pdev->dev;
>>> + node = dev->of_node;
>>> +
>>> + setting = da8xx_ddrctl_get_board_settings();
>>> + if (!setting) {
>>> + dev_err(dev, "no settings for board '%s'\n",
>>> + of_flat_dt_get_machine_name());
>>> + return -EINVAL;
>>> + }
>>
>> This causes a section mismatch because of_flat_dt_get_machine_name()
>> has an __init annotation. I did not notice that before, sorry.
>>
>> It can be fixed with a patch like below:
>>
>> ---8<---
>> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
>> index a20e7bbbcbe0..9ca5aab3ac54 100644
>> --- a/drivers/memory/da8xx-ddrctl.c
>> +++ b/drivers/memory/da8xx-ddrctl.c
>> @@ -102,6 +102,18 @@ static const struct da8xx_ddrctl_setting *da8xx_ddrctl_get_board_settings(void)
>> return NULL;
>> }
>>
>> +static const char* da8xx_ddrctl_get_machine_name(void)
>> +{
>> + const char *str;
>> + int ret;
>> +
>> + ret = of_property_read_string(of_root, "model", &str);
>> + if (ret)
>> + ret = of_property_read_string(of_root, "compatible", &str);
>> +
>> + return str;
>> +}
>> +
>> static int da8xx_ddrctl_probe(struct platform_device *pdev)
>> {
>> const struct da8xx_ddrctl_config_knob *knob;
>> @@ -118,7 +130,7 @@ static int da8xx_ddrctl_probe(struct platform_device *pdev)
>> setting = da8xx_ddrctl_get_board_settings();
>> if (!setting) {
>> dev_err(dev, "no settings for board '%s'\n",
>> - of_flat_dt_get_machine_name());
>
> da8xx_ddrctl_get_board_settings() tries to match based on the "compatible"
> property in the root node. The "model" property in the root node has
> nothing to do with the failure to match. So creating and then using
> da8xx_ddrctl_get_machine_name() to potentially report model is not useful.
>
> It should be sufficient to simply report that no compatible matched.
I agree with you on this. Even if model name is printed, you will have
to go back and check the compatible anyway. But I think it will be
useful to print the compatible instead of just reporting that nothing
matched.
Bartosz, if you agree too, could you send a fix patch just printing the
compatible?
Thanks,
Sekhar
^ permalink raw reply
* [PATCH v3 0/3] Fixes for Vybrid SPI DMA implementation
From: Sanchayan Maity @ 2016-11-22 7:01 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
This v3 set of patches have fixes for Vybrid SPI DMA
implementation and is rebased on top of latest topic/fsl-dspi.
http://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/log/?h=topic/fsl-dspi
The patches have been tested on a Toradex Colibri Vybrid VF61 module
and now incoporate feedback from Stefan on version 2 of patchset.
Changes since v2:
1. Drop the patch "Fix SPI transfer issue when using multiple SPI_IOC_MESSAGE"
since it's now applied and rebase the whole patchset
2. Second patch in this series "Fix continuous selection format" now
fixes the issue using an existing function and handling it similar to
existing EOQ mode and also cleaning up nicely the transmit code path.
3. Third patch now just fixes the incorrect freeing of DMA allocated buffers
and drops the minor clean up patch from earlier series completely due to
the clean up from 2 above.
Changes since v1:
1. Place the continuous selection format patch second in order and remove
code duplication
2. Improve the use of curr_xfer_len and instead of converting from bytes
to DMA transfers in every use, do it at a single place. Accordingly change
it's use at other places
3. Code cleanup patch has less to clean with change above
v2:
https://www.spinics.net/lists/arm-kernel/msg543941.html
v1:
http://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1274632.html
Thanks & Regards,
Sanchayan.
Sanchayan Maity (3):
spi: spi-fsl-dspi: Fix incorrect DMA setup
spi: spi-fsl-dspi: Fix continuous selection format
spi: spi-fsl-dspi: Fix incorrect freeing of DMA allocated buffers
drivers/spi/spi-fsl-dspi.c | 59 +++++++++++++++++++++-------------------------
1 file changed, 27 insertions(+), 32 deletions(-)
--
2.10.2
^ permalink raw reply
* [PATCH v3 1/3] spi: spi-fsl-dspi: Fix incorrect DMA setup
From: Sanchayan Maity @ 2016-11-22 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1479796821.git.maitysanchayan@gmail.com>
Currently dmaengine_prep_slave_single was being called with length
set to the complete DMA buffer size. This resulted in unwanted bytes
being transferred to the SPI register leading to clock and MOSI lines
having unwanted data even after chip select got deasserted and the
required bytes having been transferred.
While at it also clean up the use of curr_xfer_len which is central
to the DMA setup, from bytes to DMA transfers for every use.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
---
drivers/spi/spi-fsl-dspi.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index b1ee1f5..911aadb 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -151,6 +151,7 @@ static const struct fsl_dspi_devtype_data ls2085a_data = {
};
struct fsl_dspi_dma {
+ /* Length of transfer in words of DSPI_FIFO_SIZE */
u32 curr_xfer_len;
u32 *tx_dma_buf;
@@ -217,15 +218,13 @@ static void dspi_rx_dma_callback(void *arg)
struct fsl_dspi *dspi = arg;
struct fsl_dspi_dma *dma = dspi->dma;
int rx_word;
- int i, len;
+ int i;
u16 d;
rx_word = is_double_byte_mode(dspi);
- len = rx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
-
if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
- for (i = 0; i < len; i++) {
+ for (i = 0; i < dma->curr_xfer_len; i++) {
d = dspi->dma->rx_dma_buf[i];
rx_word ? (*(u16 *)dspi->rx = d) :
(*(u8 *)dspi->rx = d);
@@ -242,14 +241,12 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
struct device *dev = &dspi->pdev->dev;
int time_left;
int tx_word;
- int i, len;
+ int i;
u16 val;
tx_word = is_double_byte_mode(dspi);
- len = tx_word ? (dma->curr_xfer_len / 2) : dma->curr_xfer_len;
-
- for (i = 0; i < len - 1; i++) {
+ for (i = 0; i < dma->curr_xfer_len - 1; i++) {
val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
dspi->dma->tx_dma_buf[i] =
SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) |
@@ -265,7 +262,9 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
dma->tx_dma_phys,
- DSPI_DMA_BUFSIZE, DMA_MEM_TO_DEV,
+ dma->curr_xfer_len *
+ DMA_SLAVE_BUSWIDTH_4_BYTES,
+ DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma->tx_desc) {
dev_err(dev, "Not able to get desc for DMA xfer\n");
@@ -281,7 +280,9 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
dma->rx_dma_phys,
- DSPI_DMA_BUFSIZE, DMA_DEV_TO_MEM,
+ dma->curr_xfer_len *
+ DMA_SLAVE_BUSWIDTH_4_BYTES,
+ DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma->rx_desc) {
dev_err(dev, "Not able to get desc for DMA xfer\n");
@@ -328,17 +329,17 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi)
struct device *dev = &dspi->pdev->dev;
int curr_remaining_bytes;
int bytes_per_buffer;
- int tx_word;
+ int word = 1;
int ret = 0;
- tx_word = is_double_byte_mode(dspi);
+ if (is_double_byte_mode(dspi))
+ word = 2;
curr_remaining_bytes = dspi->len;
+ bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
while (curr_remaining_bytes) {
/* Check if current transfer fits the DMA buffer */
- dma->curr_xfer_len = curr_remaining_bytes;
- bytes_per_buffer = DSPI_DMA_BUFSIZE /
- (DSPI_FIFO_SIZE / (tx_word ? 2 : 1));
- if (curr_remaining_bytes > bytes_per_buffer)
+ dma->curr_xfer_len = curr_remaining_bytes / word;
+ if (dma->curr_xfer_len > bytes_per_buffer)
dma->curr_xfer_len = bytes_per_buffer;
ret = dspi_next_xfer_dma_submit(dspi);
@@ -347,7 +348,7 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi)
goto exit;
} else {
- curr_remaining_bytes -= dma->curr_xfer_len;
+ curr_remaining_bytes -= dma->curr_xfer_len * word;
if (curr_remaining_bytes < 0)
curr_remaining_bytes = 0;
dspi->len = curr_remaining_bytes;
--
2.10.2
^ permalink raw reply related
* [PATCH v3 2/3] spi: spi-fsl-dspi: Fix continuous selection format
From: Sanchayan Maity @ 2016-11-22 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1479796821.git.maitysanchayan@gmail.com>
Current DMA implementation was not handling the continuous selection
format viz. SPI chip select would be deasserted even between sequential
serial transfers.
Use existing dspi_data_to_pushr function to restructure the transmit
code path and set or reset the CONT bit on same lines as code path
in EOQ mode does. This correctly implements continuous selection format
while also correcting and cleaning up the transmit code path.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
drivers/spi/spi-fsl-dspi.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 911aadb..8af3151 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -196,6 +196,8 @@ struct fsl_dspi {
struct fsl_dspi_dma *dma;
};
+static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word);
+
static inline int is_double_byte_mode(struct fsl_dspi *dspi)
{
unsigned int val;
@@ -242,24 +244,15 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
int time_left;
int tx_word;
int i;
- u16 val;
tx_word = is_double_byte_mode(dspi);
- for (i = 0; i < dma->curr_xfer_len - 1; i++) {
- val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
- dspi->dma->tx_dma_buf[i] =
- SPI_PUSHR_TXDATA(val) | SPI_PUSHR_PCS(dspi->cs) |
- SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT;
- dspi->tx += tx_word + 1;
+ for (i = 0; i < dma->curr_xfer_len; i++) {
+ dspi->dma->tx_dma_buf[i] = dspi_data_to_pushr(dspi, tx_word);
+ if ((dspi->cs_change) && (!dspi->len))
+ dspi->dma->tx_dma_buf[i] &= ~SPI_PUSHR_CONT;
}
- val = tx_word ? *(u16 *) dspi->tx : *(u8 *) dspi->tx;
- dspi->dma->tx_dma_buf[i] = SPI_PUSHR_TXDATA(val) |
- SPI_PUSHR_PCS(dspi->cs) |
- SPI_PUSHR_CTAS(0);
- dspi->tx += tx_word + 1;
-
dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
dma->tx_dma_phys,
dma->curr_xfer_len *
@@ -351,7 +344,6 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi)
curr_remaining_bytes -= dma->curr_xfer_len * word;
if (curr_remaining_bytes < 0)
curr_remaining_bytes = 0;
- dspi->len = curr_remaining_bytes;
}
}
--
2.10.2
^ permalink raw reply related
* [PATCH v3 3/3] spi: spi-fsl-dspi: Fix incorrect freeing of DMA allocated buffers
From: Sanchayan Maity @ 2016-11-22 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1479796821.git.maitysanchayan@gmail.com>
Buffers allocated with a call to dma_alloc_coherent should be
freed with dma_free_coherent instead of the currently used
devm_kfree.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
---
drivers/spi/spi-fsl-dspi.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 8af3151..7ada112 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -420,9 +420,11 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
return 0;
err_slave_config:
- devm_kfree(dev, dma->rx_dma_buf);
+ dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
+ dma->rx_dma_buf, dma->rx_dma_phys);
err_rx_dma_buf:
- devm_kfree(dev, dma->tx_dma_buf);
+ dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
+ dma->tx_dma_buf, dma->tx_dma_phys);
err_tx_dma_buf:
dma_release_channel(dma->chan_tx);
err_tx_channel:
--
2.10.2
^ permalink raw reply related
* [BUG] hdlcd gets confused about base address
From: Daniel Vetter @ 2016-11-22 7:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20161121145528.GI1041@n2100.armlinux.org.uk>
On Mon, Nov 21, 2016 at 02:55:28PM +0000, Russell King - ARM Linux wrote:
> On Mon, Nov 21, 2016 at 02:30:53PM +0000, Russell King - ARM Linux wrote:
> > On Mon, Nov 21, 2016 at 01:24:19PM +0000, Russell King - ARM Linux wrote:
> > > On Mon, Nov 21, 2016 at 12:56:53PM +0000, Liviu Dudau wrote:
> > > > That is mostly due to the check in hdlcd_crtc_disable() which I should
> > > > remove, I've added it because I was getting a ->disable() hook call
> > > > before any ->enable() was called at startup time. I need to revisit
> > > > this as I remember Daniel was commenting that this was not needed.
> > >
> > > Removing that test results in:
> > >
> > > [drm:drm_atomic_helper_commit_cleanup_done] *ERROR* [CRTC:24:crtc-0] flip_done timed out
> > >
> > > and the kernel hanging, seemingly in an IRQs-off region.
> >
> > Annoyingly, enabling DRM debug prevents the kernel hanging...
>
> I've been trying to trace through what's happening with this flip_done
> stuff, but I'm finding it _extremely_ difficult to follow the atomic
> code.
>
> (Sorry, I'm going to go over my usual 72 column limit for this due to
> the damn long DRM function names.)
>
> I can see that drm_atomic_helper_commit() calls drm_atomic_helper_setup_commit()
> which sets up commit->flip_done for each CRTC, and sets up an event for
> each.
>
> drm_atomic_helper_commit() continues on to eventually call drm_atomic_helper_swap_state()
> which then swaps the state for the CRTCs, but then ends up dropping
> the event reference:
>
> state->crtcs[i].commit->event = NULL;
>
> What I can't see is why this isn't a leaked pointer - I don't see
> anything inbetween taking charge of that structure. The _commit_
> hasn't been swapped from what I can see, it's just state->crtcs[i].state
> that have been swapped.
The event is also stored in crtc_state->event, which after swap_states
land in drm_crtc->state->event, which is the place drivers are supposed to
pick it up from for delivery.
> So I can't see who's responsible for generating this event, or how the
> backend DRM drivers get to know about this event, and that they should
> complete the flip.
>
> What I also don't get is why DRM is wanting to wait for a flip event
> when we're disabling the CRTC. None of this makes sense to me, like
> much of the atomic modeset code...
The DRM event has two uses:
- high-precision timestamp for when the new frame starts displaying.
- confirmation that the old buffers are no longer being used by the hw.
This is used on Android's drm_hwcomposer in the new hwc2 mode.
Note that the crtc_state->event has 3 uses in total, all hidden behind the
abstraction:
- flip_done, for the atomic helpers
- drm event, for current userspace (also needed to emulate legacy flips)
- and out-fences, needed by android.
The trouble with ->event delivery was that many drivers didn't bother to
implement this at all, since driver submitters never even tested
pageflippping. And for those maintainers that did test pageflipping, they
only ever tested the legacy page_flip paths, which e.g. doesn't ever ask
for an event when disabling the CRTC (since you can't do that). But atomic
allows all this, and review wasn't enough to fight the influx of bad
drivers. Hence I opted to make the nonblocking support in the atomic
helpers enforce this part of the abi contract, even for blocking modesets.
If you're stuck on a flip_done, then your driver doesn't send out events
when disabling the CRTC.
All the waits have a 10s timeout, and none of them are in atomic contexts,
so no idea why this takes down your box. I suspect it's something
unrelated.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply
* [PATCH 2/2] MAINTAINERS: Add myself as co-maintainer to fpga mgr framework.
From: Michal Simek @ 2016-11-22 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1611212021050.3633@atull-VirtualBox2>
On 22.11.2016 03:29, atull wrote:
> On Mon, 21 Nov 2016, Moritz Fischer wrote:
>
>> Add myself as co-maintainer to fpga mgr framework.
>>
>> Signed-off-by: Moritz Fischer <mdf@kernel.org>
>> Cc: Alan Tull <atull@opensource.altera.com>
>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> Cc: linux-kernel at vger.kernel.org
>> Cc: linux-fpga at vger.kernel.org
>> ---
>> Hi all,
>>
>> Lately we've fallen behind a bit on reviewing patches lately.
>
> Hi Moritz,
>
> drivers/fpga has been in the upstream kernel a year now. Most of that
> time, traffic has been very slow. Recently we had more traffic while
> I was travelling and moving to a new office, both cases leaving me
> with bad network connectivity. Things will probably return to normal.
> I appreciate your passion and all your effort reviewing stuff. I
> don't see a need for two maintainers at this point.
TBH. I think it is not a bad option. I do normally have backup person
for all repos I do maintain. It doesn't mean that second maintainer does
something but it has all accesses to repos you maintain.
It means if something really happens to you (hopefully not) than this
person can continue in this work without any delay which is not a bad
thing.
It is really just about talking to each other what that second person
will do - probably just review patches as is done now. You can also
learn from each other.
I would like to be involved more in this but unfortunately I don't have
enough time to do it properly.
Regarding maintaining this repo. It is just standard process. Apply
sensible things, well described and test it. And then send pull request
to Greg based on signed tags and you are done.
Greg should told you what should be the base which you should use for
pull request. Someone is taking patches based on rc1 tag, someone is
rebasing it on the final tag.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Thanks,
Michal
^ permalink raw reply
* [PATCH 0/6] add hisilicon reset
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
Add reset-hi3660.c
Update reset-hi6220 as well
reset.c is shared by reset-hi3660.c and reset-hi6220.c
Change hi6220.dtsi accordingly
Zhangfei Gao (6):
reset: hisilicon: add reset core
dt-bindings: Document the hi3660 reset bindings
reset: hisilicon: add reset-hi3660
dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
reset: hisilicon: Use new driver reset-hi6222
arm64: dts: hi6220: update reset node according to reset-hi6220.c
.../bindings/reset/hisilicon,hi3660-reset.txt | 42 ++++++
.../bindings/reset/hisilicon,hi6220-reset.txt | 14 +-
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 20 ++-
drivers/reset/Makefile | 2 +-
drivers/reset/hisilicon/Kconfig | 7 +
drivers/reset/hisilicon/Makefile | 4 +-
drivers/reset/hisilicon/hi6220_reset.c | 157 ---------------------
drivers/reset/hisilicon/reset-hi3660.c | 78 ++++++++++
drivers/reset/hisilicon/reset-hi6220.c | 123 ++++++++++++++++
drivers/reset/hisilicon/reset.c | 108 ++++++++++++++
drivers/reset/hisilicon/reset.h | 37 +++++
include/dt-bindings/reset/hisi,hi3660-resets.h | 38 +++++
include/dt-bindings/reset/hisi,hi6220-resets.h | 130 ++++++++---------
13 files changed, 527 insertions(+), 233 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
delete mode 100644 drivers/reset/hisilicon/hi6220_reset.c
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
create mode 100644 drivers/reset/hisilicon/reset-hi6220.c
create mode 100644 drivers/reset/hisilicon/reset.c
create mode 100644 drivers/reset/hisilicon/reset.h
create mode 100644 include/dt-bindings/reset/hisi,hi3660-resets.h
--
2.7.4
^ permalink raw reply
* [PATCH 1/6] reset: hisilicon: add reset core
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
reset.c will be shared by hisilicon chips like hi3660 and hi6220
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/reset/Makefile | 2 +-
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset.c | 108 +++++++++++++++++++++++++++++++++++++++
drivers/reset/hisilicon/reset.h | 37 ++++++++++++++
4 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 drivers/reset/hisilicon/reset.c
create mode 100644 drivers/reset/hisilicon/reset.h
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index bbe7026..7e3dc4e 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,8 +1,8 @@
obj-y += core.o
-obj-y += hisilicon/
obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index c932f86..df511f5 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1 +1,2 @@
+obj-y += reset.o
obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/reset.c b/drivers/reset/hisilicon/reset.c
new file mode 100644
index 0000000..c4971c9
--- /dev/null
+++ b/drivers/reset/hisilicon/reset.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset.h"
+
+struct hisi_reset_controller {
+ struct reset_controller_dev rst;
+ const struct hisi_reset_channel_data *channels;
+ struct regmap *map;
+};
+
+#define to_hisi_reset_controller(_rst) \
+ container_of(_rst, struct hisi_reset_controller, rst)
+
+static int hisi_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, bool assert)
+{
+ struct hisi_reset_controller *rc = to_hisi_reset_controller(rcdev);
+ const struct hisi_reset_channel_data *ch;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ ch = &rc->channels[idx];
+
+ if (assert)
+ return regmap_write(rc->map, ch->enable.reg,
+ GENMASK(ch->enable.msb, ch->enable.lsb));
+ else
+ return regmap_write(rc->map, ch->disable.reg,
+ GENMASK(ch->disable.msb, ch->disable.lsb));
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hisi_reset_program_hw(rcdev, idx, true);
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hisi_reset_program_hw(rcdev, idx, false);
+}
+
+static int hisi_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err;
+
+ err = hisi_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return hisi_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+ .reset = hisi_reset_dev,
+ .assert = hisi_reset_assert,
+ .deassert = hisi_reset_deassert,
+};
+
+int hisi_reset_probe(struct platform_device *pdev)
+{
+ struct hisi_reset_controller *rc;
+ struct device_node *np = pdev->dev.of_node;
+ struct hisi_reset_controller_data *d;
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *match;
+
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ d = (struct hisi_reset_controller_data *)match->data;
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
+ if (IS_ERR(rc->map)) {
+ dev_err(dev, "failed to get hisi,rst-syscon\n");
+ return PTR_ERR(rc->map);
+ }
+
+ rc->rst.ops = &hisi_reset_ops,
+ rc->rst.of_node = np;
+ rc->rst.nr_resets = d->nr_channels;
+ rc->channels = d->channels;
+
+ return reset_controller_register(&rc->rst);
+}
+EXPORT_SYMBOL_GPL(hisi_reset_probe);
diff --git a/drivers/reset/hisilicon/reset.h b/drivers/reset/hisilicon/reset.h
new file mode 100644
index 0000000..77259ee
--- /dev/null
+++ b/drivers/reset/hisilicon/reset.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __HISILICON_RESET_H
+#define __HISILICON_RESET_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/* reset separated register offset is 0x4 */
+#define HISI_RST_SEP(off, bit) \
+ { .enable = REG_FIELD(off, bit, bit), \
+ .disable = REG_FIELD(off + 0x4, bit, bit), \
+ .status = REG_FIELD(off + 0x8, bit, bit), }
+
+struct hisi_reset_channel_data {
+ struct reg_field enable;
+ struct reg_field disable;
+ struct reg_field status;
+};
+
+struct hisi_reset_controller_data {
+ int nr_channels;
+ const struct hisi_reset_channel_data *channels;
+};
+
+int hisi_reset_probe(struct platform_device *pdev);
+
+#endif /* __HISILICON_RESET_H */
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: Document the hi3660 reset bindings
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
Add DT bindings documentation for hi3660 SoC reset controller.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
.../bindings/reset/hisilicon,hi3660-reset.txt | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
new file mode 100644
index 0000000..20e03a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -0,0 +1,42 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi3660 SoC.
+
+Required properties:
+- compatible: should be one of the following:
+ - "hisilicon,hi3660-reset-crgctrl : reset control for peripherals in crgctrl.
+ - "hisilicon,hi3660-reset-iomcu : reset control for peripherals in iomcu.
+- hisi,rst-syscon: phandle of the reset's syscon.
+- #reset-cells: 1, see below
+
+Example:
+ crg_ctrl: crg_ctrl at fff35000 {
+ compatible = "hisilicon,hi3660-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ crg_rst: crg_rst_controller {
+ compatible = "hisilicon,hi3660-reset-crgctrl";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&crg_ctrl>;
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ ufs: ufs at ..... {
+ ...
+ resets = <&crg_rst HI3660_RST_UFS>,
+ <&crg_rst HI3660_RST_UFS_ASSERT>;
+ reset-names = "rst", "assert";
+ ...
+ };
+
+The index could be found in <dt-bindings/reset/hisi,hi3660-resets.h>.
--
2.7.4
^ permalink raw reply related
* [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
Add hi3660 reset driver based on common reset.c
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/reset/hisilicon/Kconfig | 7 +++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset-hi3660.c | 78 ++++++++++++++++++++++++++
include/dt-bindings/reset/hisi,hi3660-resets.h | 38 +++++++++++++
4 files changed, 124 insertions(+)
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
create mode 100644 include/dt-bindings/reset/hisi,hi3660-resets.h
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
index 1ff8b0c..10134dc 100644
--- a/drivers/reset/hisilicon/Kconfig
+++ b/drivers/reset/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_RESET_HI3660
+ tristate "Hi3660 Reset Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi3660 reset driver.
+
config COMMON_RESET_HI6220
tristate "Hi6220 Reset Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index df511f5..57e9893 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1,2 +1,3 @@
obj-y += reset.o
+obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c
new file mode 100644
index 0000000..7da3153
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi3660.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/reset/hisi,hi3660-resets.h>
+
+#include "reset.h"
+
+static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
+ [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
+ [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
+ [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
+ [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
+};
+
+static struct hisi_reset_controller_data hi3660_iomcu_controller = {
+ .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
+ .channels = hi3660_iomcu_rst,
+};
+
+static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
+ [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
+ [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
+ [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
+ [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
+ [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
+ [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
+ [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
+ [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
+ [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
+ [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
+ [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
+ [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
+ [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
+ [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
+ [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
+};
+
+static struct hisi_reset_controller_data hi3660_crgctrl_controller = {
+ .nr_channels = ARRAY_SIZE(hi3660_crgctrl_rst),
+ .channels = hi3660_crgctrl_rst,
+};
+
+static const struct of_device_id hi3660_reset_match[] = {
+ { .compatible = "hisilicon,hi3660-reset-crgctrl",
+ .data = &hi3660_crgctrl_controller, },
+ { .compatible = "hisilicon,hi3660-reset-iomcu",
+ .data = &hi3660_iomcu_controller, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hi3660_reset_match);
+
+static struct platform_driver hi3660_reset_driver = {
+ .probe = hisi_reset_probe,
+ .driver = {
+ .name = "reset-hi3660",
+ .of_match_table = hi3660_reset_match,
+ },
+};
+
+static int __init hi3660_reset_init(void)
+{
+ return platform_driver_register(&hi3660_reset_driver);
+}
+arch_initcall(hi3660_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi3660-reset");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Reset Driver");
diff --git a/include/dt-bindings/reset/hisi,hi3660-resets.h b/include/dt-bindings/reset/hisi,hi3660-resets.h
new file mode 100644
index 0000000..a65f382
--- /dev/null
+++ b/include/dt-bindings/reset/hisi,hi3660-resets.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI3660
+#define _DT_BINDINGS_RESET_CONTROLLER_HI3660
+
+/* reset in iomcu */
+#define HI3660_RST_I2C0 0
+#define HI3660_RST_I2C1 1
+#define HI3660_RST_I2C2 2
+#define HI3660_RST_I2C6 3
+
+
+/* reset in crgctrl */
+#define HI3660_RST_I2C3 0
+#define HI3660_RST_I2C4 1
+#define HI3660_RST_I2C7 2
+#define HI3660_RST_SD 3
+#define HI3660_RST_SDIO 4
+#define HI3660_RST_UFS 5
+#define HI3660_RST_UFS_ASSERT 6
+#define HI3660_RST_PCIE_SYS 7
+#define HI3660_RST_PCIE_PHY 8
+#define HI3660_RST_PCIE_BUS 9
+#define HI3660_RST_USB3OTG_PHY 10
+#define HI3660_RST_USB3OTG 11
+#define HI3660_RST_USB3OTG_32K 12
+#define HI3660_RST_USB3OTG_AHB 13
+#define HI3660_RST_USB3OTG_MUX 14
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI3660*/
--
2.7.4
^ permalink raw reply related
* [PATCH 4/6] dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
.../devicetree/bindings/reset/hisilicon,hi6220-reset.txt | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
index c25da39..6a864f3 100644
--- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -9,10 +9,9 @@ hi6220 SoC.
Required properties:
- compatible: should be one of the following:
- - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
- - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
-- reg: should be register base and length as documented in the
- datasheet
+ - "hisilicon,hi6220-reset-sysctrl" : For peripheral reset controller.
+ - "hisilicon,hi6220-reset-mediactrl" : For media reset controller.
+- hisi,rst-syscon: phandle of the reset's syscon.
- #reset-cells: 1, see below
Example:
@@ -20,7 +19,12 @@ sys_ctrl: sys_ctrl at f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
+};
+
+sys_ctrl_rst: sys_rst_controller {
+ compatible = "hisilicon,hi6220-reset-sysctrl";
#reset-cells = <1>;
+ hisi,rst-syscon = <&sys_ctrl>;
};
Specifying reset lines connected to IP modules
@@ -29,7 +33,7 @@ example:
uart1: serial at ..... {
...
- resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
+ resets = <&sys_ctrl_rst PERIPH_RSTEN3_UART1>;
...
};
--
2.7.4
^ permalink raw reply related
* [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
Using new reset-hi6220 with common reset.c
And keeps the same reset define
dts hi6220.c should be updated with new node sys_ctrl_rst
Solving potential issue of sys_ctrl can not be used as clock and reset
at the same time.
sys_ctrl: sys_ctrl at f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
sys_ctrl_rst: sys_rst_controller {
compatible = "hisilicon,hi6220-reset-sysctrl";
#reset-cells = <1>;
hisi,rst-syscon = <&sys_ctrl>;
};
uart1: serial at ..... {
...
resets = <&sys_ctrl_rst PERIPH_RSTEN3_UART1>;
...
};
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/reset/hisilicon/Makefile | 2 +-
drivers/reset/hisilicon/hi6220_reset.c | 157 -------------------------
drivers/reset/hisilicon/reset-hi6220.c | 123 +++++++++++++++++++
include/dt-bindings/reset/hisi,hi6220-resets.h | 130 ++++++++++----------
4 files changed, 190 insertions(+), 222 deletions(-)
delete mode 100644 drivers/reset/hisilicon/hi6220_reset.c
create mode 100644 drivers/reset/hisilicon/reset-hi6220.c
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index 57e9893..caddac1 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1,3 +1,3 @@
obj-y += reset.o
obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
-obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
+obj-$(CONFIG_COMMON_RESET_HI6220) += reset-hi6220.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
deleted file mode 100644
index 35ce53e..0000000
--- a/drivers/reset/hisilicon/hi6220_reset.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Hisilicon Hi6220 reset controller driver
- *
- * Copyright (c) 2016 Linaro Limited.
- * Copyright (c) 2015-2016 Hisilicon Limited.
- *
- * Author: Feng Chen <puck.chen@hisilicon.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-#include <linux/reset-controller.h>
-#include <linux/reset.h>
-#include <linux/platform_device.h>
-
-#define PERIPH_ASSERT_OFFSET 0x300
-#define PERIPH_DEASSERT_OFFSET 0x304
-#define PERIPH_MAX_INDEX 0x509
-
-#define SC_MEDIA_RSTEN 0x052C
-#define SC_MEDIA_RSTDIS 0x0530
-#define MEDIA_MAX_INDEX 8
-
-#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
-
-enum hi6220_reset_ctrl_type {
- PERIPHERAL,
- MEDIA,
-};
-
-struct hi6220_reset_data {
- struct reset_controller_dev rc_dev;
- struct regmap *regmap;
-};
-
-static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev,
- unsigned long idx)
-{
- struct hi6220_reset_data *data = to_reset_data(rc_dev);
- struct regmap *regmap = data->regmap;
- u32 bank = idx >> 8;
- u32 offset = idx & 0xff;
- u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;
-
- return regmap_write(regmap, reg, BIT(offset));
-}
-
-static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev,
- unsigned long idx)
-{
- struct hi6220_reset_data *data = to_reset_data(rc_dev);
- struct regmap *regmap = data->regmap;
- u32 bank = idx >> 8;
- u32 offset = idx & 0xff;
- u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;
-
- return regmap_write(regmap, reg, BIT(offset));
-}
-
-static const struct reset_control_ops hi6220_peripheral_reset_ops = {
- .assert = hi6220_peripheral_assert,
- .deassert = hi6220_peripheral_deassert,
-};
-
-static int hi6220_media_assert(struct reset_controller_dev *rc_dev,
- unsigned long idx)
-{
- struct hi6220_reset_data *data = to_reset_data(rc_dev);
- struct regmap *regmap = data->regmap;
-
- return regmap_write(regmap, SC_MEDIA_RSTEN, BIT(idx));
-}
-
-static int hi6220_media_deassert(struct reset_controller_dev *rc_dev,
- unsigned long idx)
-{
- struct hi6220_reset_data *data = to_reset_data(rc_dev);
- struct regmap *regmap = data->regmap;
-
- return regmap_write(regmap, SC_MEDIA_RSTDIS, BIT(idx));
-}
-
-static const struct reset_control_ops hi6220_media_reset_ops = {
- .assert = hi6220_media_assert,
- .deassert = hi6220_media_deassert,
-};
-
-static int hi6220_reset_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- enum hi6220_reset_ctrl_type type;
- struct hi6220_reset_data *data;
- struct regmap *regmap;
-
- data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- type = (enum hi6220_reset_ctrl_type)of_device_get_match_data(dev);
-
- regmap = syscon_node_to_regmap(np);
- if (IS_ERR(regmap)) {
- dev_err(dev, "failed to get reset controller regmap\n");
- return PTR_ERR(regmap);
- }
-
- data->regmap = regmap;
- data->rc_dev.of_node = np;
- if (type == MEDIA) {
- data->rc_dev.ops = &hi6220_media_reset_ops;
- data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
- } else {
- data->rc_dev.ops = &hi6220_peripheral_reset_ops;
- data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
- }
-
- return reset_controller_register(&data->rc_dev);
-}
-
-static const struct of_device_id hi6220_reset_match[] = {
- {
- .compatible = "hisilicon,hi6220-sysctrl",
- .data = (void *)PERIPHERAL,
- },
- {
- .compatible = "hisilicon,hi6220-mediactrl",
- .data = (void *)MEDIA,
- },
- { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, hi6220_reset_match);
-
-static struct platform_driver hi6220_reset_driver = {
- .probe = hi6220_reset_probe,
- .driver = {
- .name = "reset-hi6220",
- .of_match_table = hi6220_reset_match,
- },
-};
-
-static int __init hi6220_reset_init(void)
-{
- return platform_driver_register(&hi6220_reset_driver);
-}
-
-postcore_initcall(hi6220_reset_init);
diff --git a/drivers/reset/hisilicon/reset-hi6220.c b/drivers/reset/hisilicon/reset-hi6220.c
new file mode 100644
index 0000000..a2a64ae
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi6220.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/reset/hisi,hi6220-resets.h>
+
+#include "reset.h"
+
+static const struct hisi_reset_channel_data hi6220_media_rst[] = {
+ [MEDIA_G3D] = HISI_RST_SEP(0x52c, 0),
+ [MEDIA_CODEC_VPU] = HISI_RST_SEP(0x52c, 2),
+ [MEDIA_CODEC_JPEG] = HISI_RST_SEP(0x52c, 3),
+ [MEDIA_ISP] = HISI_RST_SEP(0x52c, 4),
+ [MEDIA_ADE] = HISI_RST_SEP(0x52c, 5),
+ [MEDIA_MMU] = HISI_RST_SEP(0x52c, 6),
+ [MEDIA_XG2RAM1] = HISI_RST_SEP(0x52c, 7),
+};
+
+static struct hisi_reset_controller_data hi6220_media_controller = {
+ .nr_channels = ARRAY_SIZE(hi6220_media_rst),
+ .channels = hi6220_media_rst,
+};
+
+static const struct hisi_reset_channel_data hi6220_sysctrl_rst[] = {
+ [PERIPH_RSTDIS0_MMC0] = HISI_RST_SEP(0x300, 0),
+ [PERIPH_RSTDIS0_MMC1] = HISI_RST_SEP(0x300, 1),
+ [PERIPH_RSTDIS0_MMC2] = HISI_RST_SEP(0x300, 2),
+ [PERIPH_RSTDIS0_NANDC] = HISI_RST_SEP(0x300, 3),
+ [PERIPH_RSTDIS0_USBOTG_BUS] = HISI_RST_SEP(0x300, 4),
+ [PERIPH_RSTDIS0_POR_PICOPHY] = HISI_RST_SEP(0x300, 5),
+ [PERIPH_RSTDIS0_USBOTG] = HISI_RST_SEP(0x300, 6),
+ [PERIPH_RSTDIS0_USBOTG_32K] = HISI_RST_SEP(0x300, 7),
+ [PERIPH_RSTDIS1_HIFI] = HISI_RST_SEP(0x310, 0),
+ [PERIPH_RSTDIS1_DIGACODEC] = HISI_RST_SEP(0x310, 5),
+ [PERIPH_RSTEN2_IPF] = HISI_RST_SEP(0x320, 0),
+ [PERIPH_RSTEN2_SOCP] = HISI_RST_SEP(0x320, 1),
+ [PERIPH_RSTEN2_DMAC] = HISI_RST_SEP(0x320, 2),
+ [PERIPH_RSTEN2_SECENG] = HISI_RST_SEP(0x320, 3),
+ [PERIPH_RSTEN2_ABB] = HISI_RST_SEP(0x320, 4),
+ [PERIPH_RSTEN2_HPM0] = HISI_RST_SEP(0x320, 5),
+ [PERIPH_RSTEN2_HPM1] = HISI_RST_SEP(0x320, 6),
+ [PERIPH_RSTEN2_HPM2] = HISI_RST_SEP(0x320, 7),
+ [PERIPH_RSTEN2_HPM3] = HISI_RST_SEP(0x320, 8),
+ [PERIPH_RSTEN3_CSSYS] = HISI_RST_SEP(0x330, 0),
+ [PERIPH_RSTEN3_I2C0] = HISI_RST_SEP(0x330, 1),
+ [PERIPH_RSTEN3_I2C1] = HISI_RST_SEP(0x330, 2),
+ [PERIPH_RSTEN3_I2C2] = HISI_RST_SEP(0x330, 3),
+ [PERIPH_RSTEN3_I2C3] = HISI_RST_SEP(0x330, 4),
+ [PERIPH_RSTEN3_UART1] = HISI_RST_SEP(0x330, 5),
+ [PERIPH_RSTEN3_UART2] = HISI_RST_SEP(0x330, 6),
+ [PERIPH_RSTEN3_UART3] = HISI_RST_SEP(0x330, 7),
+ [PERIPH_RSTEN3_UART4] = HISI_RST_SEP(0x330, 8),
+ [PERIPH_RSTEN3_SSP] = HISI_RST_SEP(0x330, 9),
+ [PERIPH_RSTEN3_PWM] = HISI_RST_SEP(0x330, 10),
+ [PERIPH_RSTEN3_BLPWM] = HISI_RST_SEP(0x330, 11),
+ [PERIPH_RSTEN3_TSENSOR] = HISI_RST_SEP(0x330, 12),
+ [PERIPH_RSTEN3_DAPB] = HISI_RST_SEP(0x330, 18),
+ [PERIPH_RSTEN3_HKADC] = HISI_RST_SEP(0x330, 19),
+ [PERIPH_RSTEN3_CODEC_SSI] = HISI_RST_SEP(0x330, 20),
+ [PERIPH_RSTEN8_RS0] = HISI_RST_SEP(0x340, 0),
+ [PERIPH_RSTEN8_RS2] = HISI_RST_SEP(0x340, 1),
+ [PERIPH_RSTEN8_RS3] = HISI_RST_SEP(0x340, 2),
+ [PERIPH_RSTEN8_MS0] = HISI_RST_SEP(0x340, 3),
+ [PERIPH_RSTEN8_MS2] = HISI_RST_SEP(0x340, 5),
+ [PERIPH_RSTEN8_XG2RAM0] = HISI_RST_SEP(0x340, 6),
+ [PERIPH_RSTEN8_X2SRAM_TZMA] = HISI_RST_SEP(0x340, 7),
+ [PERIPH_RSTEN8_SRAM] = HISI_RST_SEP(0x340, 8),
+ [PERIPH_RSTEN8_HARQ] = HISI_RST_SEP(0x340, 10),
+ [PERIPH_RSTEN8_DDRC] = HISI_RST_SEP(0x340, 12),
+ [PERIPH_RSTEN8_DDRC_APB] = HISI_RST_SEP(0x340, 13),
+ [PERIPH_RSTEN8_DDRPACK_APB] = HISI_RST_SEP(0x340, 14),
+ [PERIPH_RSTEN8_DDRT] = HISI_RST_SEP(0x340, 17),
+ [PERIPH_RSDIST9_CARM_DAP] = HISI_RST_SEP(0x350, 0),
+ [PERIPH_RSDIST9_CARM_ATB] = HISI_RST_SEP(0x350, 1),
+ [PERIPH_RSDIST9_CARM_LBUS] = HISI_RST_SEP(0x350, 2),
+ [PERIPH_RSDIST9_CARM_POR] = HISI_RST_SEP(0x350, 3),
+ [PERIPH_RSDIST9_CARM_CORE] = HISI_RST_SEP(0x350, 4),
+ [PERIPH_RSDIST9_CARM_DBG] = HISI_RST_SEP(0x350, 5),
+ [PERIPH_RSDIST9_CARM_L2] = HISI_RST_SEP(0x350, 6),
+ [PERIPH_RSDIST9_CARM_SOCDBG] = HISI_RST_SEP(0x350, 7),
+ [PERIPH_RSDIST9_CARM_ETM] = HISI_RST_SEP(0x350, 8),
+};
+
+static struct hisi_reset_controller_data hi6220_sysctrl_controller = {
+ .nr_channels = ARRAY_SIZE(hi6220_sysctrl_rst),
+ .channels = hi6220_sysctrl_rst,
+};
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-reset-sysctrl",
+ .data = &hi6220_sysctrl_controller, },
+ { .compatible = "hisilicon,hi6220-reset-mediactrl",
+ .data = &hi6220_media_controller, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hi6220_reset_match);
+
+static struct platform_driver hi6220_reset_driver = {
+ .probe = hisi_reset_probe,
+ .driver = {
+ .name = "reset-hi6220",
+ .of_match_table = hi6220_reset_match,
+ },
+};
+
+static int __init hi6220_reset_init(void)
+{
+ return platform_driver_register(&hi6220_reset_driver);
+}
+arch_initcall(hi6220_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi6220-reset");
+MODULE_DESCRIPTION("HiSilicon hi6220 Reset Driver");
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
index 322ec53..837f1a1 100644
--- a/include/dt-bindings/reset/hisi,hi6220-resets.h
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -5,71 +5,73 @@
#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
-#define PERIPH_RSTDIS0_MMC0 0x000
-#define PERIPH_RSTDIS0_MMC1 0x001
-#define PERIPH_RSTDIS0_MMC2 0x002
-#define PERIPH_RSTDIS0_NANDC 0x003
-#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
-#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
-#define PERIPH_RSTDIS0_USBOTG 0x006
-#define PERIPH_RSTDIS0_USBOTG_32K 0x007
-#define PERIPH_RSTDIS1_HIFI 0x100
-#define PERIPH_RSTDIS1_DIGACODEC 0x105
-#define PERIPH_RSTEN2_IPF 0x200
-#define PERIPH_RSTEN2_SOCP 0x201
-#define PERIPH_RSTEN2_DMAC 0x202
-#define PERIPH_RSTEN2_SECENG 0x203
-#define PERIPH_RSTEN2_ABB 0x204
-#define PERIPH_RSTEN2_HPM0 0x205
-#define PERIPH_RSTEN2_HPM1 0x206
-#define PERIPH_RSTEN2_HPM2 0x207
-#define PERIPH_RSTEN2_HPM3 0x208
-#define PERIPH_RSTEN3_CSSYS 0x300
-#define PERIPH_RSTEN3_I2C0 0x301
-#define PERIPH_RSTEN3_I2C1 0x302
-#define PERIPH_RSTEN3_I2C2 0x303
-#define PERIPH_RSTEN3_I2C3 0x304
-#define PERIPH_RSTEN3_UART1 0x305
-#define PERIPH_RSTEN3_UART2 0x306
-#define PERIPH_RSTEN3_UART3 0x307
-#define PERIPH_RSTEN3_UART4 0x308
-#define PERIPH_RSTEN3_SSP 0x309
-#define PERIPH_RSTEN3_PWM 0x30a
-#define PERIPH_RSTEN3_BLPWM 0x30b
-#define PERIPH_RSTEN3_TSENSOR 0x30c
-#define PERIPH_RSTEN3_DAPB 0x312
-#define PERIPH_RSTEN3_HKADC 0x313
-#define PERIPH_RSTEN3_CODEC_SSI 0x314
-#define PERIPH_RSTEN3_PMUSSI1 0x316
-#define PERIPH_RSTEN8_RS0 0x400
-#define PERIPH_RSTEN8_RS2 0x401
-#define PERIPH_RSTEN8_RS3 0x402
-#define PERIPH_RSTEN8_MS0 0x403
-#define PERIPH_RSTEN8_MS2 0x405
-#define PERIPH_RSTEN8_XG2RAM0 0x406
-#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
-#define PERIPH_RSTEN8_SRAM 0x408
-#define PERIPH_RSTEN8_HARQ 0x40a
-#define PERIPH_RSTEN8_DDRC 0x40c
-#define PERIPH_RSTEN8_DDRC_APB 0x40d
-#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
-#define PERIPH_RSTEN8_DDRT 0x411
-#define PERIPH_RSDIST9_CARM_DAP 0x500
-#define PERIPH_RSDIST9_CARM_ATB 0x501
-#define PERIPH_RSDIST9_CARM_LBUS 0x502
-#define PERIPH_RSDIST9_CARM_POR 0x503
-#define PERIPH_RSDIST9_CARM_CORE 0x504
-#define PERIPH_RSDIST9_CARM_DBG 0x505
-#define PERIPH_RSDIST9_CARM_L2 0x506
-#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
-#define PERIPH_RSDIST9_CARM_ETM 0x508
+/* reset in sysctrl */
+#define PERIPH_RSTDIS0_MMC0 0
+#define PERIPH_RSTDIS0_MMC1 1
+#define PERIPH_RSTDIS0_MMC2 2
+#define PERIPH_RSTDIS0_NANDC 3
+#define PERIPH_RSTDIS0_USBOTG_BUS 4
+#define PERIPH_RSTDIS0_POR_PICOPHY 5
+#define PERIPH_RSTDIS0_USBOTG 6
+#define PERIPH_RSTDIS0_USBOTG_32K 7
+#define PERIPH_RSTDIS1_HIFI 8
+#define PERIPH_RSTDIS1_DIGACODEC 9
+#define PERIPH_RSTEN2_IPF 10
+#define PERIPH_RSTEN2_SOCP 11
+#define PERIPH_RSTEN2_DMAC 12
+#define PERIPH_RSTEN2_SECENG 13
+#define PERIPH_RSTEN2_ABB 14
+#define PERIPH_RSTEN2_HPM0 15
+#define PERIPH_RSTEN2_HPM1 16
+#define PERIPH_RSTEN2_HPM2 17
+#define PERIPH_RSTEN2_HPM3 18
+#define PERIPH_RSTEN3_CSSYS 19
+#define PERIPH_RSTEN3_I2C0 20
+#define PERIPH_RSTEN3_I2C1 21
+#define PERIPH_RSTEN3_I2C2 22
+#define PERIPH_RSTEN3_I2C3 23
+#define PERIPH_RSTEN3_UART1 24
+#define PERIPH_RSTEN3_UART2 25
+#define PERIPH_RSTEN3_UART3 26
+#define PERIPH_RSTEN3_UART4 27
+#define PERIPH_RSTEN3_SSP 28
+#define PERIPH_RSTEN3_PWM 29
+#define PERIPH_RSTEN3_BLPWM 30
+#define PERIPH_RSTEN3_TSENSOR 31
+#define PERIPH_RSTEN3_DAPB 32
+#define PERIPH_RSTEN3_HKADC 33
+#define PERIPH_RSTEN3_CODEC_SSI 34
+#define PERIPH_RSTEN8_RS0 35
+#define PERIPH_RSTEN8_RS2 36
+#define PERIPH_RSTEN8_RS3 37
+#define PERIPH_RSTEN8_MS0 38
+#define PERIPH_RSTEN8_MS2 39
+#define PERIPH_RSTEN8_XG2RAM0 40
+#define PERIPH_RSTEN8_X2SRAM_TZMA 41
+#define PERIPH_RSTEN8_SRAM 42
+#define PERIPH_RSTEN8_HARQ 43
+#define PERIPH_RSTEN8_DDRC 44
+#define PERIPH_RSTEN8_DDRC_APB 45
+#define PERIPH_RSTEN8_DDRPACK_APB 46
+#define PERIPH_RSTEN8_DDRT 47
+#define PERIPH_RSDIST9_CARM_DAP 48
+#define PERIPH_RSDIST9_CARM_ATB 49
+#define PERIPH_RSDIST9_CARM_LBUS 50
+#define PERIPH_RSDIST9_CARM_POR 51
+#define PERIPH_RSDIST9_CARM_CORE 52
+#define PERIPH_RSDIST9_CARM_DBG 53
+#define PERIPH_RSDIST9_CARM_L2 54
+#define PERIPH_RSDIST9_CARM_SOCDBG 55
+#define PERIPH_RSDIST9_CARM_ETM 56
+
+/* reset in media */
#define MEDIA_G3D 0
-#define MEDIA_CODEC_VPU 2
-#define MEDIA_CODEC_JPEG 3
-#define MEDIA_ISP 4
-#define MEDIA_ADE 5
-#define MEDIA_MMU 6
-#define MEDIA_XG2RAM1 7
+#define MEDIA_CODEC_VPU 1
+#define MEDIA_CODEC_JPEG 2
+#define MEDIA_ISP 3
+#define MEDIA_ADE 4
+#define MEDIA_MMU 5
+#define MEDIA_XG2RAM1 6
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
--
2.7.4
^ permalink raw reply related
* [PATCH 6/6] arm64: dts: hi6220: update reset node according to reset-hi6220.c
From: Zhangfei Gao @ 2016-11-22 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 17839db..7918043 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -246,14 +246,24 @@
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
- #reset-cells = <1>;
};
media_ctrl: media_ctrl at f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
+ };
+
+ sys_ctrl_rst: sys_rst_controller {
+ compatible = "hisilicon,hi6220-reset-sysctrl";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&sys_ctrl>;
+ };
+
+ media_ctrl_rst: media_rst_controller {
+ compatible = "hisilicon,hi6220-reset-mediactrl";
#reset-cells = <1>;
+ hisi,rst-syscon = <&media_ctrl>;
};
pm_ctrl: pm_ctrl at f7032000 {
@@ -771,7 +781,7 @@
interrupts = <0x0 0x48 0x4>;
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
+ resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC0>;
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
pinctrl-names = "default";
@@ -794,7 +804,7 @@
#size-cells = <0x0>;
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
+ resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC1>;
vqmmc-supply = <&ldo7>;
vmmc-supply = <&ldo10>;
bus-width = <0x4>;
@@ -812,7 +822,7 @@
interrupts = <0x0 0x4a 0x4>;
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
clock-names = "ciu", "biu";
- resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
+ resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC2>;
bus-width = <0x4>;
broken-cd;
pinctrl-names = "default", "idle";
@@ -867,7 +877,7 @@
reg = <0x0 0xf4100000 0x0 0x7800>;
reg-names = "ade_base";
hisilicon,noc-syscon = <&medianoc_ade>;
- resets = <&media_ctrl MEDIA_ADE>;
+ resets = <&media_ctrl_rst MEDIA_ADE>;
interrupts = <0 115 4>; /* ldi interrupt */
clocks = <&media_ctrl HI6220_ADE_CORE>,
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] MAINTAINERS: Add myself as co-maintainer to fpga mgr framework.
From: Greg Kroah-Hartman @ 2016-11-22 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <47eb36a7-ee48-53bd-fbdc-15225c3147ec@xilinx.com>
On Tue, Nov 22, 2016 at 08:48:57AM +0100, Michal Simek wrote:
> On 22.11.2016 03:29, atull wrote:
> > On Mon, 21 Nov 2016, Moritz Fischer wrote:
> >
> >> Add myself as co-maintainer to fpga mgr framework.
> >>
> >> Signed-off-by: Moritz Fischer <mdf@kernel.org>
> >> Cc: Alan Tull <atull@opensource.altera.com>
> >> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> >> Cc: linux-kernel at vger.kernel.org
> >> Cc: linux-fpga at vger.kernel.org
> >> ---
> >> Hi all,
> >>
> >> Lately we've fallen behind a bit on reviewing patches lately.
> >
> > Hi Moritz,
> >
> > drivers/fpga has been in the upstream kernel a year now. Most of that
> > time, traffic has been very slow. Recently we had more traffic while
> > I was travelling and moving to a new office, both cases leaving me
> > with bad network connectivity. Things will probably return to normal.
> > I appreciate your passion and all your effort reviewing stuff. I
> > don't see a need for two maintainers at this point.
>
> TBH. I think it is not a bad option. I do normally have backup person
> for all repos I do maintain. It doesn't mean that second maintainer does
> something but it has all accesses to repos you maintain.
> It means if something really happens to you (hopefully not) than this
> person can continue in this work without any delay which is not a bad
> thing.
> It is really just about talking to each other what that second person
> will do - probably just review patches as is done now. You can also
> learn from each other.
> I would like to be involved more in this but unfortunately I don't have
> enough time to do it properly.
>
> Regarding maintaining this repo. It is just standard process. Apply
> sensible things, well described and test it. And then send pull request
> to Greg based on signed tags and you are done.
> Greg should told you what should be the base which you should use for
> pull request. Someone is taking patches based on rc1 tag, someone is
> rebasing it on the final tag.
Greg doesn't care what base you use, as long as you don't rebase
patches. What subsystem does that? I need to go yell at someone...
And I take patches just as easily, what ever works best for the
subsystem.
thanks,
greg k-h
^ permalink raw reply
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