* [PATCH v2 0/5] arm: spear6xx: DT cleanups and improvements
From: Viresh Kumar @ 2017-04-17 7:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170417091016.1f0732a9@free-electrons.com>
On 17-04-17, 09:10, Thomas Petazzoni wrote:
> Hello,
>
> On Mon, 17 Apr 2017 09:36:55 +0530, Viresh Kumar wrote:
>
> > Yes, that would be the normal flow and I did that initially. But then the number
> > of patches really decreased and its better to send the patches directly to ARM
> > maintainers so that they can apply them. No need of PULL requests really.
> >
> > Send them to: arm-soc <arm@kernel.org>
>
> OK, thanks. I more recently sent two other SPEAr600 patches, one adding
> the ADC to the DT, one fixing the clock driver for the ADC clock.
>
> Could you have a look at them, and hopefully give your Acked-by, so
> that I can get send them to arm-soc at the same time?
Already done this morning.
--
viresh
^ permalink raw reply
* [PATCH v2 0/5] arm: spear6xx: DT cleanups and improvements
From: Thomas Petazzoni @ 2017-04-17 7:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170417040655.GA28191@vireshk-i7>
Hello,
On Mon, 17 Apr 2017 09:36:55 +0530, Viresh Kumar wrote:
> Yes, that would be the normal flow and I did that initially. But then the number
> of patches really decreased and its better to send the patches directly to ARM
> maintainers so that they can apply them. No need of PULL requests really.
>
> Send them to: arm-soc <arm@kernel.org>
OK, thanks. I more recently sent two other SPEAr600 patches, one adding
the ADC to the DT, one fixing the clock driver for the ADC clock.
Could you have a look at them, and hopefully give your Acked-by, so
that I can get send them to arm-soc at the same time?
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
From: Hoegeun Kwon @ 2017-04-17 6:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492408934-22096-1-git-send-email-hoegeun.kwon@samsung.com>
This patch add the panel device tree node for s6e3hf2 display
controller to TM2e dts.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 694717a..98ad094 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -52,6 +52,18 @@
assigned-clock-rates = <278000000>, <400000000>;
};
+&dsi {
+ panel at 0 {
+ compatible = "samsung,s6e3hf2";
+ reg = <0>;
+ vdd3-supply = <&ldo27_reg>;
+ vci-supply = <&ldo28_reg>;
+ reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
+ te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&ldo31_reg {
regulator-name = "TSP_VDD_1.8V_AP";
regulator-min-microvolt = <1800000>;
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/3] drm/panel: s6e3ha2: Add support for s6e3hf2 panel on TM2e board
From: Hoegeun Kwon @ 2017-04-17 6:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492408934-22096-1-git-send-email-hoegeun.kwon@samsung.com>
This patch supports TM2e panel and the panel has 1600x2560 resolution
in 5.65" physical.
This identify panel type with compatibility string, also invoke
display mode that matches the type. So add the check code for s6e3ha2
compatibility and s6e3hf2 type and select the drm_display_mode of
default and edge type.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c | 64 ++++++++++++++++++++++++---
1 file changed, 57 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
index 4cc08d7..c7b418b 100644
--- a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
+++ b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c
@@ -16,6 +16,7 @@
#include <drm/drm_panel.h>
#include <linux/backlight.h>
#include <linux/gpio/consumer.h>
+#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#define S6E3HA2_MIN_BRIGHTNESS 0
@@ -218,6 +219,16 @@
0x1d, 0x1e, 0x1f, 0x20, 0x21
};
+enum s6e3ha2_type {
+ HA2_TYPE,
+ HF2_TYPE,
+};
+
+struct s6e3ha2_panel_desc {
+ const struct drm_display_mode *mode;
+ enum s6e3ha2_type type;
+};
+
struct s6e3ha2 {
struct device *dev;
struct drm_panel panel;
@@ -226,6 +237,8 @@ struct s6e3ha2 {
struct regulator_bulk_data supplies[2];
struct gpio_desc *reset_gpio;
struct gpio_desc *enable_gpio;
+
+ const struct s6e3ha2_panel_desc *desc;
};
static int s6e3ha2_dcs_write(struct s6e3ha2 *ctx, const void *data, size_t len)
@@ -283,11 +296,19 @@ static int s6e3ha2_single_dsi_set(struct s6e3ha2 *ctx)
static int s6e3ha2_freq_calibration(struct s6e3ha2 *ctx)
{
s6e3ha2_dcs_write_seq_static(ctx, 0xfd, 0x1c);
+ if (ctx->desc->type == HF2_TYPE)
+ s6e3ha2_dcs_write_seq_static(ctx, 0xf2, 0x67, 0x40, 0xc5);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x20, 0x39);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0xa0);
s6e3ha2_dcs_write_seq_static(ctx, 0xfe, 0x20);
- s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x12, 0x62, 0x40,
- 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+
+ if (ctx->desc->type == HA2_TYPE)
+ s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x12, 0x62,
+ 0x40, 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+ else
+ s6e3ha2_dcs_write_seq_static(ctx, 0xce, 0x03, 0x3b, 0x14, 0x6d,
+ 0x40, 0x80, 0xc0, 0x28, 0x28, 0x28, 0x28, 0x39, 0xc5);
+
return 0;
}
@@ -583,7 +604,7 @@ static int s6e3ha2_enable(struct drm_panel *panel)
return 0;
}
-static const struct drm_display_mode default_mode = {
+static const struct drm_display_mode s6e3ha2_mode = {
.clock = 222372,
.hdisplay = 1440,
.hsync_start = 1440 + 1,
@@ -597,16 +618,41 @@ static int s6e3ha2_enable(struct drm_panel *panel)
.flags = 0,
};
+static const struct s6e3ha2_panel_desc samsung_s6e3ha2 = {
+ .mode = &s6e3ha2_mode,
+ .type = HA2_TYPE,
+};
+
+static const struct drm_display_mode s6e3hf2_mode = {
+ .clock = 247856,
+ .hdisplay = 1600,
+ .hsync_start = 1600 + 1,
+ .hsync_end = 1600 + 1 + 1,
+ .htotal = 1600 + 1 + 1 + 1,
+ .vdisplay = 2560,
+ .vsync_start = 2560 + 1,
+ .vsync_end = 2560 + 1 + 1,
+ .vtotal = 2560 + 1 + 1 + 15,
+ .vrefresh = 60,
+ .flags = 0,
+};
+
+static const struct s6e3ha2_panel_desc samsung_s6e3hf2 = {
+ .mode = &s6e3hf2_mode,
+ .type = HF2_TYPE,
+};
+
static int s6e3ha2_get_modes(struct drm_panel *panel)
{
struct drm_connector *connector = panel->connector;
+ struct s6e3ha2 *ctx = container_of(panel, struct s6e3ha2, panel);
struct drm_display_mode *mode;
- mode = drm_mode_duplicate(panel->drm, &default_mode);
+ mode = drm_mode_duplicate(panel->drm, ctx->desc->mode);
if (!mode) {
DRM_ERROR("failed to add mode %ux%ux@%u\n",
- default_mode.hdisplay, default_mode.vdisplay,
- default_mode.vrefresh);
+ ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
+ ctx->desc->mode->vrefresh);
return -ENOMEM;
}
@@ -642,6 +688,7 @@ static int s6e3ha2_probe(struct mipi_dsi_device *dsi)
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dev = dev;
+ ctx->desc = of_device_get_match_data(dev);
dsi->lanes = 4;
dsi->format = MIPI_DSI_FMT_RGB888;
@@ -717,7 +764,10 @@ static int s6e3ha2_remove(struct mipi_dsi_device *dsi)
}
static const struct of_device_id s6e3ha2_of_match[] = {
- { .compatible = "samsung,s6e3ha2" },
+ { .compatible = "samsung,s6e3ha2",
+ .data = &samsung_s6e3ha2 },
+ { .compatible = "samsung,s6e3hf2",
+ .data = &samsung_s6e3hf2 },
{ }
};
MODULE_DEVICE_TABLE(of, s6e3ha2_of_match);
--
1.9.1
^ permalink raw reply related
* [PATCH v2 1/3] dt-bindings: Add support for samsung s6e3hf2 panel
From: Hoegeun Kwon @ 2017-04-17 6:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492408934-22096-1-git-send-email-hoegeun.kwon@samsung.com>
The samsung s6e3hf2 panel is a 5.65" 1600x2560 AMOLED panel connected
using MIPI-DSI interfaces.
The s6e3hf2 is add to samsung,s6e3ha2.txt binding because it is a
panel similar to the s6e3ha2. So add the compatible string and
comments.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
---
Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt b/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt
index 18854f4..4acea25 100644
--- a/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt
+++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e3ha2.txt
@@ -1,7 +1,10 @@
Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel
+Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel
Required properties:
- - compatible: "samsung,s6e3ha2"
+ - compatible: should be one of:
+ "samsung,s6e3ha2",
+ "samsung,s6e3hf2".
- reg: the virtual channel number of a DSI peripheral
- vdd3-supply: I/O voltage supply
- vci-supply: voltage supply for analog circuits
--
1.9.1
^ permalink raw reply related
* [PATCH v2 0/3] Add support for the S6E3HF2 panel on TM2e board
From: Hoegeun Kwon @ 2017-04-17 6:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CGME20170417060217epcas1p167d86ba0e12d461efbab67b0014fa1d2@epcas1p1.samsung.com>
Hi all,
First, thanks for Andrzej review.
The purpose of this patch is add support for s6e3hf2 AMOLED panel on
the TM2e board. The panel has 1600x2560 resolution in 5.65" physical
panel in the TM2e device.
The s6e3hf2 panel(5.65") is simliar to the previous s6e3ha2 panel(5.7"),
but resolution and some command message are different. So it can be
distinguished as a compatiblitiy string.
Best regards,
Hoegeun
Changes for V2:
- Add new compatible string to "samsung,s6e3ha2.txt binding with comments.
- Fix the panel name from s6e3ha2-e to s6e3hf2
Hoegeun Kwon (3):
dt-bindings: Add support for samsung s6e3hf2 panel
drm/panel: s6e3ha2: Add support for s6e3hf2 panel on TM2e board
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
.../bindings/display/panel/samsung,s6e3ha2.txt | 5 +-
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 12 ++++
drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c | 64 +++++++++++++++++++---
3 files changed, 73 insertions(+), 8 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 0/2] ADC support for SPEAr600
From: Viresh Kumar @ 2017-04-17 4:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492203072-27771-1-git-send-email-thomas.petazzoni@free-electrons.com>
On 14-04-17, 22:51, Thomas Petazzoni wrote:
> Hello,
>
> This set of two patches add support for the ADC of the SPEAr600, using
> the existing spear_adc driver. Only a Device Tree description and a
> minor clock fix are needed to make the ADC work.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Please send them to arm-soc as well.
--
viresh
^ permalink raw reply
* [PATCH v2 0/5] arm: spear6xx: DT cleanups and improvements
From: Viresh Kumar @ 2017-04-17 4:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170414224715.4493109a@free-electrons.com>
On 14-04-17, 22:47, Thomas Petazzoni wrote:
> Thanks! However, unless I'm missing something, I don't see these
> changes in linux-next. Who is going to apply them and send a pull
> request to arm-soc? You're listed as one the maintainers for SPEAr, so
> I was assuming you would do it. Is this correct?
>
> Let me know if there's anything to be done on my side to get those
> patches merged.
Yes, that would be the normal flow and I did that initially. But then the number
of patches really decreased and its better to send the patches directly to ARM
maintainers so that they can apply them. No need of PULL requests really.
Send them to: arm-soc <arm@kernel.org>
--
viresh
^ permalink raw reply
* [PATCH v1 1/1] mtd: mtk-nor: set controller's address width according to nor flash
From: Guochun Mao @ 2017-04-17 3:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e78dba15-80d0-f2c3-c963-a7eb033af58d@wedev4u.fr>
Hi Cyrille,
On Sun, 2017-04-16 at 19:18 +0200, Cyrille Pitchen wrote:
> Le 13/04/2017 ? 10:24, Cyrille Pitchen a ?crit :
> > Hi Guochun,
> >
> > Le 13/04/2017 ? 04:40, Guochun Mao a ?crit :
> >> Hi Cyrille,
> >>
> >> On Wed, 2017-04-12 at 22:57 +0200, Cyrille Pitchen wrote:
> >>> Hi Guochun,
> >>>
> >>> Le 05/04/2017 ? 10:37, Guochun Mao a ?crit :
> >>>> When nor's size larger than 16MByte, nor's address width maybe
> >>>> set to 3 or 4, and controller should change address width according
> >>>> to nor's setting.
> >>>>
> >>>> Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>st
> >
> > Acked-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
> >
>
> Applied to github/spi-nor
Thank you very much!
Best regards,
Guochun
^ permalink raw reply
* [PATCH V5 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G
From: Chunyan Zhang @ 2017-04-17 3:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1490599960-27330-1-git-send-email-chunyan.zhang@spreadtrum.com>
Hi Arnd,
Could you please take this patch through arm-soc git if there are no
further comments? (The three other patches in this series have been
taken by Greg.)
Thanks,
Chunyan
On 27 March 2017 at 15:32, Chunyan Zhang <chunyan.zhang@spreadtrum.com> wrote:
> From: Orson Zhai <orson.zhai@spreadtrum.com>
>
> SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum.
>
> According to regular hierarchy of sprd dts, whale2.dtsi contains SoC
> peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
> and sp9860g dts is for the board level.
>
> Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com>
> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> arch/arm64/boot/dts/sprd/Makefile | 3 +-
> arch/arm64/boot/dts/sprd/sc9860.dtsi | 569 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 56 +++
> arch/arm64/boot/dts/sprd/whale2.dtsi | 71 ++++
> 4 files changed, 698 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/sprd/sc9860.dtsi
> create mode 100644 arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> create mode 100644 arch/arm64/boot/dts/sprd/whale2.dtsi
>
> diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
> index b658c5e..f0535e6 100644
> --- a/arch/arm64/boot/dts/sprd/Makefile
> +++ b/arch/arm64/boot/dts/sprd/Makefile
> @@ -1,4 +1,5 @@
> -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
> +dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
> + sp9860g-1h10.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> new file mode 100644
> index 0000000..7b7d8ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> @@ -0,0 +1,569 @@
> +/*
> + * Spreadtrum SC9860 SoC
> + *
> + * Copyright (C) 2016, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "whale2.dtsi"
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + core1 {
> + cpu = <&CPU1>;
> + };
> + core2 {
> + cpu = <&CPU2>;
> + };
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> + core1 {
> + cpu = <&CPU5>;
> + };
> + core2 {
> + cpu = <&CPU6>;
> + };
> + core3 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + CPU0: cpu at 530000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU1: cpu at 530001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU2: cpu at 530002 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530002>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU3: cpu at 530003 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530003>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU4: cpu at 530100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU5: cpu at 530101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU6: cpu at 530102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530102>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU7: cpu at 530103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530103>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> + };
> +
> + idle-states{
> + entry-method = "arm,psci";
> +
> + CORE_PD: core_pd {
> + compatible = "arm,idle-state";
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2500>;
> + local-timer-stop;
> + arm,psci-suspend-param = <0x00010002>;
> + };
> +
> + CLUSTER_PD: cluster_pd {
> + compatible = "arm,idle-state";
> + entry-latency-us = <1000>;
> + exit-latency-us = <1000>;
> + min-residency-us = <3000>;
> + local-timer-stop;
> + arm,psci-suspend-param = <0x01010003>;
> + };
> + };
> +
> + gic: interrupt-controller at 12001000 {
> + compatible = "arm,gic-400";
> + reg = <0 0x12001000 0 0x1000>,
> + <0 0x12002000 0 0x2000>,
> + <0 0x12004000 0 0x2000>,
> + <0 0x12006000 0 0x2000>;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&CPU0>,
> + <&CPU1>,
> + <&CPU2>,
> + <&CPU3>,
> + <&CPU4>,
> + <&CPU5>,
> + <&CPU6>,
> + <&CPU7>;
> + };
> +
> + soc {
> + funnel at 10001000 { /* SoC Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x10001000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + soc_funnel_out_port: endpoint {
> + remote-endpoint = <&etb_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + soc_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&main_funnel_out_port>;
> + };
> + };
> +
> + port at 2 {
> + reg = <4>;
> + soc_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpioint =
> + <&stm_out_port>;
> + };
> + };
> + };
> + };
> +
> + etb at 10003000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x10003000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + port {
> + etb_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&soc_funnel_out_port>;
> + };
> + };
> + };
> +
> + stm at 10006000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x10006000 0 0x1000>,
> + <0 0x01000000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + port {
> + stm_out_port: endpoint {
> + remote-endpoint =
> + <&soc_funnel_in_port1>;
> + };
> + };
> + };
> +
> + funnel at 11001000 { /* Cluster0 Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> +
> + port at 3 {
> + reg = <2>;
> + cluster0_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> +
> + port at 4 {
> + reg = <4>;
> + cluster0_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + };
> + };
> +
> + funnel at 11002000 { /* Cluster1 Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11002000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm4_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm5_out>;
> + };
> + };
> +
> + port at 3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm6_out>;
> + };
> + };
> +
> + port at 4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + etf at 11003000 { /* ETF on Cluster0 */
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x11003000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster0_etf_out: endpoint {
> + remote-endpoint =
> + <&main_funnel_in_port0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster0_etf_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster0_funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> + etf at 11004000 { /* ETF on Cluster1 */
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x11004000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster1_etf_out: endpoint {
> + remote-endpoint =
> + <&main_funnel_in_port1>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster1_etf_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster1_funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> + funnel at 11005000 { /* Main Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11005000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&soc_funnel_in_port0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster0_etf_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster1_etf_out>;
> + };
> + };
> + };
> + };
> +
> + etm at 11440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11440000 0 0x1000>;
> + cpu = <&CPU0>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm at 11540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11540000 0 0x1000>;
> + cpu = <&CPU1>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm at 11640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11640000 0 0x1000>;
> + cpu = <&CPU2>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm at 11740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11740000 0 0x1000>;
> + cpu = <&CPU3>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port3>;
> + };
> + };
> + };
> +
> + etm at 11840000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11840000 0 0x1000>;
> + cpu = <&CPU4>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm at 11940000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11940000 0 0x1000>;
> + cpu = <&CPU5>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm at 11a40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11a40000 0 0x1000>;
> + cpu = <&CPU6>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm at 11b40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11b40000 0 0x1000>;
> + cpu = <&CPU7>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> new file mode 100644
> index 0000000..ae0b28c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> @@ -0,0 +1,56 @@
> +/*
> + * Spreadtrum SP9860g board
> + *
> + * Copyright (C) 2017, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/dts-v1/;
> +
> +#include "sc9860.dtsi"
> +
> +/ {
> + model = "Spreadtrum SP9860G 3GFHD Board";
> +
> + compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
> +
> + aliases {
> + serial0 = &uart0; /* for Bluetooth */
> + serial1 = &uart1; /* UART console */
> + serial2 = &uart2; /* Reserved */
> + serial3 = &uart3; /* for GPS */
> + };
> +
> + memory{
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x60000000>,
> + <0x1 0x80000000 0 0x60000000>;
> + };
> +
> + chosen {
> + stdout-path = "serial1:115200n8";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
> new file mode 100644
> index 0000000..7c217c5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
> @@ -0,0 +1,71 @@
> +/*
> + * Spreadtrum Whale2 platform peripherals
> + *
> + * Copyright (C) 2016, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ap-apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x70000000 0x10000000>;
> +
> + uart0: serial at 0 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x0 0x100>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 100000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x100000 0x100>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart2: serial at 200000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x200000 0x100>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart3: serial at 300000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x300000 0x100>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> + };
> +
> + };
> +
> + ext_26m: ext-26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "ext_26m";
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3 1/8] trace: ras: add ARM processor error information trace event
From: Xie XiuQi @ 2017-04-17 3:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6c0d2652-71ba-aefc-d6cd-5cc9a0b0d729@huawei.com>
Hi Tyler,
On 2017/4/17 11:08, Xie XiuQi wrote:
> Hi Tyler,
>
> Thanks for your comments and testing.
>
> On 2017/4/15 4:36, Baicar, Tyler wrote:
>> On 3/30/2017 4:31 AM, Xie XiuQi wrote:
>>> Add a new trace event for ARM processor error information, so that
>>> the user will know what error occurred. With this information the
>>> user may take appropriate action.
>>>
>>> These trace events are consistent with the ARM processor error
>>> information table which defined in UEFI 2.6 spec section N.2.4.4.1.
>>>
>>> ---
>>> v2: add trace enabled condition as Steven's suggestion.
>>> fix a typo.
>>> ---
>>>
>>> Cc: Steven Rostedt <rostedt@goodmis.org>
>>> Cc: Tyler Baicar <tbaicar@codeaurora.org>
>>> Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>
>>> ---
>> ...
>>> +#define ARM_PROC_ERR_TYPE \
>>> + EM ( CPER_ARM_INFO_TYPE_CACHE, "cache error" ) \
>>> + EM ( CPER_ARM_INFO_TYPE_TLB, "TLB error" ) \
>>> + EM ( CPER_ARM_INFO_TYPE_BUS, "bus error" ) \
>>> + EMe ( CPER_ARM_INFO_TYPE_UARCH, "micro-architectural error" )
>>> +
>>> +#define ARM_PROC_ERR_FLAGS \
>>> + EM ( CPER_ARM_INFO_FLAGS_FIRST, "First error captured" ) \
>>> + EM ( CPER_ARM_INFO_FLAGS_LAST, "Last error captured" ) \
>>> + EM ( CPER_ARM_INFO_FLAGS_PROPAGATED, "Propagated" ) \
>>> + EMe ( CPER_ARM_INFO_FLAGS_OVERFLOW, "Overflow" )
>>> +
>> Hello Xie XiuQi,
>>
>> This isn't compiling for me because of these definitions. Here you are using ARM_*, but below in the TP_printk you are using ARCH_*. The compiler complains the ARCH_* ones are undefined:
>>
>> ./include/trace/../../include/ras/ras_event.h:278:37: error: 'ARCH_PROC_ERR_TYPE' undeclared (first use in this function)
>> __print_symbolic(__entry->type, ARCH_PROC_ERR_TYPE),
>> ./include/trace/../../include/ras/ras_event.h:280:38: error: 'ARCH_PROC_ERR_FLAGS' undeclared (first use in this function)
>> __print_symbolic(__entry->flags, ARCH_PROC_ERR_FLAGS),
>
> Sorry, it's a typo. It should be ARM_xxx.
>
>>
>>> +/*
>>> + * First define the enums in MM_ACTION_RESULT to be exported to userspace
>>> + * via TRACE_DEFINE_ENUM().
>>> + */
>>> +#undef EM
>>> +#undef EMe
>>> +#define EM(a, b) TRACE_DEFINE_ENUM(a);
>>> +#define EMe(a, b) TRACE_DEFINE_ENUM(a);
>>> +
>>> +ARM_PROC_ERR_TYPE
>>> +ARM_PROC_ERR_FLAGS
>> Are the above two lines supposed to be here?
>>> +
>>> +/*
>>> + * Now redefine the EM() and EMe() macros to map the enums to the strings
>>> + * that will be printed in the output.
>>> + */
>>> +#undef EM
>>> +#undef EMe
>>> +#define EM(a, b) { a, b },
>>> +#define EMe(a, b) { a, b }
>>> +
>>> +TRACE_EVENT(arm_proc_err,
>> I think it would be better to keep this similar to the naming of the current RAS trace events (right now we have mc_event, arm_event, aer_event, etc.). I would suggest using "arm_err_info_event" since this is handling the error information structures of the arm errors.
>>> +
>>> + TP_PROTO(const struct cper_arm_err_info *err),
>>> +
>>> + TP_ARGS(err),
>>> +
>>> + TP_STRUCT__entry(
>>> + __field(u8, type)
>>> + __field(u16, multiple_error)
>>> + __field(u8, flags)
>>> + __field(u64, error_info)
>>> + __field(u64, virt_fault_addr)
>>> + __field(u64, physical_fault_addr)
>> Validation bits should also be a part of this structure that way user space tools will know which of these fields are valid.
>
> Could we use the default value to check the validation which we have checked in TP_fast_assign?
>
>>> + ),
>>> +
>>> + TP_fast_assign(
>>> + __entry->type = err->type;
>>> +
>>> + if (err->validation_bits & CPER_ARM_INFO_VALID_MULTI_ERR)
>>> + __entry->multiple_error = err->multiple_error;
>>> + else
>>> + __entry->multiple_error = ~0;
>>> +
>>> + if (err->validation_bits & CPER_ARM_INFO_VALID_FLAGS)
>>> + __entry->flags = err->flags;
>>> + else
>>> + __entry->flags = ~0;
>>> +
>>> + if (err->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO)
>>> + __entry->error_info = err->error_info;
>>> + else
>>> + __entry->error_info = 0ULL;
>>> +
>>> + if (err->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR)
>>> + __entry->virt_fault_addr = err->virt_fault_addr;
>>> + else
>>> + __entry->virt_fault_addr = 0ULL;
>>> +
>>> + if (err->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR)
>>> + __entry->physical_fault_addr = err->physical_fault_addr;
>>> + else
>>> + __entry->physical_fault_addr = 0ULL;
>>> + ),
>>> +
>>> + TP_printk("ARM Processor Error: type %s; count: %u; flags: %s;"
>> I think the "ARM Processor Error:" part of this should just be removed. Here's the output with this removed and the trace event renamed to arm_err_info_event. I think this looks much cleaner and matches the style used with the arm_event.
>>
>> <idle>-0 [020] .ns. 366.592434: arm_event: affinity level: 2; MPIDR: 0000000000000000; MIDR: 00000000510f8000; running state: 1; PSCI state: 0
>> <idle>-0 [020] .ns. 366.592437: arm_err_info_event: type cache error; count: 0; flags: 0x3; error info: 0000000000c20058; virtual address: 0000000000000000; physical address: 0000000000000000
>
As this section is ARM Processor Error Section, how about use arm_proc_err_event?
> I agree. It looks much better.
>
>>
>> Thanks,
>> Tyler
>>
>
--
Thanks,
Xie XiuQi
^ permalink raw reply
* [PATCH v3 1/8] trace: ras: add ARM processor error information trace event
From: Xie XiuQi @ 2017-04-17 3:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <32ca4e7e-eb5e-a4ff-33d6-68d06e9242fb@codeaurora.org>
Hi Tyler,
Thanks for your comments and testing.
On 2017/4/15 4:36, Baicar, Tyler wrote:
> On 3/30/2017 4:31 AM, Xie XiuQi wrote:
>> Add a new trace event for ARM processor error information, so that
>> the user will know what error occurred. With this information the
>> user may take appropriate action.
>>
>> These trace events are consistent with the ARM processor error
>> information table which defined in UEFI 2.6 spec section N.2.4.4.1.
>>
>> ---
>> v2: add trace enabled condition as Steven's suggestion.
>> fix a typo.
>> ---
>>
>> Cc: Steven Rostedt <rostedt@goodmis.org>
>> Cc: Tyler Baicar <tbaicar@codeaurora.org>
>> Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>
>> ---
> ...
>> +#define ARM_PROC_ERR_TYPE \
>> + EM ( CPER_ARM_INFO_TYPE_CACHE, "cache error" ) \
>> + EM ( CPER_ARM_INFO_TYPE_TLB, "TLB error" ) \
>> + EM ( CPER_ARM_INFO_TYPE_BUS, "bus error" ) \
>> + EMe ( CPER_ARM_INFO_TYPE_UARCH, "micro-architectural error" )
>> +
>> +#define ARM_PROC_ERR_FLAGS \
>> + EM ( CPER_ARM_INFO_FLAGS_FIRST, "First error captured" ) \
>> + EM ( CPER_ARM_INFO_FLAGS_LAST, "Last error captured" ) \
>> + EM ( CPER_ARM_INFO_FLAGS_PROPAGATED, "Propagated" ) \
>> + EMe ( CPER_ARM_INFO_FLAGS_OVERFLOW, "Overflow" )
>> +
> Hello Xie XiuQi,
>
> This isn't compiling for me because of these definitions. Here you are using ARM_*, but below in the TP_printk you are using ARCH_*. The compiler complains the ARCH_* ones are undefined:
>
> ./include/trace/../../include/ras/ras_event.h:278:37: error: 'ARCH_PROC_ERR_TYPE' undeclared (first use in this function)
> __print_symbolic(__entry->type, ARCH_PROC_ERR_TYPE),
> ./include/trace/../../include/ras/ras_event.h:280:38: error: 'ARCH_PROC_ERR_FLAGS' undeclared (first use in this function)
> __print_symbolic(__entry->flags, ARCH_PROC_ERR_FLAGS),
Sorry, it's a typo. It should be ARM_xxx.
>
>> +/*
>> + * First define the enums in MM_ACTION_RESULT to be exported to userspace
>> + * via TRACE_DEFINE_ENUM().
>> + */
>> +#undef EM
>> +#undef EMe
>> +#define EM(a, b) TRACE_DEFINE_ENUM(a);
>> +#define EMe(a, b) TRACE_DEFINE_ENUM(a);
>> +
>> +ARM_PROC_ERR_TYPE
>> +ARM_PROC_ERR_FLAGS
> Are the above two lines supposed to be here?
>> +
>> +/*
>> + * Now redefine the EM() and EMe() macros to map the enums to the strings
>> + * that will be printed in the output.
>> + */
>> +#undef EM
>> +#undef EMe
>> +#define EM(a, b) { a, b },
>> +#define EMe(a, b) { a, b }
>> +
>> +TRACE_EVENT(arm_proc_err,
> I think it would be better to keep this similar to the naming of the current RAS trace events (right now we have mc_event, arm_event, aer_event, etc.). I would suggest using "arm_err_info_event" since this is handling the error information structures of the arm errors.
>> +
>> + TP_PROTO(const struct cper_arm_err_info *err),
>> +
>> + TP_ARGS(err),
>> +
>> + TP_STRUCT__entry(
>> + __field(u8, type)
>> + __field(u16, multiple_error)
>> + __field(u8, flags)
>> + __field(u64, error_info)
>> + __field(u64, virt_fault_addr)
>> + __field(u64, physical_fault_addr)
> Validation bits should also be a part of this structure that way user space tools will know which of these fields are valid.
Could we use the default value to check the validation which we have checked in TP_fast_assign?
>> + ),
>> +
>> + TP_fast_assign(
>> + __entry->type = err->type;
>> +
>> + if (err->validation_bits & CPER_ARM_INFO_VALID_MULTI_ERR)
>> + __entry->multiple_error = err->multiple_error;
>> + else
>> + __entry->multiple_error = ~0;
>> +
>> + if (err->validation_bits & CPER_ARM_INFO_VALID_FLAGS)
>> + __entry->flags = err->flags;
>> + else
>> + __entry->flags = ~0;
>> +
>> + if (err->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO)
>> + __entry->error_info = err->error_info;
>> + else
>> + __entry->error_info = 0ULL;
>> +
>> + if (err->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR)
>> + __entry->virt_fault_addr = err->virt_fault_addr;
>> + else
>> + __entry->virt_fault_addr = 0ULL;
>> +
>> + if (err->validation_bits & CPER_ARM_INFO_VALID_PHYSICAL_ADDR)
>> + __entry->physical_fault_addr = err->physical_fault_addr;
>> + else
>> + __entry->physical_fault_addr = 0ULL;
>> + ),
>> +
>> + TP_printk("ARM Processor Error: type %s; count: %u; flags: %s;"
> I think the "ARM Processor Error:" part of this should just be removed. Here's the output with this removed and the trace event renamed to arm_err_info_event. I think this looks much cleaner and matches the style used with the arm_event.
>
> <idle>-0 [020] .ns. 366.592434: arm_event: affinity level: 2; MPIDR: 0000000000000000; MIDR: 00000000510f8000; running state: 1; PSCI state: 0
> <idle>-0 [020] .ns. 366.592437: arm_err_info_event: type cache error; count: 0; flags: 0x3; error info: 0000000000c20058; virtual address: 0000000000000000; physical address: 0000000000000000
I agree. It looks much better.
>
> Thanks,
> Tyler
>
--
Thanks,
Xie XiuQi
^ permalink raw reply
* [PATCH V2] PM / OPP: Use - instead of @ for DT entries
From: Masahiro Yamada @ 2017-04-17 2:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2765521.jPoRkFTblf@aspire.rjw.lan>
2017-04-15 7:47 GMT+09:00 Rafael J. Wysocki <rjw@rjwysocki.net>:
> On Monday, April 10, 2017 02:51:35 PM Viresh Kumar wrote:
>> Compiling the DT file with W=1, DTC warns like follows:
>>
>> Warning (unit_address_vs_reg): Node /opp_table0/opp at 1000000000 has a
>> unit name, but no reg property
>>
>> Fix this by replacing '@' with '-' as the OPP nodes will never have a
>> "reg" property.
>>
>> Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
>> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> Suggested-by: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> (sunxi)
>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> OK, so any ACKs from the DT side? Rob?
>
> Thanks,
> Rafael
I see Rob's Acked-by.
https://lkml.org/lkml/2017/4/13/648
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
From: Andy Tang @ 2017-04-17 1:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR0402MB283701D478A1678D28894C77F30A0@DB6PR0402MB2837.eurprd04.prod.outlook.com>
Hi Stephen and Michael,
This patch set has been pending for more than two months since it was first sent.
I have not received any response from you until now.
Could you give some comments on it?
Regards,
Andy
-----Original Message-----
From: Andy Tang
Sent: Wednesday, April 05, 2017 2:16 PM
To: mturquette at baylibre.com; sboyd at codeaurora.org
Cc: robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: RE: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
Hello
Do you have any comments on this patch set which was acked by Rob?
Regards,
Andy
> -----Original Message-----
> From: Yuantian Tang [mailto:andy.tang at nxp.com]
> Sent: Monday, March 20, 2017 10:37 AM
> To: mturquette at baylibre.com
> Cc: sboyd at codeaurora.org; robh+dt at kernel.org; mark.rutland at arm.com;
> linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-
> kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott
> Wood <oss@buserror.net>; Andy Tang <andy.tang@nxp.com>
> Subject: [PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk
>
> From: Scott Wood <oss@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> Update the qoriq-clock binding to allow a second input clock, named
> "coreclk". If present, this clock will be used for the core PLLs.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> v2:
> -- change the author to Scott
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index aa3526f..119cafd 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -56,6 +56,11 @@ Optional properties:
> - clocks: If clock-frequency is not specified, sysclk may be provided
> as an input clock. Either clock-frequency or clocks must be
> provided.
> + A second input clock, called "coreclk", may be provided if
> + core PLLs are based on a different input clock from the
> + platform PLL.
> +- clock-names: Required if a coreclk is present. Valid names are
> + "sysclk" and "coreclk".
>
> 2. Clock Provider
>
> @@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
> 2 hwaccel index (n in CLKCGnHWACSR)
> 3 fman 0 for fm1, 1 for fm2
> 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
> + 5 coreclk must be 0
>
> 3. Example
>
> --
> 2.1.0.27.g96db324
^ permalink raw reply
* [PATCH v5 2/5] drivers: watchdog: Add STM32 IWDG driver
From: Guenter Roeck @ 2017-04-17 1:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491481168-22213-3-git-send-email-yannick.fertre@st.com>
On 04/06/2017 05:19 AM, Yannick Fertre wrote:
> This patch adds IWDG (Independent WatchDoG) support for STM32 platform.
>
> Signed-off-by: Yannick FERTRE <yannick.fertre@st.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> drivers/watchdog/Kconfig | 12 ++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/stm32_iwdg.c | 253 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 266 insertions(+)
> create mode 100644 drivers/watchdog/stm32_iwdg.c
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 52a70ee..d014deb 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -744,6 +744,18 @@ config ZX2967_WATCHDOG
> To compile this driver as a module, choose M here: the
> module will be called zx2967_wdt.
>
> +config STM32_WATCHDOG
> + tristate "STM32 Independent WatchDoG (IWDG) support"
> + depends on ARCH_STM32
> + select WATCHDOG_CORE
> + default y
> + help
> + Say Y here to include support for the watchdog timer
> + in stm32 SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called stm32_iwdg.
> +
> # AVR32 Architecture
>
> config AT32AP700X_WDT
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index a2126e2..a35e423 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -84,6 +84,7 @@ obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
> obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
> obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
> obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
> +obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
>
> # AVR32 Architecture
> obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
> diff --git a/drivers/watchdog/stm32_iwdg.c b/drivers/watchdog/stm32_iwdg.c
> new file mode 100644
> index 0000000..6c501b7
> --- /dev/null
> +++ b/drivers/watchdog/stm32_iwdg.c
> @@ -0,0 +1,253 @@
> +/*
> + * Driver for STM32 Independent Watchdog
> + *
> + * Copyright (C) Yannick Fertre 2017
> + * Author: Yannick Fertre <yannick.fertre@st.com>
> + *
> + * This driver is based on tegra_wdt.c
> + *
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/watchdog.h>
> +
> +/* IWDG registers */
> +#define IWDG_KR 0x00 /* Key register */
> +#define IWDG_PR 0x04 /* Prescaler Register */
> +#define IWDG_RLR 0x08 /* ReLoad Register */
> +#define IWDG_SR 0x0C /* Status Register */
> +#define IWDG_WINR 0x10 /* Windows Register */
> +
> +/* IWDG_KR register bit mask */
> +#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
> +#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
> +#define KR_KEY_EWA 0x5555 /* write access enable */
> +#define KR_KEY_DWA 0x0000 /* write access disable */
> +
> +/* IWDG_PR register bit values */
> +#define PR_4 0x00 /* prescaler set to 4 */
> +#define PR_8 0x01 /* prescaler set to 8 */
> +#define PR_16 0x02 /* prescaler set to 16 */
> +#define PR_32 0x03 /* prescaler set to 32 */
> +#define PR_64 0x04 /* prescaler set to 64 */
> +#define PR_128 0x05 /* prescaler set to 128 */
> +#define PR_256 0x06 /* prescaler set to 256 */
> +
> +/* IWDG_RLR register values */
> +#define RLR_MIN 0x07C /* min value supported by reload register */
> +#define RLR_MAX 0xFFF /* max value supported by reload register */
> +
> +/* IWDG_SR register bit mask */
> +#define FLAG_PVU BIT(0) /* Watchdog prescaler value update */
> +#define FLAG_RVU BIT(1) /* Watchdog counter reload value update */
> +
> +/* set timeout to 100000 us */
> +#define TIMEOUT_US 100000
> +#define SLEEP_US 1000
> +
> +struct stm32_iwdg {
> + struct watchdog_device wdd;
> + void __iomem *regs;
> + struct clk *clk;
> + unsigned int rate;
> +};
> +
> +static inline u32 reg_read(void __iomem *base, u32 reg)
> +{
> + return readl_relaxed(base + reg);
> +}
> +
> +static inline void reg_write(void __iomem *base, u32 reg, u32 val)
> +{
> + writel_relaxed(val, base + reg);
> +}
> +
> +static int stm32_iwdg_start(struct watchdog_device *wdd)
> +{
> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
> + u32 val = FLAG_PVU | FLAG_RVU;
> + u32 reload;
> + int ret;
> +
> + dev_dbg(wdd->parent, "%s\n", __func__);
> +
> + /* prescaler fixed to 256 */
> + reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
> + RLR_MIN, RLR_MAX);
> +
> + /* enable write access */
> + reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
> +
> + /* set prescaler & reload registers */
> + reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
> + reg_write(wdt->regs, IWDG_RLR, reload);
> + reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
> +
> + /* wait for the registers to be updated (max 100ms) */
> + ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
> + !(val & (FLAG_PVU | FLAG_RVU)),
> + SLEEP_US, TIMEOUT_US);
> + if (ret) {
> + dev_err(wdd->parent,
> + "Fail to set prescaler or reload registers\n");
> + return ret;
> + }
> +
> + /* reload watchdog */
> + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
> +
> + return 0;
> +}
> +
> +static int stm32_iwdg_ping(struct watchdog_device *wdd)
> +{
> + struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
> +
> + dev_dbg(wdd->parent, "%s\n", __func__);
> +
> + /* reload watchdog */
> + reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
> +
> + return 0;
> +}
> +
> +static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
> + unsigned int timeout)
> +{
> + dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
> +
> + wdd->timeout = timeout;
> +
> + if (watchdog_active(wdd))
> + return stm32_iwdg_start(wdd);
> +
> + return 0;
> +}
> +
> +static const struct watchdog_info stm32_iwdg_info = {
> + .options = WDIOF_SETTIMEOUT |
> + WDIOF_MAGICCLOSE |
> + WDIOF_KEEPALIVEPING,
> + .identity = "STM32 Independent Watchdog",
> +};
> +
> +static struct watchdog_ops stm32_iwdg_ops = {
> + .owner = THIS_MODULE,
> + .start = stm32_iwdg_start,
> + .ping = stm32_iwdg_ping,
> + .set_timeout = stm32_iwdg_set_timeout,
> +};
> +
> +static int stm32_iwdg_probe(struct platform_device *pdev)
> +{
> + struct watchdog_device *wdd;
> + struct stm32_iwdg *wdt;
> + struct resource *res;
> + void __iomem *regs;
> + struct clk *clk;
> + int ret;
> +
> + /* This is the timer base. */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + regs = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(regs)) {
> + dev_err(&pdev->dev, "Could not get resource\n");
> + return PTR_ERR(regs);
> + }
> +
> + clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "Unable to get clock\n");
> + return PTR_ERR(clk);
> + }
> +
> + ret = clk_prepare_enable(clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to prepare clock %p\n", clk);
> + return ret;
> + }
> +
> + /*
> + * Allocate our watchdog driver data, which has the
> + * struct watchdog_device nested within it.
> + */
> + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
> + if (!wdt) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + /* Initialize struct stm32_iwdg. */
> + wdt->regs = regs;
> + wdt->clk = clk;
> + wdt->rate = clk_get_rate(clk);
> +
> + /* Initialize struct watchdog_device. */
> + wdd = &wdt->wdd;
> + wdd->info = &stm32_iwdg_info;
> + wdd->ops = &stm32_iwdg_ops;
> + wdd->min_timeout = ((RLR_MIN + 1) * 256) / wdt->rate;
> + wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 256 * 1000) / wdt->rate;
> + wdd->parent = &pdev->dev;
> +
> + watchdog_set_drvdata(wdd, wdt);
> + watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
> +
> + ret = watchdog_init_timeout(wdd, 0, &pdev->dev);
> + if (ret)
> + dev_warn(&pdev->dev,
> + "unable to set timeout value, using default\n");
> +
> + ret = watchdog_register_device(wdd);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register watchdog device\n");
> + goto err;
> + }
> +
> + platform_set_drvdata(pdev, wdt);
> +
> + return 0;
> +err:
> + clk_disable_unprepare(clk);
> +
> + return ret;
> +}
> +
> +static int stm32_iwdg_remove(struct platform_device *pdev)
> +{
> + struct stm32_iwdg *wdt = platform_get_drvdata(pdev);
> +
> + watchdog_unregister_device(&wdt->wdd);
> + clk_disable_unprepare(wdt->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_iwdg_of_match[] = {
> + { .compatible = "st,stm32-iwdg" },
> + { /* end node */ }
> +};
> +MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
> +
> +static struct platform_driver stm32_iwdg_driver = {
> + .probe = stm32_iwdg_probe,
> + .remove = stm32_iwdg_remove,
> + .driver = {
> + .name = "iwdg",
> + .of_match_table = stm32_iwdg_of_match,
> + },
> +};
> +module_platform_driver(stm32_iwdg_driver);
> +
> +MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
> +MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* [PATCH] arm: dma: fix sharing of coherent DMA memory without struct page
From: Shuah Khan @ 2017-04-17 1:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170414094643.GG17774@n2100.armlinux.org.uk>
On 04/14/2017 03:46 AM, Russell King - ARM Linux wrote:
> On Fri, Apr 14, 2017 at 09:56:07AM +0200, Marek Szyprowski wrote:
>>>> This would be however quite large task, especially taking into account
>>>> all current users of DMA-buf framework...
>>> Yeah it will be a large task.
>>
>> Maybe once scatterlist are switched to pfns, changing dmabuf internal
>> memory representation to pfn array might be much easier.
>
> Switching to a PFN array won't work either as we have no cross-arch
> way to translate PFNs to a DMA address and vice versa. Yes, we have
> them in ARM, but they are an _implementation detail_ of ARM's
> DMA API support, they are not for use by drivers.
>
> So, the very first problem that needs solving is this:
>
> How do we go from a coherent DMA allocation for device X to a set
> of DMA addresses for device Y.
>
> Essentially, we need a way of remapping the DMA buffer for use with
> another device, and returning a DMA address suitable for that device.
> This could well mean that we need to deal with setting up an IOMMU
> mapping. My guess is that this needs to happen at the DMA coherent
> API level - the DMA coherent API needs to be augmented with support
> for this. I'll call this "DMA coherent remap".
>
> We then need to think about how to pass this through the dma-buf API.
> dma_map_sg() is done by the exporter, who should know what kind of
> memory is being exported. The exporter can avoid calling dma_map_sg()
> if it knows in advance that it is exporting DMA coherent memory.
> Instead, the exporter can simply create a scatterlist with the DMA
> address and DMA length prepopulated with the results of the DMA
> coherent remap operation above.
The only way to conclusively say that it is coming from coherent area
is at the time it is getting allocated in dma_alloc_from_coherent().
Since dma_alloc_attrs() will go on to find memory from other areas if
dma_alloc_from_coherent() doesn't allocate memory.
dma_get_sgtable_attrs() is what is used by the exporter to create the
sg_table. One way to do this cleanly without needing to check buffer
type flags would be to add a set of sg_table ops: get_sgtable,
map_sg, and unmap_sg. Sounds like sg_table interfaces need to be in
dma_buf_ops level. More below.
>
> What the scatterlist can't carry in this case is a set of valid
> struct page pointers, and an importer must not walk the scatterlist
> expecting to get at the virtual address parameters or struct page
> pointers.
>
> On the mmap() side of things, remember that DMA coherent allocations
> may require special mapping into userspace, and which can only be
> mapped by the DMA coherent mmap support. kmap etc will also need to
> be different. So it probably makes sense for DMA coherent dma-buf
> exports to use a completely separate set of dma_buf_ops from the
> streaming version.
How about adding get_sgtable, map_sg, unmap_sg to dma_buf_ops. The right
ops need to be installed based on buffer type. As I mentioned before, we
don't know which memory we got until dma_alloc_from_coherent() finds
memory in dev->mem area. So how about using the dma_check_dev_coherent()
to determine which ops we need. These could be set based on buffer type.
vb2_dc_get_dmabuf() can do that.
I think this will work.
thanks,
-- Shuah
^ permalink raw reply
* [PATCH 2/2] arm64: Fix power-of-ten vs. power-of-two prefixes in comments etc.
From: Simon Horman @ 2017-04-16 23:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492085938.20068.6.camel@infradead.org>
[Cc linux-renesas-soc]
On Thu, Apr 13, 2017 at 01:18:58PM +0100, David Woodhouse wrote:
> Less important than in user-visible messages, but still good practice as
> there's still no excuse for ARM64 code to look like it was written before
> 1996.
>
> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Hi David,
I'd be happy to take the Renesas portions of this change if they were
broken out into a separate patch. The reason I would prefer a separate
patch is to avoid the possibility of conflicts, even trivial ones.
> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 2 +-
> .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +-
> arch/arm64/boot/dts/broadcom/ns2-xmc.dts | 24 +++++++++++-----------
> arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
> arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts | 2 +-
> arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 2 +-
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 2 +-
> arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +-
> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 2 +-
> arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 2 +-
> arch/arm64/include/asm/assembler.h | 2 +-
> arch/arm64/include/asm/boot.h | 4 ++--
> arch/arm64/include/asm/elf.h | 2 +-
> arch/arm64/include/asm/fixmap.h | 6 +++---
> arch/arm64/kernel/head.S | 8 ++++----
> arch/arm64/kernel/hyp-stub.S | 2 +-
> arch/arm64/kernel/kaslr.c | 14 ++++++-------
> arch/arm64/kernel/module-plts.c | 2 +-
> arch/arm64/kernel/vmlinux.lds.S | 18 ++++++++--------
> arch/arm64/mm/mmu.c | 2 +-
> arch/arm64/mm/proc.S | 2 +-
> 22 files changed, 53 insertions(+), 53 deletions(-)
...
^ permalink raw reply
* [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU
From: icenowy at aosc.io @ 2017-04-16 21:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170416205740.b5pk3kcxwaegij6g@lukather>
? 2017-04-17 04:57?Maxime Ripard ???
> On Tue, Apr 11, 2017 at 09:28:55PM +0800, icenowy at aosc.io wrote:
>> ? 2017-04-11 17:13?Maxime Ripard ???
>> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
>> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
>> > >
>> > > Add a DVFS table based on the one tweaked by Armbian developers, which
>> > > are proven to work stably on BSP kernels.
>> > >
>> > > Frequencies higher than 1008MHz are temporarily dropped in the
>> > > table, as
>> > > they may lead to over voltage on boards without proper regulator
>> > > settings or over temperature on boards with proper regulator settings.
>> > > They will be added back once regulator settings are ready and thermal
>> > > sensor driver is merged.
>> > >
>> > > In order to satisfy all different regulators (SY8106A which is 50mV
>> > > per
>> > > level, SY8113B which have two states: 1.1V and 1.3V, and some board
>> > > with
>> > > non-tweakable regulators), all the OPPs are defined with a range
>> > > which has
>> > > the target value as the minimum allowed value, and 1.3V (the highest
>> > > VDD-CPUX voltage suggested by the datasheet) as the maximum allowed
>> > > value.
>> > > It's proven to work well with a board with SY8113B.
>> > >
>> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> > > ---
>> > > arch/arm/boot/dts/sun8i-h3.dtsi | 38
>> > > +++++++++++++++++++++++++++++++++++++-
>> > > 1 file changed, 37 insertions(+), 1 deletion(-)
>> > >
>> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > b/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > index b36f9f423c39..a0cee17fe44b 100644
>> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > @@ -43,32 +43,68 @@
>> > > #include "sunxi-h3-h5.dtsi"
>> > >
>> > > / {
>> > > + cpu0_opp_table: opp_table0 {
>> > > + compatible = "operating-points-v2";
>> > > + opp-shared;
>> > > +
>> > > + opp at 480000000 {
>> > > + opp-hz = /bits/ 64 <480000000>;
>> > > + opp-microvolt = <980000 980000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 648000000 {
>> > > + opp-hz = /bits/ 64 <816000000>;
>> > > + opp-microvolt = <1020000 1020000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 912000000 {
>> > > + opp-hz = /bits/ 64 <960000000>;
>> > > + opp-microvolt = <1080000 1080000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 1008000000 {
>> > > + opp-hz = /bits/ 64 <1008000000>;
>> > > + opp-microvolt = <1140000 1140000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > + };
>> > > +
>> >
>> > From your serie, I guess you never actually tested those OPPs on any
>> > board without SY8113B, right?
>>
>> Yes. But I will test them on an Orange Pi PC (newly got) soon.
>
> The orange pi pc also uses the SY8113B.
I checked the wiki, it says "The Orange Pi PC board uses the
SY8106A voltage regulator for providing the CPU core voltage
(VDD_CPUX). The default CPU voltage is 1.2V after power-on
(selected by the resistors on the PCB) and can be changed at
runtime by software via I2C interface. According to the table
above, this default voltage should be safe for using with the
CPU clock frequencies up to 1008MHz. The H3 datasheet specifies
1.5V as the absolute maximum for the VDD_CPUX voltage and
1.4V as the recommended maximum." in the "Xunlong Orange Pi PC"
page.
>
>> (After all PLL_CPUX-related things are well fixed)
>>
>> P.S. how to implement such a thing:
>>
>> - Before tweaking CPUX clock, first switch it to osc24M
>> (implemented yet)
>> - Before tweaking PLL_CPUX clock (triggered by tweaking CPUX
>> clock), first gate it
>> - After tweaking PLL_CPUX clock, ungate it and wait it to be stable
>> - After tweaking PLL_CPUX clock, change CPUX mux back to PLL_CPUX
>> (implemented yet)
>>
>> I think notifiers on PLL_CPUX can be used to implement the second
>> and third part?
>
> Do you still have any issues with the code we merged?
No problem... But I think the H3 part of the patch is still not merged
yet...
>
> Maxime
^ permalink raw reply
* [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU
From: Icenowy Zheng @ 2017-04-16 21:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170416205740.b5pk3kcxwaegij6g@lukather>
? 2017?4?17? GMT+08:00 ??4:57:40, Maxime Ripard <maxime.ripard@free-electrons.com> ??:
>On Tue, Apr 11, 2017 at 09:28:55PM +0800, icenowy at aosc.io wrote:
>> ? 2017-04-11 17:13?Maxime Ripard ???
>> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
>> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
>> > >
>> > > Add a DVFS table based on the one tweaked by Armbian developers,
>which
>> > > are proven to work stably on BSP kernels.
>> > >
>> > > Frequencies higher than 1008MHz are temporarily dropped in the
>> > > table, as
>> > > they may lead to over voltage on boards without proper regulator
>> > > settings or over temperature on boards with proper regulator
>settings.
>> > > They will be added back once regulator settings are ready and
>thermal
>> > > sensor driver is merged.
>> > >
>> > > In order to satisfy all different regulators (SY8106A which is
>50mV
>> > > per
>> > > level, SY8113B which have two states: 1.1V and 1.3V, and some
>board
>> > > with
>> > > non-tweakable regulators), all the OPPs are defined with a range
>> > > which has
>> > > the target value as the minimum allowed value, and 1.3V (the
>highest
>> > > VDD-CPUX voltage suggested by the datasheet) as the maximum
>allowed
>> > > value.
>> > > It's proven to work well with a board with SY8113B.
>> > >
>> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> > > ---
>> > > arch/arm/boot/dts/sun8i-h3.dtsi | 38
>> > > +++++++++++++++++++++++++++++++++++++-
>> > > 1 file changed, 37 insertions(+), 1 deletion(-)
>> > >
>> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > b/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > index b36f9f423c39..a0cee17fe44b 100644
>> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> > > @@ -43,32 +43,68 @@
>> > > #include "sunxi-h3-h5.dtsi"
>> > >
>> > > / {
>> > > + cpu0_opp_table: opp_table0 {
>> > > + compatible = "operating-points-v2";
>> > > + opp-shared;
>> > > +
>> > > + opp at 480000000 {
>> > > + opp-hz = /bits/ 64 <480000000>;
>> > > + opp-microvolt = <980000 980000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 648000000 {
>> > > + opp-hz = /bits/ 64 <816000000>;
>> > > + opp-microvolt = <1020000 1020000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 912000000 {
>> > > + opp-hz = /bits/ 64 <960000000>;
>> > > + opp-microvolt = <1080000 1080000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > +
>> > > + opp at 1008000000 {
>> > > + opp-hz = /bits/ 64 <1008000000>;
>> > > + opp-microvolt = <1140000 1140000 1300000>;
>> > > + clock-latency-ns = <244144>; /* 8 32k periods */
>> > > + };
>> > > + };
>> > > +
>> >
>> > From your serie, I guess you never actually tested those OPPs on
>any
>> > board without SY8113B, right?
>>
>> Yes. But I will test them on an Orange Pi PC (newly got) soon.
>
>The orange pi pc also uses the SY8113B.
I remember in H3 Orange Pi's only One, Lite and Zero uses SY8113B, and PC is SY8106A.
>
>> (After all PLL_CPUX-related things are well fixed)
>>
>> P.S. how to implement such a thing:
>>
>> - Before tweaking CPUX clock, first switch it to osc24M
>> (implemented yet)
>> - Before tweaking PLL_CPUX clock (triggered by tweaking CPUX
>> clock), first gate it
>> - After tweaking PLL_CPUX clock, ungate it and wait it to be stable
>> - After tweaking PLL_CPUX clock, change CPUX mux back to PLL_CPUX
>> (implemented yet)
>>
>> I think notifiers on PLL_CPUX can be used to implement the second
>> and third part?
>
>Do you still have any issues with the code we merged?
Chen-Yu's? I tested it and it has no issue at all.
>
>Maxime
^ permalink raw reply
* [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU
From: Maxime Ripard @ 2017-04-16 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b37490ed1282f45542168701dea332bb@aosc.io>
On Tue, Apr 11, 2017 at 09:28:55PM +0800, icenowy at aosc.io wrote:
> ? 2017-04-11 17:13?Maxime Ripard ???
> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
> > >
> > > Add a DVFS table based on the one tweaked by Armbian developers, which
> > > are proven to work stably on BSP kernels.
> > >
> > > Frequencies higher than 1008MHz are temporarily dropped in the
> > > table, as
> > > they may lead to over voltage on boards without proper regulator
> > > settings or over temperature on boards with proper regulator settings.
> > > They will be added back once regulator settings are ready and thermal
> > > sensor driver is merged.
> > >
> > > In order to satisfy all different regulators (SY8106A which is 50mV
> > > per
> > > level, SY8113B which have two states: 1.1V and 1.3V, and some board
> > > with
> > > non-tweakable regulators), all the OPPs are defined with a range
> > > which has
> > > the target value as the minimum allowed value, and 1.3V (the highest
> > > VDD-CPUX voltage suggested by the datasheet) as the maximum allowed
> > > value.
> > > It's proven to work well with a board with SY8113B.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > > ---
> > > arch/arm/boot/dts/sun8i-h3.dtsi | 38
> > > +++++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 37 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > index b36f9f423c39..a0cee17fe44b 100644
> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > @@ -43,32 +43,68 @@
> > > #include "sunxi-h3-h5.dtsi"
> > >
> > > / {
> > > + cpu0_opp_table: opp_table0 {
> > > + compatible = "operating-points-v2";
> > > + opp-shared;
> > > +
> > > + opp at 480000000 {
> > > + opp-hz = /bits/ 64 <480000000>;
> > > + opp-microvolt = <980000 980000 1300000>;
> > > + clock-latency-ns = <244144>; /* 8 32k periods */
> > > + };
> > > +
> > > + opp at 648000000 {
> > > + opp-hz = /bits/ 64 <816000000>;
> > > + opp-microvolt = <1020000 1020000 1300000>;
> > > + clock-latency-ns = <244144>; /* 8 32k periods */
> > > + };
> > > +
> > > + opp at 912000000 {
> > > + opp-hz = /bits/ 64 <960000000>;
> > > + opp-microvolt = <1080000 1080000 1300000>;
> > > + clock-latency-ns = <244144>; /* 8 32k periods */
> > > + };
> > > +
> > > + opp at 1008000000 {
> > > + opp-hz = /bits/ 64 <1008000000>;
> > > + opp-microvolt = <1140000 1140000 1300000>;
> > > + clock-latency-ns = <244144>; /* 8 32k periods */
> > > + };
> > > + };
> > > +
> >
> > From your serie, I guess you never actually tested those OPPs on any
> > board without SY8113B, right?
>
> Yes. But I will test them on an Orange Pi PC (newly got) soon.
The orange pi pc also uses the SY8113B.
> (After all PLL_CPUX-related things are well fixed)
>
> P.S. how to implement such a thing:
>
> - Before tweaking CPUX clock, first switch it to osc24M
> (implemented yet)
> - Before tweaking PLL_CPUX clock (triggered by tweaking CPUX
> clock), first gate it
> - After tweaking PLL_CPUX clock, ungate it and wait it to be stable
> - After tweaking PLL_CPUX clock, change CPUX mux back to PLL_CPUX
> (implemented yet)
>
> I think notifiers on PLL_CPUX can be used to implement the second
> and third part?
Do you still have any issues with the code we merged?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH V2] clk: hi6220: Add the hi655x's pmic clock
From: Daniel Lezcano @ 2017-04-16 20:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170412150245.GK7065@codeaurora.org>
On Wed, Apr 12, 2017 at 08:02:45AM -0700, Stephen Boyd wrote:
> On 04/08, Daniel Lezcano wrote:
> >
> > Example:
> > pmic: pmic at f8000000 {
> > @@ -24,4 +29,5 @@ Example:
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
> > + clock-cells = <0>;
>
> Should be #clock-cells instead.
Ok.
> > +static int hi655x_clk_probe(struct platform_device *pdev)
> > +{
> > + struct device *parent = pdev->dev.parent;
> > + struct hi655x_pmic *hi655x = dev_get_drvdata(parent);
> > + struct clk_init_data *hi655x_clk_init;
>
> This can just go onto the stack? We don't need it around after
> probe.
Agree.
> > + struct hi655x_clk *hi655x_clk;
> > + const char *clk_name = "hi655x-clk";
> > + int ret;
> > +
> > + hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
> > + if (!hi655x_clk)
> > + return -ENOMEM;
> > +
> > + hi655x_clk_init = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk_init),
> > + GFP_KERNEL);
> > + if (!hi655x_clk_init)
> > + return -ENOMEM;
> > +
> > + of_property_read_string_index(parent->of_node, "clock-output-names",
> > + 0, &clk_name);
> > +
> > + hi655x_clk_init->name = clk_name;
> > + hi655x_clk_init->ops = &hi655x_clk_ops;
> > +
> > + hi655x_clk->clk_hw.init = hi655x_clk_init;
> > + hi655x_clk->hi655x = hi655x;
> > +
> > + platform_set_drvdata(pdev, hi655x_clk);
> > +
> > + ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
> > + if (ret)
> > + return ret;
> > +
> > + ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get,
> > + &hi655x_clk->clk_hw);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_hw_register_clkdev(&hi655x_clk->clk_hw, clk_name, NULL);
>
> Missed this last time. Do you use this clkdev lookup? The name is
> usually supposed to be based on what the device is expecting,
> instead of clk_name, and we would want some device name for the
> third argument here.
I'm not sure to get your comment. Are you saying the clk_name should be the
third argument?
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH 26/29] ARM: dts: rockchip: disable arm-global-timer for rk3188
From: Daniel Lezcano @ 2017-04-16 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Alexander Kochetkov <al.kochet@gmail.com>
The clocksource and the sched_clock provided by the arm_global_timer
are quite unstable because their rates depend on the cpu frequency.
On the other side, the arm_global_timer has a higher rating than the
rockchip_timer, it will be selected by default by the time framework
while we want to use the stable rockchip clocksource.
Let's disable the arm_global_timer in order to have the rockchip
clocksource selected by default.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3188.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 8428fae..1aff4ad2 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -546,6 +546,7 @@
&global_timer {
interrupts = <GIC_PPI 11 0xf04>;
+ status = "disabled";
};
&local_timer {
--
2.7.4
^ permalink raw reply related
* [PATCH 25/29] ARM: dts: rockchip: Add timer entries to rk3188 SoC
From: Daniel Lezcano @ 2017-04-16 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Alexander Kochetkov <al.kochet@gmail.com>
The patch add two timers to all rk3188 based boards.
The first timer is from alive subsystem and it act as a backup
for the local timers at sleep time. It act the same as other
SoC rockchip timers already present in kernel.
The second timer is from CPU subsystem and act as replacement
for the arm-global-timer clocksource and sched clock. It run
at stable frequency 24MHz.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/boot/dts/rk3188.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index cf91254..8428fae 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -106,6 +106,22 @@
};
};
+ timer3: timer at 2000e000 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x2000e000 0x20>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
+ clock-names = "timer", "pclk";
+ };
+
+ timer6: timer at 200380a0 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x200380a0 0x20>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
+ clock-names = "timer", "pclk";
+ };
+
i2s0: i2s at 1011a000 {
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 24/29] clocksource/drivers/rockchip_timer: Implement clocksource timer
From: Daniel Lezcano @ 2017-04-16 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Alexander Kochetkov <al.kochet@gmail.com>
The clock supplying the arm-global-timer on the rk3188 is coming from the
the cpu clock itself and thus changes its rate everytime cpufreq adjusts
the cpu frequency making this timer unsuitable as a stable clocksource
and sched clock.
The rk3188, rk3288 and following socs share a separate timer block already
handled by the rockchip-timer driver. Therefore adapt this driver to also
be able to act as clocksource and sched clock on rk3188.
In order to test clocksource you can run following commands and check
how much time it take in real. On rk3188 it take about ~45 seconds.
cpufreq-set -f 1.6GHZ
date; sleep 60; date
In order to use the patch you need to declare two timers in the dts
file. The first timer will be initialized as clockevent provider
and the second one as clocksource. The clockevent must be from
alive subsystem as it used as backup for the local timers at sleep
time.
The patch does not break compatibility with older device tree files.
The older device tree files contain only one timer. The timer
will be initialized as clockevent, as expected.
rk3288 (and probably anything newer) is irrelevant to this patch,
as it has the arch timer interface. This patch may be useful
for Cortex-A9/A5 based parts.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/rockchip_timer.c | 218 +++++++++++++++++++++++++----------
2 files changed, 158 insertions(+), 61 deletions(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3356ab8..483f3b1 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -81,6 +81,7 @@ config ROCKCHIP_TIMER
bool "Rockchip timer driver" if COMPILE_TEST
depends on ARM || ARM64
select CLKSRC_OF
+ select CLKSRC_MMIO
help
Enables the support for the rockchip timer driver.
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 23e267a..49c02be 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -11,6 +11,8 @@
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -19,6 +21,8 @@
#define TIMER_LOAD_COUNT0 0x00
#define TIMER_LOAD_COUNT1 0x04
+#define TIMER_CURRENT_VALUE0 0x08
+#define TIMER_CURRENT_VALUE1 0x0C
#define TIMER_CONTROL_REG3288 0x10
#define TIMER_CONTROL_REG3399 0x1c
#define TIMER_INT_STATUS 0x18
@@ -29,103 +33,118 @@
#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
#define TIMER_INT_UNMASK (1 << 2)
-struct bc_timer {
- struct clock_event_device ce;
+struct rk_timer {
void __iomem *base;
void __iomem *ctrl;
+ struct clk *clk;
+ struct clk *pclk;
u32 freq;
+ int irq;
};
-static struct bc_timer bc_timer;
-
-static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
-{
- return container_of(ce, struct bc_timer, ce);
-}
+struct rk_clkevt {
+ struct clock_event_device ce;
+ struct rk_timer timer;
+};
-static inline void __iomem *rk_base(struct clock_event_device *ce)
-{
- return rk_timer(ce)->base;
-}
+static struct rk_clkevt *rk_clkevt;
+static struct rk_timer *rk_clksrc;
-static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
+static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
{
- return rk_timer(ce)->ctrl;
+ return &container_of(ce, struct rk_clkevt, ce)->timer;
}
-static inline void rk_timer_disable(struct clock_event_device *ce)
+static inline void rk_timer_disable(struct rk_timer *timer)
{
- writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
+ writel_relaxed(TIMER_DISABLE, timer->ctrl);
}
-static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
+static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
{
- writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
- rk_ctrl(ce));
+ writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
}
static void rk_timer_update_counter(unsigned long cycles,
- struct clock_event_device *ce)
+ struct rk_timer *timer)
{
- writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
- writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
+ writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
+ writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
}
-static void rk_timer_interrupt_clear(struct clock_event_device *ce)
+static void rk_timer_interrupt_clear(struct rk_timer *timer)
{
- writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
+ writel_relaxed(1, timer->base + TIMER_INT_STATUS);
}
static inline int rk_timer_set_next_event(unsigned long cycles,
struct clock_event_device *ce)
{
- rk_timer_disable(ce);
- rk_timer_update_counter(cycles, ce);
- rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
+ rk_timer_update_counter(cycles, timer);
+ rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
+ TIMER_INT_UNMASK);
return 0;
}
static int rk_timer_shutdown(struct clock_event_device *ce)
{
- rk_timer_disable(ce);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
return 0;
}
static int rk_timer_set_periodic(struct clock_event_device *ce)
{
- rk_timer_disable(ce);
- rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
- rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
+ rk_timer_update_counter(timer->freq / HZ - 1, timer);
+ rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
return 0;
}
static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *ce = dev_id;
+ struct rk_timer *timer = rk_timer(ce);
- rk_timer_interrupt_clear(ce);
+ rk_timer_interrupt_clear(timer);
if (clockevent_state_oneshot(ce))
- rk_timer_disable(ce);
+ rk_timer_disable(timer);
ce->event_handler(ce);
return IRQ_HANDLED;
}
-static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
+static u64 notrace rk_timer_sched_read(void)
+{
+ return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
+}
+
+static int __init
+rk_timer_probe(struct rk_timer *timer, struct device_node *np)
{
- struct clock_event_device *ce = &bc_timer.ce;
struct clk *timer_clk;
struct clk *pclk;
int ret = -EINVAL, irq;
+ u32 ctrl_reg = TIMER_CONTROL_REG3288;
- bc_timer.base = of_iomap(np, 0);
- if (!bc_timer.base) {
+ timer->base = of_iomap(np, 0);
+ if (!timer->base) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
return -ENXIO;
}
- bc_timer.ctrl = bc_timer.base + ctrl_reg;
+
+ if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
+ ctrl_reg = TIMER_CONTROL_REG3399;
+
+ timer->ctrl = timer->base + ctrl_reg;
pclk = of_clk_get_by_name(np, "pclk");
if (IS_ERR(pclk)) {
@@ -139,6 +158,7 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
goto out_unmap;
}
+ timer->pclk = pclk;
timer_clk = of_clk_get_by_name(np, "timer");
if (IS_ERR(timer_clk)) {
@@ -152,8 +172,9 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
pr_err("Failed to enable timer clock\n");
goto out_timer_clk;
}
+ timer->clk = timer_clk;
- bc_timer.freq = clk_get_rate(timer_clk);
+ timer->freq = clk_get_rate(timer_clk);
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
@@ -161,51 +182,126 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
goto out_irq;
}
+ timer->irq = irq;
+
+ rk_timer_interrupt_clear(timer);
+ rk_timer_disable(timer);
+ return 0;
+
+out_irq:
+ clk_disable_unprepare(timer_clk);
+out_timer_clk:
+ clk_disable_unprepare(pclk);
+out_unmap:
+ iounmap(timer->base);
+
+ return ret;
+}
+
+static void __init rk_timer_cleanup(struct rk_timer *timer)
+{
+ clk_disable_unprepare(timer->clk);
+ clk_disable_unprepare(timer->pclk);
+ iounmap(timer->base);
+}
+
+static int __init rk_clkevt_init(struct device_node *np)
+{
+ struct clock_event_device *ce;
+ int ret = -EINVAL;
+
+ rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL);
+ if (!rk_clkevt) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ ret = rk_timer_probe(&rk_clkevt->timer, np);
+ if (ret)
+ goto out_probe;
+
+ ce = &rk_clkevt->ce;
ce->name = TIMER_NAME;
ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_DYNIRQ;
ce->set_next_event = rk_timer_set_next_event;
ce->set_state_shutdown = rk_timer_shutdown;
ce->set_state_periodic = rk_timer_set_periodic;
- ce->irq = irq;
+ ce->irq = rk_clkevt->timer.irq;
ce->cpumask = cpu_possible_mask;
ce->rating = 250;
- rk_timer_interrupt_clear(ce);
- rk_timer_disable(ce);
-
- ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
+ ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER,
+ TIMER_NAME, ce);
if (ret) {
- pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
+ pr_err("Failed to initialize '%s': %d\n",
+ TIMER_NAME, ret);
goto out_irq;
}
- clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
-
+ clockevents_config_and_register(&rk_clkevt->ce,
+ rk_clkevt->timer.freq, 1, UINT_MAX);
return 0;
out_irq:
- clk_disable_unprepare(timer_clk);
-out_timer_clk:
- clk_disable_unprepare(pclk);
-out_unmap:
- iounmap(bc_timer.base);
-
+ rk_timer_cleanup(&rk_clkevt->timer);
+out_probe:
+ kfree(rk_clkevt);
+out:
+ /* Leave rk_clkevt not NULL to prevent future init */
+ rk_clkevt = ERR_PTR(ret);
return ret;
}
-static int __init rk3288_timer_init(struct device_node *np)
+static int __init rk_clksrc_init(struct device_node *np)
{
- return rk_timer_init(np, TIMER_CONTROL_REG3288);
+ int ret = -EINVAL;
+
+ rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL);
+ if (!rk_clksrc) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = rk_timer_probe(rk_clksrc, np);
+ if (ret)
+ goto out_probe;
+
+ rk_timer_update_counter(UINT_MAX, rk_clksrc);
+ rk_timer_enable(rk_clksrc, 0);
+
+ ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0,
+ TIMER_NAME, rk_clksrc->freq, 250, 32,
+ clocksource_mmio_readl_down);
+ if (ret) {
+ pr_err("Failed to register clocksource");
+ goto out_clocksource;
+ }
+
+ sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
+ return 0;
+
+out_clocksource:
+ rk_timer_cleanup(rk_clksrc);
+out_probe:
+ kfree(rk_clksrc);
+out:
+ /* Leave rk_clksrc not NULL to prevent future init */
+ rk_clksrc = ERR_PTR(ret);
+ return ret;
}
-static int __init rk3399_timer_init(struct device_node *np)
+static int __init rk_timer_init(struct device_node *np)
{
- return rk_timer_init(np, TIMER_CONTROL_REG3399);
+ if (!rk_clkevt)
+ return rk_clkevt_init(np);
+
+ if (!rk_clksrc)
+ return rk_clksrc_init(np);
+
+ pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
+ return -EINVAL;
}
-CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
- rk3288_timer_init);
-CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
- rk3399_timer_init);
+CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
+CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
--
2.7.4
^ permalink raw reply related
* [PATCH 23/29] ARM: dts: rockchip: Update compatible property for rk322x timer
From: Daniel Lezcano @ 2017-04-16 20:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492374441-23336-1-git-send-email-daniel.lezcano@linaro.org>
From: Alexander Kochetkov <al.kochet@gmail.com>
Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
to match devicetree bindings.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Suggested-by: Heiko St?bner <heiko@sntech.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm/boot/dts/rk322x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 9dff822..641607d 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -325,7 +325,7 @@
};
timer: timer at 110c0000 {
- compatible = "rockchip,rk3288-timer";
+ compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
reg = <0x110c0000 0x20>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
--
2.7.4
^ permalink raw reply related
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