* [PATCH v2 4/5] pinctrl: imx7ulp: constify struct imx_cfg_params_decode
From: Linus Walleij @ 2018-01-11 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106142553.15322-5-stefan@agner.ch>
On Sat, Jan 6, 2018 at 3:25 PM, Stefan Agner <stefan@agner.ch> wrote:
> The decode parameters are constant mark them const.
>
> Cc: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] ARM64: dts: meson-axg: add RMII pins for ethernet controller
From: Neil Armstrong @ 2018-01-11 9:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2fa28259-cce9-37fc-3bcd-6017a35a052a@amlogic.com>
On 11/01/2018 10:11, Yixun Lan wrote:
> Hi Jerome?
>
> On 01/11/18 16:37, Jerome Brunet wrote:
>> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>>> Comparing to RGMII interface, the RMII interface require few pins.
>>> So it's worth describing them here.
>>>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>
>> The only axg platform we have upstream is the s400 and is using rgmii.
>> May I ask how this was tested ?
>>
> It's true that S400 using RGMII interface.
>
> but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,
>
> This is actually tested with the 'eth_rmii_x_pins' group.
>
> Yixun
>
I pushed the same for GXBB,
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* [PATCH 0/7] Initial Allwinner H6 support
From: Linus Walleij @ 2018-01-11 9:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106041813.46256-1-icenowy@aosc.io>
On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> This patchset adds initial support for the Allwinner H6 SoC.
Can I apply the pin control patches without the clock patches?
Also waiting for Maxime and/or Chen-Yu to provide some review
before merging this.
Yours,
Linus Walleij
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 0/7] Initial Allwinner H6 support
From: Icenowy Zheng @ 2018-01-11 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdY3xY-7-YTCS=QmRQ3hmXiJZ_2M=ZhJRTTMx7XNfXRRSw@mail.gmail.com>
? 2018?1?11???? CST ??5:36:39?Linus Walleij ???
> On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> > This patchset adds initial support for the Allwinner H6 SoC.
>
> Can I apply the pin control patches without the clock patches?
I think it's OK.
Note: on H6 now the pin controller do not depend on
the CCU at all -- it only needs two oscillators now.
>
> Also waiting for Maxime and/or Chen-Yu to provide some review
> before merging this.
>
> Yours,
> Linus Walleij
^ permalink raw reply
* [PATCH 3/4] bcm2835-gpio-exp: Driver for GPIO expander via mailbox service
From: Linus Walleij @ 2018-01-11 9:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180110034557.5sqpbsvt6ly6s2go@tarshish>
On Wed, Jan 10, 2018 at 4:45 AM, Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Linus,
>
> On Wed, Jan 03, 2018 at 11:08:15AM +0100, Linus Walleij wrote:
>> On Tue, Jan 2, 2018 at 2:19 PM, Baruch Siach <baruch@tkos.co.il> wrote:
>> > +#include <linux/err.h>
>> > +#include <linux/gpio.h>
>>
>> Just use
>>
>> #include <linux/driver.h>
>
> You mean linux/gpio/driver.h, right?
Yes.
> I still need linux/gpio.h for GPIOF_DIR_*.
Don't use these, just use 0 and 1 open coded for the
moment (if you check my devel branch, the references to
these flags are gone).
We need to make new defines for the new API.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/9] iommu/of: Drop early initialisation hooks
From: Marek Szyprowski @ 2018-01-11 9:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111082229.24011-2-jeffy.chen@rock-chips.com>
Hi Jeffy,
On 2018-01-11 09:22, Jeffy Chen wrote:
> With the probe-deferral mechanism, early initialisation hooks are no
> longer needed.
>
> Suggested-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> ---
>
> drivers/iommu/arm-smmu-v3.c | 2 +-
> drivers/iommu/arm-smmu.c | 12 ++++++------
> drivers/iommu/exynos-iommu.c | 2 +-
For Exynos IOMMU:
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
IPMMU and MSM IOMMU are no longer multi-platform safe after this patch.
It breaks them in the same way as my commit 928055a01b3f ("iommu/exynos:
Remove custom platform device registration code") broke Exynos IOMMU.
You need a similar fix for them:
https://www.spinics.net/lists/arm-kernel/msg627648.html
> drivers/iommu/ipmmu-vmsa.c | 17 ++---------------
> drivers/iommu/msm_iommu.c | 24 +++++++-----------------
> drivers/iommu/of_iommu.c | 16 ----------------
> drivers/iommu/qcom_iommu.c | 2 +-
> include/linux/of_iommu.h | 6 ++----
> 8 files changed, 20 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 744592d330ca..3f2f1fc68b52 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -2971,7 +2971,7 @@ static struct platform_driver arm_smmu_driver = {
> };
> module_platform_driver(arm_smmu_driver);
>
> -IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", NULL);
> +IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3");
>
> MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
> MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 78d4c6b8f1ba..69e7c60792a8 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -2211,12 +2211,12 @@ static struct platform_driver arm_smmu_driver = {
> };
> module_platform_driver(arm_smmu_driver);
>
> -IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", NULL);
> -IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", NULL);
> -IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", NULL);
> -IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", NULL);
> -IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", NULL);
> -IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", NULL);
> +IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1");
> +IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2");
> +IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400");
> +IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401");
> +IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500");
> +IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2");
>
> MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
> MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> index 79c45650f8de..1c7f926fad0e 100644
> --- a/drivers/iommu/exynos-iommu.c
> +++ b/drivers/iommu/exynos-iommu.c
> @@ -1394,4 +1394,4 @@ static int __init exynos_iommu_init(void)
> }
> core_initcall(exynos_iommu_init);
>
> -IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", NULL);
> +IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu");
> diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
> index 8dce3a9de9d8..07b711bb4b16 100644
> --- a/drivers/iommu/ipmmu-vmsa.c
> +++ b/drivers/iommu/ipmmu-vmsa.c
> @@ -1081,12 +1081,8 @@ static struct platform_driver ipmmu_driver = {
>
> static int __init ipmmu_init(void)
> {
> - static bool setup_done;
> int ret;
>
> - if (setup_done)
> - return 0;
> -
> ret = platform_driver_register(&ipmmu_driver);
> if (ret < 0)
> return ret;
> @@ -1096,7 +1092,6 @@ static int __init ipmmu_init(void)
> bus_set_iommu(&platform_bus_type, &ipmmu_ops);
> #endif
>
> - setup_done = true;
> return 0;
> }
>
> @@ -1109,16 +1104,8 @@ subsys_initcall(ipmmu_init);
> module_exit(ipmmu_exit);
>
> #ifdef CONFIG_IOMMU_DMA
> -static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np)
> -{
> - ipmmu_init();
> - return 0;
> -}
> -
> -IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa",
> - ipmmu_vmsa_iommu_of_setup);
> -IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795",
> - ipmmu_vmsa_iommu_of_setup);
> +IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa");
> +IOMMU_OF_DECLARE(ipmmu_r8a7795_iommu_of, "renesas,ipmmu-r8a7795");
> #endif
>
> MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
> diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
> index 04f4d51ffacb..a41d4251b0a9 100644
> --- a/drivers/iommu/msm_iommu.c
> +++ b/drivers/iommu/msm_iommu.c
> @@ -856,7 +856,7 @@ static struct platform_driver msm_iommu_driver = {
> .remove = msm_iommu_remove,
> };
>
> -static int __init msm_iommu_driver_init(void)
> +static int __init msm_iommu_init(void)
> {
> int ret;
>
> @@ -864,30 +864,20 @@ static int __init msm_iommu_driver_init(void)
> if (ret != 0)
> pr_err("Failed to register IOMMU driver\n");
>
> + bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
> +
> return ret;
> }
>
> -static void __exit msm_iommu_driver_exit(void)
> +static void __exit msm_iommu_exit(void)
> {
> platform_driver_unregister(&msm_iommu_driver);
> }
>
> -subsys_initcall(msm_iommu_driver_init);
> -module_exit(msm_iommu_driver_exit);
> -
> -static int __init msm_iommu_init(void)
> -{
> - bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
> - return 0;
> -}
> -
> -static int __init msm_iommu_of_setup(struct device_node *np)
> -{
> - msm_iommu_init();
> - return 0;
> -}
> +subsys_initcall(msm_iommu_init);
> +module_exit(msm_iommu_exit);
>
> -IOMMU_OF_DECLARE(msm_iommu_of, "qcom,apq8064-iommu", msm_iommu_of_setup);
> +IOMMU_OF_DECLARE(msm_iommu_of, "qcom,apq8064-iommu");
>
> MODULE_LICENSE("GPL v2");
> MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
> index 50947ebb6d17..5c36a8b7656a 100644
> --- a/drivers/iommu/of_iommu.c
> +++ b/drivers/iommu/of_iommu.c
> @@ -231,19 +231,3 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
>
> return ops;
> }
> -
> -static int __init of_iommu_init(void)
> -{
> - struct device_node *np;
> - const struct of_device_id *match, *matches = &__iommu_of_table;
> -
> - for_each_matching_node_and_match(np, matches, &match) {
> - const of_iommu_init_fn init_fn = match->data;
> -
> - if (init_fn && init_fn(np))
> - pr_err("Failed to initialise IOMMU %pOF\n", np);
> - }
> -
> - return 0;
> -}
> -postcore_initcall_sync(of_iommu_init);
> diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
> index e07f02d00c68..65b9c99707f8 100644
> --- a/drivers/iommu/qcom_iommu.c
> +++ b/drivers/iommu/qcom_iommu.c
> @@ -947,7 +947,7 @@ static void __exit qcom_iommu_exit(void)
> module_init(qcom_iommu_init);
> module_exit(qcom_iommu_exit);
>
> -IOMMU_OF_DECLARE(qcom_iommu_dev, "qcom,msm-iommu-v1", NULL);
> +IOMMU_OF_DECLARE(qcom_iommu_dev, "qcom,msm-iommu-v1");
>
> MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations");
> MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h
> index cddfaff4d0b7..ae03752e8e3a 100644
> --- a/include/linux/of_iommu.h
> +++ b/include/linux/of_iommu.h
> @@ -34,9 +34,7 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev,
>
> extern struct of_device_id __iommu_of_table;
>
> -typedef int (*of_iommu_init_fn)(struct device_node *);
> -
> -#define IOMMU_OF_DECLARE(name, compat, fn) \
> - _OF_DECLARE(iommu, name, compat, fn, of_iommu_init_fn)
> +#define IOMMU_OF_DECLARE(name, compat) \
> + OF_DECLARE_1(iommu, name, compat, NULL)
>
> #endif /* __OF_IOMMU_H */
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH] pinctrl: uniphier: refactor drive strength get/set functions
From: Linus Walleij @ 2018-01-11 9:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515573254-8894-1-git-send-email-yamada.masahiro@socionext.com>
On Wed, Jan 10, 2018 at 9:34 AM, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> There is code duplication between uniphier_conf_pin_drive_get() and
> uniphier_conf_pin_drive_set(). Factor out the common code into
> uniphier_conf_get_drvctrl_data().
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/2] pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
From: Linus Walleij @ 2018-01-11 9:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a26c40a8ad2af3cf81b31ae34bc82c1ef80d9279.1515514758.git.sean.wang@mediatek.com>
On Tue, Jan 9, 2018 at 5:28 PM, <sean.wang@mediatek.com> wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> commit d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622
> SoC") leads to the following static checker warning:
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 2/2] pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
From: Linus Walleij @ 2018-01-11 9:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0eb8fd904f9b49d0e992bc2ee725d057f94cf735.1515514758.git.sean.wang@mediatek.com>
On Tue, Jan 9, 2018 at 5:28 PM, <sean.wang@mediatek.com> wrote:
> From: Sean Wang <sean.wang@mediatek.com>
>
> Make consistent error handling of all mtk_hw_get_value occurrences using
> propagating error code from the internal instead of creating a new one.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 0/2] pinctrl: meson: use one uniform 'function' name
From: Linus Walleij @ 2018-01-11 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180108073328.205769-1-yixun.lan@amlogic.com>
On Mon, Jan 8, 2018 at 8:33 AM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> These two patches are general improvement for meson pinctrl driver.
> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name for
> one hardware block even its pin groups live inside two differet hardware domains,
> which for example EE vs AO domain here.
>
> This idea is motivated by Martin's question at [1]
>
> [1]
> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=Gw at mail.gmail.com
There seems to be controversy here so I'd like input from Carlo
and/or Beniamino if possible.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH V5 00/13] drivers: Boot Constraint core
From: Viresh Kumar @ 2018-01-11 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMgeaWd5z7VEiVhs=Ei3ZWZQN0C-p4smTMCy3AYrZ-TdTA@mail.gmail.com>
On 10-01-18, 10:54, Olof Johansson wrote:
> The SoC-specific pieces should preferrably go under drivers/soc
> instead, to reduce cross-tree dependencies when introducing new SoC
> variants.
>
> They're more related to the SoC than to the boot_constraint framework anyway.
Hmm, okay.
> Bikeshed: We've traditionally had really terse and precise names under
> drivers/. This is the first verbose one with a _ in it. Maybe find a
> shorter name or just concatenate to 'bootconstraints'? We didn't call
> it remote_proc or rapid_io, etc, either. :)
Sure.
--
viresh
^ permalink raw reply
* [PATCH linux dev-4.10 0/6] Add support PECI and PECI hwmon drivers
From: Greg KH @ 2018-01-11 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515661011.31850.27.camel@au1.ibm.com>
On Thu, Jan 11, 2018 at 07:56:51PM +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-01-11 at 08:30 +0100, Greg KH wrote:
> > 4.13? Why that kernel? It too is obsolete and insecure and
> > unsupported.
>
> Haha, it's n-1. come on :-)
And, if you use it in a device, it's still totally unsupported and
insecure. Seriously, does no one actually pay attention to the patches
I merge in the stable trees anymore?
Anyway, your other comments are good, glad to see work is progressing
well, and yes it's better than a 2.6.y based kernel, but really, that's
a low bar...
thanks,
greg k-h
^ permalink raw reply
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Andre Przywara @ 2018-01-11 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106042326.46519-1-icenowy@aosc.io>
Hi,
On 06/01/18 04:23, Icenowy Zheng wrote:
> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> have no bus gate clocks.
>
> Add support for this kind of pin controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 ++++++++++++++++++++----------
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
> 2 files changed, 21 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 4b6cb25bc796..68cd505679d9 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
> unsigned int hosc_div, losc_div;
> struct clk *hosc, *losc;
> u8 div, src;
> - int i, ret;
> + int i, ret, clk_count;
> +
> + if (pctl->desc->without_bus_gate)
> + clk_count = 2;
> + else
> + clk_count = 3;
>
> /* Deal with old DTs that didn't have the oscillators */
> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
> goto gpiochip_error;
> }
>
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk)) {
> - ret = PTR_ERR(clk);
> - goto gpiochip_error;
> - }
> + if (!desc->without_bus_gate) {
Do we really need explicit support for that case?
Can't we have something that works automatically?
if (node has clock-names property) (A)
use clocks as enumerated and named there
else if (node has one clock reference) (B)
use this as gate clock, no debounce support
else if (node has no clock property at all) (C)
no gate clock needed, no debounce support
On top of that we should add the clock-names property to all DTs, even
for those with only a "apb" clock. Shouldn't hurt existing kernels.
Possibly even add debounce support for those on the way, if applicable.
So we would just support case (B) and (C) for legacy reasons.
Does that make sense?
Cheers,
Andre.
> + clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + goto gpiochip_error;
> + }
>
> - ret = clk_prepare_enable(clk);
> - if (ret)
> - goto gpiochip_error;
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + goto gpiochip_error;
> + } else {
> + clk = NULL;
> + }
>
> pctl->irq = devm_kcalloc(&pdev->dev,
> pctl->desc->irq_banks,
> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
> return 0;
>
> clk_error:
> - clk_disable_unprepare(clk);
> + if (clk)
> + clk_disable_unprepare(clk);
> gpiochip_error:
> gpiochip_remove(pctl->chip);
> return ret;
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> index 11b128f54ed2..ccb6230f0bb5 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
> unsigned irq_bank_base;
> bool irq_read_needs_mux;
> bool disable_strict_mode;
> + bool without_bus_gate;
> };
>
> struct sunxi_pinctrl_function {
>
^ permalink raw reply
* [PATCH V4 0/3] Map larger kernels at early init
From: Steve Capper @ 2018-01-11 10:11 UTC (permalink / raw)
To: linux-arm-kernel
The early pagetable creation code assumes that a single pgd, pud, pmd
and pte are sufficient to map the kernel text for MMU bringup. For 16KB
granules this is, unfortunately, rarely the case. Some kernels may be too
big even for a 64KB granule employing this scheme.
This patch series addresses the problem in three steps: 1) re-order the
reserved_ttbr0 to allow its address computation to be independent of
swapper_pg_dir size, 2) re-order the trampoline in a similar manner,
and 3) re-write the early pgtable code to allow for multiple page table
entries at each level.
Changes in v4: Reviewed-by's/Tested-by's added, count logic simplified
in last patch.
Changes in v3: Series rebased on top of arm64/for-next/core branch. This
necessitated changes to accommodate kpti (mainly moving the trampiline page
table before the swapper, in patch #2); as well as 52-bit PA (some assembler
rebasing).
Changes in v2: Ack added to patch #1, KASLR space calculation redone
in patch #2.
Steve Capper (3):
arm64: Re-order reserved_ttbr0 in linker script
arm64: entry: Move the trampoline to be before PAN
arm64: Extend early page table code to allow for larger kernels
arch/arm64/include/asm/asm-uaccess.h | 8 +-
arch/arm64/include/asm/kernel-pgtable.h | 47 ++++++++++-
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/include/asm/uaccess.h | 4 +-
arch/arm64/kernel/entry.S | 4 +-
arch/arm64/kernel/head.S | 144 +++++++++++++++++++++++---------
arch/arm64/kernel/vmlinux.lds.S | 15 ++--
arch/arm64/mm/mmu.c | 3 +-
8 files changed, 171 insertions(+), 55 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH V4 1/3] arm64: Re-order reserved_ttbr0 in linker script
From: Steve Capper @ 2018-01-11 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111101159.9748-1-steve.capper@arm.com>
Currently one resolves the location of the reserved_ttbr0 for PAN by
taking a positive offset from swapper_pg_dir. In a future patch we wish
to extend the swapper s.t. its size is determined at link time rather
than comile time, rendering SWAPPER_DIR_SIZE unsuitable for such a low
level calculation.
In this patch we re-arrange the order of the linker script s.t. instead
one computes reserved_ttbr0 by subtracting RESERVED_TTBR0_SIZE from
swapper_pg_dir.
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Changed in V4: added Ard's tags
---
arch/arm64/include/asm/asm-uaccess.h | 8 ++++----
arch/arm64/include/asm/uaccess.h | 4 ++--
arch/arm64/kernel/vmlinux.lds.S | 5 ++---
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
index f4f234b6155e..8719ce122a38 100644
--- a/arch/arm64/include/asm/asm-uaccess.h
+++ b/arch/arm64/include/asm/asm-uaccess.h
@@ -13,11 +13,11 @@
*/
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
.macro __uaccess_ttbr0_disable, tmp1
- mrs \tmp1, ttbr1_el1 // swapper_pg_dir
- add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir
- msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
+ mrs \tmp1, ttbr1_el1 // swapper_pg_dir
+ sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir
+ msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
isb
- sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE
+ add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE
bic \tmp1, \tmp1, #TTBR_ASID_MASK
msr ttbr1_el1, \tmp1 // set reserved ASID
isb
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 6eadf55ebaf0..e269d35372cf 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -108,8 +108,8 @@ static inline void __uaccess_ttbr0_disable(void)
unsigned long ttbr;
ttbr = read_sysreg(ttbr1_el1);
- /* reserved_ttbr0 placed at the end of swapper_pg_dir */
- write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
+ /* reserved_ttbr0 placed before swapper_pg_dir */
+ write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1);
isb();
/* Set reserved ASID */
ttbr &= ~TTBR_ASID_MASK;
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index ddfd3c0942f7..8e567de8f369 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -218,13 +218,12 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
idmap_pg_dir = .;
. += IDMAP_DIR_SIZE;
- swapper_pg_dir = .;
- . += SWAPPER_DIR_SIZE;
-
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
reserved_ttbr0 = .;
. += RESERVED_TTBR0_SIZE;
#endif
+ swapper_pg_dir = .;
+ . += SWAPPER_DIR_SIZE;
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
tramp_pg_dir = .;
--
2.11.0
^ permalink raw reply related
* [PATCH V4 2/3] arm64: entry: Move the trampoline to be before PAN
From: Steve Capper @ 2018-01-11 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111101159.9748-1-steve.capper@arm.com>
The trampoline page tables are positioned after the early page tables in
the kernel linker script.
As we are about to change the early page table logic to resolve the
swapper size at link time as opposed to compile time, the
SWAPPER_DIR_SIZE variable (currently used to locate the trampline)
will be rendered unsuitable for low level assembler.
This patch solves this issue by moving the trampoline before the PAN
page tables. The offset to the trampoline from ttbr1 can then be
expressed by: PAGE_SIZE + RESERVED_TTBR0_SIZE, which is available to the
entry assembler.
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Changed in V4: added Ard's tags
---
arch/arm64/kernel/entry.S | 4 ++--
arch/arm64/kernel/vmlinux.lds.S | 11 ++++++-----
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 031392ee5f47..7902d8145b9a 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -987,7 +987,7 @@ __ni_sys_trace:
.macro tramp_map_kernel, tmp
mrs \tmp, ttbr1_el1
- sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
bic \tmp, \tmp, #USER_ASID_FLAG
msr ttbr1_el1, \tmp
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
@@ -1006,7 +1006,7 @@ alternative_else_nop_endif
.macro tramp_unmap_kernel, tmp
mrs \tmp, ttbr1_el1
- add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
orr \tmp, \tmp, #USER_ASID_FLAG
msr ttbr1_el1, \tmp
/*
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 8e567de8f369..4c7112a47469 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -218,6 +218,12 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
idmap_pg_dir = .;
. += IDMAP_DIR_SIZE;
+
+#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
+ tramp_pg_dir = .;
+ . += PAGE_SIZE;
+#endif
+
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
reserved_ttbr0 = .;
. += RESERVED_TTBR0_SIZE;
@@ -225,11 +231,6 @@ SECTIONS
swapper_pg_dir = .;
. += SWAPPER_DIR_SIZE;
-#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
- tramp_pg_dir = .;
- . += PAGE_SIZE;
-#endif
-
__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
_end = .;
--
2.11.0
^ permalink raw reply related
* [PATCH V4 3/3] arm64: Extend early page table code to allow for larger kernels
From: Steve Capper @ 2018-01-11 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111101159.9748-1-steve.capper@arm.com>
Currently the early assembler page table code assumes that precisely
1xpgd, 1xpud, 1xpmd are sufficient to represent the early kernel text
mappings.
Unfortunately this is rarely the case when running with a 16KB granule,
and we also run into limits with 4KB granule when building much larger
kernels.
This patch re-writes the early page table logic to compute indices of
mappings for each level of page table, and if multiple indices are
required, the next-level page table is scaled up accordingly.
Also the required size of the swapper_pg_dir is computed at link time
to cover the mapping [KIMAGE_ADDR + VOFFSET, _end]. When KASLR is
enabled, an extra page is set aside for each level that may require extra
entries at runtime.
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Changed in V4:
local loop variable now unique to macro instatiation,
count logic simplified
---
arch/arm64/include/asm/kernel-pgtable.h | 47 ++++++++++-
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/kernel/head.S | 144 +++++++++++++++++++++++---------
arch/arm64/kernel/vmlinux.lds.S | 1 +
arch/arm64/mm/mmu.c | 3 +-
5 files changed, 156 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 77a27af01371..82386e860dd2 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -52,7 +52,52 @@
#define IDMAP_PGTABLE_LEVELS (ARM64_HW_PGTABLE_LEVELS(PHYS_MASK_SHIFT))
#endif
-#define SWAPPER_DIR_SIZE (SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)
+
+/*
+ * If KASLR is enabled, then an offset K is added to the kernel address
+ * space. The bottom 21 bits of this offset are zero to guarantee 2MB
+ * alignment for PA and VA.
+ *
+ * For each pagetable level of the swapper, we know that the shift will
+ * be larger than 21 (for the 4KB granule case we use section maps thus
+ * the smallest shift is actually 30) thus there is the possibility that
+ * KASLR can increase the number of pagetable entries by 1, so we make
+ * room for this extra entry.
+ *
+ * Note KASLR cannot increase the number of required entries for a level
+ * by more than one because it increments both the virtual start and end
+ * addresses equally (the extra entry comes from the case where the end
+ * address is just pushed over a boundary and the start address isn't).
+ */
+
+#ifdef CONFIG_RANDOMIZE_BASE
+#define EARLY_KASLR (1)
+#else
+#define EARLY_KASLR (0)
+#endif
+
+#define EARLY_ENTRIES(vstart, vend, shift) (((vend) >> (shift)) \
+ - ((vstart) >> (shift)) + 1 + EARLY_KASLR)
+
+#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
+
+#if SWAPPER_PGTABLE_LEVELS > 3
+#define EARLY_PUDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PUD_SHIFT))
+#else
+#define EARLY_PUDS(vstart, vend) (0)
+#endif
+
+#if SWAPPER_PGTABLE_LEVELS > 2
+#define EARLY_PMDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, SWAPPER_TABLE_SHIFT))
+#else
+#define EARLY_PMDS(vstart, vend) (0)
+#endif
+
+#define EARLY_PAGES(vstart, vend) ( 1 /* PGDIR page */ \
+ + EARLY_PGDS((vstart), (vend)) /* each PGDIR needs a next level page table */ \
+ + EARLY_PUDS((vstart), (vend)) /* each PUD needs a next level page table */ \
+ + EARLY_PMDS((vstart), (vend))) /* each PMD needs a next level page table */
+#define SWAPPER_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end))
#define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE)
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index bfa237e892f1..54b0a8398055 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -706,6 +706,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm,
#endif
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern pgd_t swapper_pg_end[];
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 66f01869e97c..95748a00eb89 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -191,44 +191,109 @@ ENDPROC(preserve_boot_args)
.endm
/*
- * Macro to populate the PGD (and possibily PUD) for the corresponding
- * block entry in the next level (tbl) for the given virtual address.
+ * Macro to populate page table entries, these entries can be pointers to the next level
+ * or last level entries pointing to physical memory.
*
- * Preserves: tbl, next, virt
- * Corrupts: ptrs_per_pgd, tmp1, tmp2
+ * tbl: page table address
+ * rtbl: pointer to page table or physical memory
+ * index: start index to write
+ * eindex: end index to write - [index, eindex] written to
+ * flags: flags for pagetable entry to or in
+ * inc: increment to rtbl between each entry
+ * tmp1: temporary variable
+ *
+ * Preserves: tbl, eindex, flags, inc
+ * Corrupts: index, tmp1
+ * Returns: rtbl
*/
- .macro create_pgd_entry, tbl, virt, ptrs_per_pgd, tmp1, tmp2
- create_table_entry \tbl, \virt, PGDIR_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#if SWAPPER_PGTABLE_LEVELS > 3
- mov \ptrs_per_pgd, PTRS_PER_PUD
- create_table_entry \tbl, \virt, PUD_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#endif
-#if SWAPPER_PGTABLE_LEVELS > 2
- mov \ptrs_per_pgd, PTRS_PER_PTE
- create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#endif
+ .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
+.Lpe\@: phys_to_pte \rtbl, \tmp1
+ orr \tmp1, \tmp1, \flags // tmp1 = table entry
+ str \tmp1, [\tbl, \index, lsl #3]
+ add \rtbl, \rtbl, \inc // rtbl = pa next level
+ add \index, \index, #1
+ cmp \index, \eindex
+ b.ls .Lpe\@
+ .endm
+
+/*
+ * Compute indices of table entries from virtual address range. If multiple entries
+ * were needed in the previous page table level then the next page table level is assumed
+ * to be composed of multiple pages. (This effectively scales the end index).
+ *
+ * vstart: virtual address of start of range
+ * vend: virtual address of end of range
+ * shift: shift used to transform virtual address into index
+ * ptrs: number of entries in page table
+ * istart: index in table corresponding to vstart
+ * iend: index in table corresponding to vend
+ * count: On entry: how many extra entries were required in previous level, scales
+ * our end index.
+ * On exit: returns how many extra entries required for next page table level
+ *
+ * Preserves: vstart, vend, shift, ptrs
+ * Returns: istart, iend, count
+ */
+ .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
+ lsr \iend, \vend, \shift
+ mov \istart, \ptrs
+ sub \istart, \istart, #1
+ and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
+ mov \istart, \ptrs
+ mul \istart, \istart, \count
+ add \iend, \iend, \istart // iend += (count - 1) * ptrs
+ // our entries span multiple tables
+
+ lsr \istart, \vstart, \shift
+ mov \count, \ptrs
+ sub \count, \count, #1
+ and \istart, \istart, \count
+
+ sub \count, \iend, \istart
.endm
/*
- * Macro to populate block entries in the page table for the start..end
- * virtual range (inclusive).
+ * Map memory for specified virtual address range. Each level of page table needed supports
+ * multiple entries. If a level requires n entries the next page table level is assumed to be
+ * formed from n pages.
+ *
+ * tbl: location of page table
+ * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
+ * vstart: start address to map
+ * vend: end address to map - we map [vstart, vend]
+ * flags: flags to use to map last level entries
+ * phys: physical address corresponding to vstart - physical memory is contiguous
+ * pgds: the number of pgd entries
*
- * Preserves: tbl, flags
- * Corrupts: phys, start, end, tmp, pstate
+ * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
+ * Preserves: vstart, vend, flags
+ * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
*/
- .macro create_block_map, tbl, flags, phys, start, end, tmp
- lsr \start, \start, #SWAPPER_BLOCK_SHIFT
- and \start, \start, #PTRS_PER_PTE - 1 // table index
- bic \phys, \phys, #SWAPPER_BLOCK_SIZE - 1
- lsr \end, \end, #SWAPPER_BLOCK_SHIFT
- and \end, \end, #PTRS_PER_PTE - 1 // table end index
-9999: phys_to_pte \phys, \tmp
- orr \tmp, \tmp, \flags // table entry
- str \tmp, [\tbl, \start, lsl #3] // store the entry
- add \start, \start, #1 // next entry
- add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
- cmp \start, \end
- b.ls 9999b
+ .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
+ add \rtbl, \tbl, #PAGE_SIZE
+ mov \sv, \rtbl
+ mov \count, #0
+ compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+ mov \sv, \rtbl
+
+#if SWAPPER_PGTABLE_LEVELS > 3
+ compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+ mov \sv, \rtbl
+#endif
+
+#if SWAPPER_PGTABLE_LEVELS > 2
+ compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+#endif
+
+ compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
+ bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
+ populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
.endm
/*
@@ -246,14 +311,16 @@ __create_page_tables:
* dirty cache lines being evicted.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
bl __inval_dcache_area
/*
* Clear the idmap and swapper page tables.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
1: stp xzr, xzr, [x0], #16
stp xzr, xzr, [x0], #16
stp xzr, xzr, [x0], #16
@@ -318,10 +385,10 @@ __create_page_tables:
#endif
1:
ldr_l x4, idmap_ptrs_per_pgd
- create_pgd_entry x0, x3, x4, x5, x6
mov x5, x3 // __pa(__idmap_text_start)
adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
- create_block_map x0, x7, x3, x5, x6, x4
+
+ map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
/*
* Map the kernel image (starting with PHYS_OFFSET).
@@ -330,12 +397,12 @@ __create_page_tables:
mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
add x5, x5, x23 // add KASLR displacement
mov x4, PTRS_PER_PGD
- create_pgd_entry x0, x5, x4, x3, x6
adrp x6, _end // runtime __pa(_end)
adrp x3, _text // runtime __pa(_text)
sub x6, x6, x3 // _end - _text
add x6, x6, x5 // runtime __va(_end)
- create_block_map x0, x7, x3, x5, x6, x4
+
+ map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
/*
* Since the page tables have been populated with non-cacheable
@@ -343,7 +410,8 @@ __create_page_tables:
* tables again to remove any speculatively loaded cache lines.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
dmb sy
bl __inval_dcache_area
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 4c7112a47469..0221aca6493d 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -230,6 +230,7 @@ SECTIONS
#endif
swapper_pg_dir = .;
. += SWAPPER_DIR_SIZE;
+ swapper_pg_end = .;
__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
_end = .;
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 4071602031ed..fdac11979bae 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -644,7 +644,8 @@ void __init paging_init(void)
* allocated with it.
*/
memblock_free(__pa_symbol(swapper_pg_dir) + PAGE_SIZE,
- SWAPPER_DIR_SIZE - PAGE_SIZE);
+ __pa_symbol(swapper_pg_end) - __pa_symbol(swapper_pg_dir)
+ - PAGE_SIZE);
}
/*
--
2.11.0
^ permalink raw reply related
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Chen-Yu Tsai @ 2018-01-11 10:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2ca1ee96-8dc6-c80b-ae11-45895d6a8484@arm.com>
On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>>
>> Add support for this kind of pin controllers.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 ++++++++++++++++++++----------
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> index 4b6cb25bc796..68cd505679d9 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
>> unsigned int hosc_div, losc_div;
>> struct clk *hosc, *losc;
>> u8 div, src;
>> - int i, ret;
>> + int i, ret, clk_count;
>> +
>> + if (pctl->desc->without_bus_gate)
>> + clk_count = 2;
>> + else
>> + clk_count = 3;
>>
>> /* Deal with old DTs that didn't have the oscillators */
>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
>> goto gpiochip_error;
>> }
>>
>> - clk = devm_clk_get(&pdev->dev, NULL);
>> - if (IS_ERR(clk)) {
>> - ret = PTR_ERR(clk);
>> - goto gpiochip_error;
>> - }
>> + if (!desc->without_bus_gate) {
>
> Do we really need explicit support for that case?
> Can't we have something that works automatically?
>
> if (node has clock-names property) (A)
> use clocks as enumerated and named there
You still need to know if the hardware has a bus gate or not.
If it's missing, and it's disabled, you end up with unusable
hardware.
Unless you are fully trusting the device tree to be correct.
IMHO that makes for hard to find bugs during SoC bringup.
ChenYu
> else if (node has one clock reference) (B)
> use this as gate clock, no debounce support
> else if (node has no clock property at all) (C)
> no gate clock needed, no debounce support
>
> On top of that we should add the clock-names property to all DTs, even
> for those with only a "apb" clock. Shouldn't hurt existing kernels.
> Possibly even add debounce support for those on the way, if applicable.
>
> So we would just support case (B) and (C) for legacy reasons.
>
> Does that make sense?
>
> Cheers,
> Andre.
>
>> + clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(clk)) {
>> + ret = PTR_ERR(clk);
>> + goto gpiochip_error;
>> + }
>>
>> - ret = clk_prepare_enable(clk);
>> - if (ret)
>> - goto gpiochip_error;
>> + ret = clk_prepare_enable(clk);
>> + if (ret)
>> + goto gpiochip_error;
>> + } else {
>> + clk = NULL;
>> + }
>>
>> pctl->irq = devm_kcalloc(&pdev->dev,
>> pctl->desc->irq_banks,
>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
>> return 0;
>>
>> clk_error:
>> - clk_disable_unprepare(clk);
>> + if (clk)
>> + clk_disable_unprepare(clk);
>> gpiochip_error:
>> gpiochip_remove(pctl->chip);
>> return ret;
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> index 11b128f54ed2..ccb6230f0bb5 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>> unsigned irq_bank_base;
>> bool irq_read_needs_mux;
>> bool disable_strict_mode;
>> + bool without_bus_gate;
>> };
>>
>> struct sunxi_pinctrl_function {
>>
^ permalink raw reply
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Icenowy Zheng @ 2018-01-11 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2ca1ee96-8dc6-c80b-ae11-45895d6a8484@arm.com>
? 2018?1?11? GMT+08:00 ??6:08:19, Andre Przywara <andre.przywara@arm.com> ??:
>Hi,
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>>
>> Add support for this kind of pin controllers.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
>++++++++++++++++++++----------
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> index 4b6cb25bc796..68cd505679d9 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
>sunxi_pinctrl *pctl,
>> unsigned int hosc_div, losc_div;
>> struct clk *hosc, *losc;
>> u8 div, src;
>> - int i, ret;
>> + int i, ret, clk_count;
>> +
>> + if (pctl->desc->without_bus_gate)
>> + clk_count = 2;
>> + else
>> + clk_count = 3;
>>
>> /* Deal with old DTs that didn't have the oscillators */
>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") !=
>3)
>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> goto gpiochip_error;
>> }
>>
>> - clk = devm_clk_get(&pdev->dev, NULL);
>> - if (IS_ERR(clk)) {
>> - ret = PTR_ERR(clk);
>> - goto gpiochip_error;
>> - }
>> + if (!desc->without_bus_gate) {
>
>Do we really need explicit support for that case?
>Can't we have something that works automatically?
It can be a sanity check. When a SoC comes with bus gate
support but no apb is provided, there's something wrong.
>
>if (node has clock-names property) (A)
> use clocks as enumerated and named there
>else if (node has one clock reference) (B)
> use this as gate clock, no debounce support
>else if (node has no clock property at all) (C)
> no gate clock needed, no debounce support
This should not happen in practice, as no gate clock is implemented
after debounce.
>
>On top of that we should add the clock-names property to all DTs, even
>for those with only a "apb" clock. Shouldn't hurt existing kernels.
>Possibly even add debounce support for those on the way, if applicable.
>
>So we would just support case (B) and (C) for legacy reasons.
>
>Does that make sense?
>
>Cheers,
>Andre.
>
>> + clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(clk)) {
>> + ret = PTR_ERR(clk);
>> + goto gpiochip_error;
>> + }
>>
>> - ret = clk_prepare_enable(clk);
>> - if (ret)
>> - goto gpiochip_error;
>> + ret = clk_prepare_enable(clk);
>> + if (ret)
>> + goto gpiochip_error;
>> + } else {
>> + clk = NULL;
>> + }
>>
>> pctl->irq = devm_kcalloc(&pdev->dev,
>> pctl->desc->irq_banks,
>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct
>platform_device *pdev,
>> return 0;
>>
>> clk_error:
>> - clk_disable_unprepare(clk);
>> + if (clk)
>> + clk_disable_unprepare(clk);
>> gpiochip_error:
>> gpiochip_remove(pctl->chip);
>> return ret;
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> index 11b128f54ed2..ccb6230f0bb5 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>> unsigned irq_bank_base;
>> bool irq_read_needs_mux;
>> bool disable_strict_mode;
>> + bool without_bus_gate;
>> };
>>
>> struct sunxi_pinctrl_function {
>>
^ permalink raw reply
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Andre Przywara @ 2018-01-11 10:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v64E-XOHVJG0Q-uZeCAdxF37QSVCDfiYmqtv7ydvseQwrw@mail.gmail.com>
Hi,
On 11/01/18 10:14, Chen-Yu Tsai wrote:
> On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przywara@arm.com> wrote:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus gate clocks.
>>>
>>> Add support for this kind of pin controllers.
>>>
>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>> ---
>>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 ++++++++++++++++++++----------
>>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> index 4b6cb25bc796..68cd505679d9 100644
>>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
>>> unsigned int hosc_div, losc_div;
>>> struct clk *hosc, *losc;
>>> u8 div, src;
>>> - int i, ret;
>>> + int i, ret, clk_count;
>>> +
>>> + if (pctl->desc->without_bus_gate)
>>> + clk_count = 2;
>>> + else
>>> + clk_count = 3;
>>>
>>> /* Deal with old DTs that didn't have the oscillators */
>>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
>>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
>>> goto gpiochip_error;
>>> }
>>>
>>> - clk = devm_clk_get(&pdev->dev, NULL);
>>> - if (IS_ERR(clk)) {
>>> - ret = PTR_ERR(clk);
>>> - goto gpiochip_error;
>>> - }
>>> + if (!desc->without_bus_gate) {
>>
>> Do we really need explicit support for that case?
>> Can't we have something that works automatically?
>>
>> if (node has clock-names property) (A)
>> use clocks as enumerated and named there
>
> You still need to know if the hardware has a bus gate or not.
> If it's missing, and it's disabled, you end up with unusable
> hardware.
Yes. So what? If you have a broken DT, it will not work. Just don't do
it. I don't understand why we want to defend against this case.
> Unless you are fully trusting the device tree to be correct.
Sorry, but what else do we trust?
> IMHO that makes for hard to find bugs during SoC bringup.
I am not sure if that is really an issue. I would expect people doing
SoC bringup to be able to cope with those kinds of problems.
Cheers,
Andre.
>
> ChenYu
>
>> else if (node has one clock reference) (B)
>> use this as gate clock, no debounce support
>> else if (node has no clock property at all) (C)
>> no gate clock needed, no debounce support
>>
>> On top of that we should add the clock-names property to all DTs, even
>> for those with only a "apb" clock. Shouldn't hurt existing kernels.
>> Possibly even add debounce support for those on the way, if applicable.
>>
>> So we would just support case (B) and (C) for legacy reasons.
>>
>> Does that make sense?
>>
>> Cheers,
>> Andre.
>>
>>> + clk = devm_clk_get(&pdev->dev, NULL);
>>> + if (IS_ERR(clk)) {
>>> + ret = PTR_ERR(clk);
>>> + goto gpiochip_error;
>>> + }
>>>
>>> - ret = clk_prepare_enable(clk);
>>> - if (ret)
>>> - goto gpiochip_error;
>>> + ret = clk_prepare_enable(clk);
>>> + if (ret)
>>> + goto gpiochip_error;
>>> + } else {
>>> + clk = NULL;
>>> + }
>>>
>>> pctl->irq = devm_kcalloc(&pdev->dev,
>>> pctl->desc->irq_banks,
>>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
>>> return 0;
>>>
>>> clk_error:
>>> - clk_disable_unprepare(clk);
>>> + if (clk)
>>> + clk_disable_unprepare(clk);
>>> gpiochip_error:
>>> gpiochip_remove(pctl->chip);
>>> return ret;
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> index 11b128f54ed2..ccb6230f0bb5 100644
>>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>>> unsigned irq_bank_base;
>>> bool irq_read_needs_mux;
>>> bool disable_strict_mode;
>>> + bool without_bus_gate;
>>> };
>>>
>>> struct sunxi_pinctrl_function {
>>>
^ permalink raw reply
* [PATCH 34/38] arm: Implement thread_struct whitelist for hardened usercopy
From: Russell King - ARM Linux @ 2018-01-11 10:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515636190-24061-35-git-send-email-keescook@chromium.org>
On Wed, Jan 10, 2018 at 06:03:06PM -0800, Kees Cook wrote:
> ARM does not carry FPU state in the thread structure, so it can declare
> no usercopy whitelist at all.
This comment seems to be misleading. We have stored FP state in the
thread structure for a long time - for example, VFP state is stored
in thread->vfpstate.hard, so we _do_ have floating point state in
the thread structure.
What I think this commit message needs to describe is why we don't
need a whitelist _despite_ having FP state in the thread structure.
At the moment, the commit message is making me think that this patch
is wrong and will introduce a regression.
Thanks.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Ingo Molnar <mingo@kernel.org>
> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
> Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
> Cc: linux-arm-kernel at lists.infradead.org
> Signed-off-by: Kees Cook <keescook@chromium.org>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/include/asm/processor.h | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 51c8df561077..3ea00d65f35d 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -50,6 +50,7 @@ config ARM
> select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
> select HAVE_ARCH_MMAP_RND_BITS if MMU
> select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
> + select HAVE_ARCH_THREAD_STRUCT_WHITELIST
> select HAVE_ARCH_TRACEHOOK
> select HAVE_ARM_SMCCC if CPU_V7
> select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index 338cbe0a18ef..01a41be58d43 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -45,6 +45,13 @@ struct thread_struct {
> struct debug_info debug;
> };
>
> +/* Nothing needs to be usercopy-whitelisted from thread_struct. */
> +static inline void arch_thread_struct_whitelist(unsigned long *offset,
> + unsigned long *size)
> +{
> + *offset = *size = 0;
> +}
> +
> #define INIT_THREAD { }
>
> #define start_thread(regs,pc,sp) \
> --
> 2.7.4
>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH] IIO: ADC: stm32-dfsdm: avoid unused-variable warning
From: Arnd Bergmann @ 2018-01-11 10:34 UTC (permalink / raw)
To: linux-arm-kernel
Building with CONFIG_OF disabled produces a compiler warning:
drivers/iio/adc/stm32-dfsdm-core.c: In function 'stm32_dfsdm_probe':
drivers/iio/adc/stm32-dfsdm-core.c:245:22: error: unused variable 'pnode' [-Werror=unused-variable]
This removes the variable and open-codes it in the only place
it gets used to avoid that warning.
Fixes: bed73904e76f ("IIO: ADC: add stm32 DFSDM core support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/iio/adc/stm32-dfsdm-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c
index 72427414db7f..6cd655f8239b 100644
--- a/drivers/iio/adc/stm32-dfsdm-core.c
+++ b/drivers/iio/adc/stm32-dfsdm-core.c
@@ -242,7 +242,6 @@ MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
static int stm32_dfsdm_probe(struct platform_device *pdev)
{
struct dfsdm_priv *priv;
- struct device_node *pnode = pdev->dev.of_node;
const struct of_device_id *of_id;
const struct stm32_dfsdm_dev_data *dev_data;
struct stm32_dfsdm *dfsdm;
@@ -254,7 +253,7 @@ static int stm32_dfsdm_probe(struct platform_device *pdev)
priv->pdev = pdev;
- of_id = of_match_node(stm32_dfsdm_of_match, pnode);
+ of_id = of_match_node(stm32_dfsdm_of_match, pdev->dev.of_node);
if (!of_id->data) {
dev_err(&pdev->dev, "Data associated to device is missing\n");
return -EINVAL;
--
2.9.0
^ permalink raw reply related
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Maxime Ripard @ 2018-01-11 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ba83f00d-c1e5-6f6a-84df-04169860c7eb@arm.com>
On Thu, Jan 11, 2018 at 10:23:52AM +0000, Andre Przywara wrote:
> Hi,
>
> On 11/01/18 10:14, Chen-Yu Tsai wrote:
> > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> Hi,
> >>
> >> On 06/01/18 04:23, Icenowy Zheng wrote:
> >>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> >>> have no bus gate clocks.
> >>>
> >>> Add support for this kind of pin controllers.
> >>>
> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>> ---
> >>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 ++++++++++++++++++++----------
> >>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
> >>> 2 files changed, 21 insertions(+), 10 deletions(-)
> >>>
> >>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> >>> index 4b6cb25bc796..68cd505679d9 100644
> >>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> >>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> >>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
> >>> unsigned int hosc_div, losc_div;
> >>> struct clk *hosc, *losc;
> >>> u8 div, src;
> >>> - int i, ret;
> >>> + int i, ret, clk_count;
> >>> +
> >>> + if (pctl->desc->without_bus_gate)
> >>> + clk_count = 2;
> >>> + else
> >>> + clk_count = 3;
> >>>
> >>> /* Deal with old DTs that didn't have the oscillators */
> >>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") != 3)
> >>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
> >>> goto gpiochip_error;
> >>> }
> >>>
> >>> - clk = devm_clk_get(&pdev->dev, NULL);
> >>> - if (IS_ERR(clk)) {
> >>> - ret = PTR_ERR(clk);
> >>> - goto gpiochip_error;
> >>> - }
> >>> + if (!desc->without_bus_gate) {
> >>
> >> Do we really need explicit support for that case?
> >> Can't we have something that works automatically?
> >>
> >> if (node has clock-names property) (A)
> >> use clocks as enumerated and named there
> >
> > You still need to know if the hardware has a bus gate or not.
> > If it's missing, and it's disabled, you end up with unusable
> > hardware.
>
> Yes. So what? If you have a broken DT, it will not work. Just don't do
> it. I don't understand why we want to defend against this case.
This is not the point, but rather: if we have a way to detect easily
that the device tree is missing a property that is missing in our
binding, why shouldn't we do it?
We're already doing it for reg and interrupts for example, why not for
the clocks?
> > Unless you are fully trusting the device tree to be correct.
>
> Sorry, but what else do we trust?
>
> > IMHO that makes for hard to find bugs during SoC bringup.
>
> I am not sure if that is really an issue. I would expect people
> doing SoC bringup to be able to cope with those kinds of problems.
Riiiight, because it worked so well in the past. We definitely didn't
overlooked some clocks used for debouncing in this particular driver,
or some to get the timekeeping right in the RTC.
The argument that "anyone who codes in the kernel should just know
better" doesn't work, on multiple levels. Because anyone that actually
knows better can make a mistake or overlook some feature (because you
didn't have your morning coffee yet, or because it was undocumented)
and because you just make someone that doesn't feel bad.
So, yes, we cannot not trust the device tree. But if we have a way to
detect simple mistakes in the binding, we should also do it.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180111/5ebbcbd0/attachment-0001.sig>
^ permalink raw reply
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Andre Przywara @ 2018-01-11 10:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <08CB03C2-1253-4072-B8AC-D3F1253C8A85@aosc.io>
Hi,
On 11/01/18 10:15, Icenowy Zheng wrote:
>
>
> ? 2018?1?11? GMT+08:00 ??6:08:19, Andre Przywara <andre.przywara@arm.com> ??:
>> Hi,
>>
>> On 06/01/18 04:23, Icenowy Zheng wrote:
>>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>>> have no bus gate clocks.
>>>
>>> Add support for this kind of pin controllers.
>>>
>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>> ---
>>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
>> ++++++++++++++++++++----------
>>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
>>> 2 files changed, 21 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> index 4b6cb25bc796..68cd505679d9 100644
>>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
>> sunxi_pinctrl *pctl,
>>> unsigned int hosc_div, losc_div;
>>> struct clk *hosc, *losc;
>>> u8 div, src;
>>> - int i, ret;
>>> + int i, ret, clk_count;
>>> +
>>> + if (pctl->desc->without_bus_gate)
>>> + clk_count = 2;
>>> + else
>>> + clk_count = 3;
>>>
>>> /* Deal with old DTs that didn't have the oscillators */
>>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells") !=
>> 3)
Just spotted: I guess you wanted to compare against that computed value
here?
But I wonder if we can get rid of this check at all? Don't we rely on
clock-names and input-debounce anyway? So we will bail out later anyway
if the DT does not have those?
Why do we need this check then?
>>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
>> platform_device *pdev,
>>> goto gpiochip_error;
>>> }
>>>
>>> - clk = devm_clk_get(&pdev->dev, NULL);
>>> - if (IS_ERR(clk)) {
>>> - ret = PTR_ERR(clk);
>>> - goto gpiochip_error;
>>> - }
>>> + if (!desc->without_bus_gate) {
>>
>> Do we really need explicit support for that case?
>> Can't we have something that works automatically?
>
> It can be a sanity check. When a SoC comes with bus gate
> support but no apb is provided, there's something wrong.
>
>>
>> if (node has clock-names property) (A)
>> use clocks as enumerated and named there
>> else if (node has one clock reference) (B)
>> use this as gate clock, no debounce support
>> else if (node has no clock property at all) (C)
>> no gate clock needed, no debounce support
>
> This should not happen in practice, as no gate clock is implemented
> after debounce.
But still you seem to somewhat support it with your changes above - by
bailing out if there aren't two clocks.
This kind of explicitly checking for a certain number of clocks sounds
not very robust and future proof to me, hence the suggestion to get rid
of it.
Cheers,
Andre.
>>
>> On top of that we should add the clock-names property to all DTs, even
>> for those with only a "apb" clock. Shouldn't hurt existing kernels.
>> Possibly even add debounce support for those on the way, if applicable.
>>
>> So we would just support case (B) and (C) for legacy reasons.
>>
>> Does that make sense?
>>
>> Cheers,
>> Andre.
>>
>>> + clk = devm_clk_get(&pdev->dev, NULL);
>>> + if (IS_ERR(clk)) {
>>> + ret = PTR_ERR(clk);
>>> + goto gpiochip_error;
>>> + }
>>>
>>> - ret = clk_prepare_enable(clk);
>>> - if (ret)
>>> - goto gpiochip_error;
>>> + ret = clk_prepare_enable(clk);
>>> + if (ret)
>>> + goto gpiochip_error;
>>> + } else {
>>> + clk = NULL;
>>> + }
>>>
>>> pctl->irq = devm_kcalloc(&pdev->dev,
>>> pctl->desc->irq_banks,
>>> @@ -1425,7 +1434,8 @@ int sunxi_pinctrl_init_with_variant(struct
>> platform_device *pdev,
>>> return 0;
>>>
>>> clk_error:
>>> - clk_disable_unprepare(clk);
>>> + if (clk)
>>> + clk_disable_unprepare(clk);
>>> gpiochip_error:
>>> gpiochip_remove(pctl->chip);
>>> return ret;
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> index 11b128f54ed2..ccb6230f0bb5 100644
>>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
>>> @@ -113,6 +113,7 @@ struct sunxi_pinctrl_desc {
>>> unsigned irq_bank_base;
>>> bool irq_read_needs_mux;
>>> bool disable_strict_mode;
>>> + bool without_bus_gate;
>>> };
>>>
>>> struct sunxi_pinctrl_function {
>>>
^ permalink raw reply
* [linux-sunxi] [PATCH 1/7] pinctrl: sunxi: add support for pin controllers without bus gate
From: Icenowy Zheng @ 2018-01-11 10:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111104100.j5rwitma3wgtdivm@flea.lan>
? 2018?1?11???? CST ??6:41:00?Maxime Ripard ???
> On Thu, Jan 11, 2018 at 10:23:52AM +0000, Andre Przywara wrote:
> > Hi,
> >
> > On 11/01/18 10:14, Chen-Yu Tsai wrote:
> > > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara <andre.przywara@arm.com>
wrote:
> > >> Hi,
> > >>
> > >> On 06/01/18 04:23, Icenowy Zheng wrote:
> > >>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
> > >>> have no bus gate clocks.
> > >>>
> > >>> Add support for this kind of pin controllers.
> > >>>
> > >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > >>> ---
> > >>>
> > >>> drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30
> > >>> ++++++++++++++++++++----------
> > >>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
> > >>> 2 files changed, 21 insertions(+), 10 deletions(-)
> > >>>
> > >>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index
> > >>> 4b6cb25bc796..68cd505679d9 100644
> > >>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> > >>> @@ -1182,7 +1182,12 @@ static int sunxi_pinctrl_setup_debounce(struct
> > >>> sunxi_pinctrl *pctl,> >>>
> > >>> unsigned int hosc_div, losc_div;
> > >>> struct clk *hosc, *losc;
> > >>> u8 div, src;
> > >>>
> > >>> - int i, ret;
> > >>> + int i, ret, clk_count;
> > >>> +
> > >>> + if (pctl->desc->without_bus_gate)
> > >>> + clk_count = 2;
> > >>> + else
> > >>> + clk_count = 3;
> > >>>
> > >>> /* Deal with old DTs that didn't have the oscillators */
> > >>> if (of_count_phandle_with_args(node, "clocks", "#clock-cells")
> > >>> != 3)
> > >>>
> > >>> @@ -1360,15 +1365,19 @@ int sunxi_pinctrl_init_with_variant(struct
> > >>> platform_device *pdev,> >>>
> > >>> goto gpiochip_error;
> > >>>
> > >>> }
> > >>>
> > >>> - clk = devm_clk_get(&pdev->dev, NULL);
> > >>> - if (IS_ERR(clk)) {
> > >>> - ret = PTR_ERR(clk);
> > >>> - goto gpiochip_error;
> > >>> - }
> > >>> + if (!desc->without_bus_gate) {
> > >>
> > >> Do we really need explicit support for that case?
> > >> Can't we have something that works automatically?
> > >>
> > >> if (node has clock-names property) (A)
> > >>
> > >> use clocks as enumerated and named there
> > >
> > > You still need to know if the hardware has a bus gate or not.
> > > If it's missing, and it's disabled, you end up with unusable
> > > hardware.
> >
> > Yes. So what? If you have a broken DT, it will not work. Just don't do
> > it. I don't understand why we want to defend against this case.
>
> This is not the point, but rather: if we have a way to detect easily
> that the device tree is missing a property that is missing in our
> binding, why shouldn't we do it?
>
> We're already doing it for reg and interrupts for example, why not for
> the clocks?
>
> > > Unless you are fully trusting the device tree to be correct.
> >
> > Sorry, but what else do we trust?
> >
> > > IMHO that makes for hard to find bugs during SoC bringup.
> >
> > I am not sure if that is really an issue. I would expect people
> > doing SoC bringup to be able to cope with those kinds of problems.
>
> Riiiight, because it worked so well in the past. We definitely didn't
> overlooked some clocks used for debouncing in this particular driver,
> or some to get the timekeeping right in the RTC.
>
> The argument that "anyone who codes in the kernel should just know
> better" doesn't work, on multiple levels. Because anyone that actually
> knows better can make a mistake or overlook some feature (because you
> didn't have your morning coffee yet, or because it was undocumented)
> and because you just make someone that doesn't feel bad.
I agree it here -- when I'm doing initial trial on H6 I didn't found that apb
gate is missing ;-)
>
> So, yes, we cannot not trust the device tree. But if we have a way to
> detect simple mistakes in the binding, we should also do it.
>
> Maxime
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox