* Re: [PATCH 2/6] dt-bindings: net: sun8i-a83t-emac: Add phy-io-supply property
From: Ondřej Jirman @ 2019-08-20 22:36 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Alexandre Torgue, netdev,
linux-kernel@vger.kernel.org, Maxime Ripard, linux-stm32,
Chen-Yu Tsai, Jose Abreu, Maxime Coquelin, Giuseppe Cavallaro,
David S. Miller,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_JsqJHNL91KMAP5ya97eiyTypGniCJ+tbP=NchPJK502i5FQ@mail.gmail.com>
On Tue, Aug 20, 2019 at 11:57:06AM -0500, Rob Herring wrote:
> On Tue, Aug 20, 2019 at 11:34 AM Ondřej Jirman <megous@megous.com> wrote:
> >
> > On Tue, Aug 20, 2019 at 11:20:22AM -0500, Rob Herring wrote:
> > > On Tue, Aug 20, 2019 at 9:53 AM <megous@megous.com> wrote:
> > > >
> > > > From: Ondrej Jirman <megous@megous.com>
> > > >
> > > > Some PHYs require separate power supply for I/O pins in some modes
> > > > of operation. Add phy-io-supply property, to allow enabling this
> > > > power supply.
> > >
> > > Perhaps since this is new, such phys should have *-supply in their nodes.
> >
> > Yes, I just don't understand, since external ethernet phys are so common,
> > and they require power, how there's no fairly generic mechanism for this
> > already in the PHY subsystem, or somewhere?
>
> Because generic mechanisms for this don't work. For example, what
> happens when the 2 supplies need to be turned on in a certain order
> and with certain timings? And then add in reset or control lines into
> the mix... You can see in the bindings we already have some of that.
I've looked at the emac bindings that have phy-supply, and don't see reason
why this can't be generic for the phy. Just like there's generic reset
properties for phys, now. Some bindings, like fsl-fec.txt even list
custom reset properties for phy as deprecated, and recommend using
generic ones.
From the point of the view of the emac driver, it just wants to power on/power
off the phy, and wait until it's ready to be communicated with.
It's probably better to have power supplies of the phy covered by generic
phy code, because then you don't have to duplicate all this special power
up logic in every emac driver, whenever a HW designer decides to combine
such emac with external phy that requires some special hadnling on powerup.
At the moment, this lack of flexibility is hacked around by adding multiple
regulators to the DTS, and making them dependent on each other (even if one
doesn't supply the other), just because this makes the regulator core driver
enable them all. Power up delays for the PHY are described as enable-ramp-delays
on the regulators (actual regulator ramp delay + wait time for PHY to initialize).
Basically just hacking the DT so that the Linux kernel in the end does what's
necessary, instead of DT describing the actual HW.
Adding a single supply property to the phy node, as you suggest will do nothing
to help this situation. It will just result in a more complicated dwmac-sun8i
driver and will not help anyone in the future.
So I think, maybe phy powerup should be moved to generic code, just like the
phy reset code was. Generic code can have multiple supplies and some generic
way to specify power up order and timings.
But I guess, this patch series is a dead end.
> > It looks like other ethernet mac drivers also implement supplies on phys
> > on the EMAC nodes. Just grep phy-supply through dt-bindings/net.
> >
> > Historical reasons, or am I missing something? It almost seems like I must
> > be missing something, since putting these properties to phy nodes
> > seems so obvious.
>
> Things get added one by one and one new property isn't that
> controversial. We've generally learned the lesson and avoid this
> pattern now, but ethernet phys are one of the older bindings.
Understood. So maybe the solution suggested above would improve the situation
eventually?
regards,
o.
> Rob
>
> _______________________________________________
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> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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* [GIT PULL] arm64: dts: Amlogic updates for v5.4
From: Kevin Hilman @ 2019-08-20 22:13 UTC (permalink / raw)
To: soc, arm; +Cc: linux-amlogic, linux-arm-kernel
Arnd, Olof,
Below is a regular round of DT updates for the 64-bit Amlogic SoCs.
Of note is a set of clock patches I've merged in from a stable tag
(already merged into clk-next.) This was needed for some new IDs added
for the handful of new SoCs we've added this cycle.
Please pull.
Thanks,
Kevin
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt64
for you to fetch changes up to e9a12e14322d7ddafeed6aec0d3fb02c0b5dc03c:
arm64: dts: add support for SM1 based SEI Robotics SEI610 (2019-08-20 13:31:11 -0700)
----------------------------------------------------------------
arm64: dts: Amlogic updates for v5.4
Highlights
- new SoCs (G12B family): S922X, A311D
- new SoCs (SM1 family): S905X3
- new board: SEI Robotics SEI610 (SM1/S905X3)
- new board: Khadas VIM3 (G12B/A311D)
- DVFS/CPUfreq support on G12[AB] family
----------------------------------------------------------------
Alexandre Mergnat (13):
clk: meson: g12a: fix hifi typo in mali parent_names
clk: meson: axg-audio: migrate to the new parent description method
clk: meson: g12a-aoclk: migrate to the new parent description method
clk: meson: gxbb-aoclk: migrate to the new parent description method
clk: meson: axg-aoclk: migrate to the new parent description method
clk: meson: remove ao input bypass clocks
clk: meson: g12a: migrate to the new parent description method
clk: meson: gxbb: migrate to the new parent description method
clk: meson: axg: migrate to the new parent description method
clk: meson: meson8b: migrate to the new parent description method
clk: meson: clk-regmap: migrate to new parent description method
clk: meson: remove ee input bypass clocks
clk: meson: remove clk input helper
Christian Hewitt (4):
dt-bindings: arm: amlogic: add support for the Khadas VIM3
arm64: dts: meson-g12b: support a311d and s922x cpu operating points
dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
Jerome Brunet (2):
Merge branch 'v5.4/dt' into v5.4/drivers
arm64: dts: meson: add ethernet fifo sizes
Kevin Hilman (2):
arm64: dts: amlogic: g12 CPU timers stop in suspend
Merge tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson into v5.4/dt64
Maxime Jourdan (3):
dt-bindings: media: amlogic,vdec: add default compatible
arm64: dts: meson-gx: add video decoder entry
arm64: dts: meson: add video decoder entries
Neil Armstrong (17):
arm64: dts: meson-g12a: add missing dwc2 phy-names
arm64: dts: meson-g12a-sei510: enable IR controller
clk: core: introduce clk_hw_set_parent()
clk: meson: add g12a cpu dynamic divider driver
clk: meson: g12a: add notifiers to handle cpu clock change
clk: meson: g12a: expose CPUB clock ID for G12B
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux
arm64: dts: meson-g12a: add cpus OPP table
arm64: dts: meson-g12a: enable DVFS on G12A boards
arm64: dts: meson-g12b: add cpus OPP tables
dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC
arm64: dts: meson-g12b-odroid-n2: enable DVFS
dt-bindings: arm: amlogic: add SM1 bindings
dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings
arm64: dts: add support for SM1 based SEI Robotics SEI610
Xavier Ruppen (1):
arm64: dts: amlogic: odroid-n2: keep SD card regulator always on
Documentation/devicetree/bindings/arm/amlogic.yaml | 20 +-
Documentation/devicetree/bindings/media/amlogic,vdec.txt | 5 +-
arch/arm64/boot/dts/amlogic/Makefile | 3 +
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2420 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 61 +++
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 54 +++
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 52 ++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 2417 ++-------------------------------------------------------------------------------------------
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts | 15 +
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi | 149 ++++++
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 544 +++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 99 +++-
arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts | 15 +
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi | 124 +++++
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 30 +-
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 16 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 11 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 11 +
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 4 +
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 300 ++++++++++++
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 68 +++
drivers/clk/clk.c | 6 +
drivers/clk/meson/Kconfig | 11 +-
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/axg-aoclk.c | 63 ++-
drivers/clk/meson/axg-audio.c | 261 +++++------
drivers/clk/meson/axg.c | 207 +++++---
drivers/clk/meson/clk-cpu-dyndiv.c | 73 +++
drivers/clk/meson/clk-cpu-dyndiv.h | 20 +
drivers/clk/meson/clk-input.c | 49 --
drivers/clk/meson/clk-input.h | 19 -
drivers/clk/meson/clk-regmap.h | 12 +-
drivers/clk/meson/g12a-aoclk.c | 81 ++--
drivers/clk/meson/g12a.c | 1626 +++++++++++++++++++++++++++++++++++++++++++++------------------
drivers/clk/meson/g12a.h | 1 -
drivers/clk/meson/gxbb-aoclk.c | 55 ++-
drivers/clk/meson/gxbb.c | 657 ++++++++++++++++++--------
drivers/clk/meson/meson-aoclk.c | 37 --
drivers/clk/meson/meson-aoclk.h | 8 -
drivers/clk/meson/meson-eeclk.c | 10 -
drivers/clk/meson/meson-eeclk.h | 2 -
drivers/clk/meson/meson8b.c | 710 +++++++++++++++++++---------
include/dt-bindings/clock/g12a-clkc.h | 1 +
include/linux/clk-provider.h | 1 +
45 files changed, 6660 insertions(+), 3672 deletions(-)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.c
create mode 100644 drivers/clk/meson/clk-cpu-dyndiv.h
delete mode 100644 drivers/clk/meson/clk-input.c
delete mode 100644 drivers/clk/meson/clk-input.h
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* [GIT PULL] ARM: dts: Amlogic updates for v5.4
From: Kevin Hilman @ 2019-08-20 22:10 UTC (permalink / raw)
To: soc, arm; +Cc: Martin Blumenstingl, linux-amlogic, linux-arm-kernel
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt
for you to fetch changes up to 6b14dd7267126931e9a95c68a442e8f2dabdc3c4:
ARM: dts: meson8b: odroidc1: use the MAC address stored in the eFuse (2019-08-12 13:45:38 -0700)
----------------------------------------------------------------
ARM: dts: Amlogic updates for v5.4
Highlights
- odroid-c1: use MAC address from efuse
- add VDD_EE regulator to several boards
----------------------------------------------------------------
Jerome Brunet (1):
ARM: dts: meson8b: add ethernet fifo sizes
Martin Blumenstingl (5):
ARM: dts: meson8b: add the PWM_D output pin
ARM: dts: meson8b: ec100: add the VDDEE regulator
ARM: dts: meson8b: odroidc1: add the VDDEE regulator
ARM: dts: meson8b: mxq: add the VDDEE regulator
ARM: dts: meson8b: odroidc1: use the MAC address stored in the eFuse
arch/arm/boot/dts/meson8b-ec100.dts | 31 ++++++++++++++++++++++++++++---
arch/arm/boot/dts/meson8b-mxq.dts | 26 +++++++++++++++++++++++---
arch/arm/boot/dts/meson8b-odroidc1.dts | 36 +++++++++++++++++++++++++++++++++---
arch/arm/boot/dts/meson8b.dtsi | 10 ++++++++++
4 files changed, 94 insertions(+), 9 deletions(-)
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* [GIT PULL] soc: amlogic: driver updates for v5.4
From: Kevin Hilman @ 2019-08-20 22:09 UTC (permalink / raw)
To: soc, arm; +Cc: linux-amlogic, linux-arm-kernel
The following changes since commit 5f9e832c137075045d15cd6899ab0505cfb2ca4b:
Linus 5.3-rc1 (2019-07-21 14:05:38 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-drivers
for you to fetch changes up to 49ed86f503be80aac158a567c4cfd31cf1cd181e:
soc: amlogic: meson-gx-socinfo: Add of_node_put() before return (2019-08-20 14:53:33 -0700)
----------------------------------------------------------------
soc: amlogic: driver updates for v5.4
Highlights
- clk-measure: support new S905X3 and A311D SoCs
- socinfo: support new S905X3 and A311D SoCs
----------------------------------------------------------------
Christian Hewitt (1):
soc: amlogic: meson-gx-socinfo: add A311D id
Neil Armstrong (5):
soc: amlogic: meson-clk-measure: protect measure with a mutex
soc: amlogic: meson-clk-measure: add G12B second cluster cpu clk
soc: amlogic: meson-gx-socinfo: Add SM1 and S905X3 IDs
dt-bindings: soc: amlogic: clk-measure: Add SM1 compatible
soc: amlogic: clk-measure: Add support for SM1
Nishka Dasgupta (1):
soc: amlogic: meson-gx-socinfo: Add of_node_put() before return
Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 1 +
drivers/soc/amlogic/meson-clk-measure.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
drivers/soc/amlogic/meson-gx-socinfo.c | 7 ++++-
3 files changed, 154 insertions(+), 2 deletions(-)
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* Re: [PATCH v5 3/3] coresight: etm4x: save/restore state for external agents
From: Mathieu Poirier @ 2019-08-20 22:01 UTC (permalink / raw)
To: Andrew Murray
Cc: Al.Grant, Suzuki K Poulose, Alexander Shishkin, coresight,
Sudeep Holla, Leo Yan, linux-arm-kernel, Mike Leach
In-Reply-To: <20190816154615.39854-4-andrew.murray@arm.com>
On Fri, Aug 16, 2019 at 04:46:15PM +0100, Andrew Murray wrote:
> Some hardware will ignore bit TRCPDCR.PU which is used to signal
> to hardware that power should not be removed from the trace unit. Much like
> self-hosted debug, we should also save/restore the trace unit state when
> it is in use by external agents.
>
> We wish to avoid saving the hardware state when coresight isn't in use
> to reduce PM latency - However as external trace/debug is designed to be
> unintrusive to the CPU, the only way of determining that an external agent is
> present is to read the claim tags (TRCCLAIMCLR). Unfortunately this register
> needs power and clocking - something it won't have when coresight isn't in use.
> We also don't want to temporarily enable it due to the latency and PM context.
>
> Let's compromise by adding a module parameter that will keep the trace unit
> powered and clocked, thus allowing us to only save/restore state when external
> trace (or self-hosted) is in use. Though please note that this doesn't allow
> for tracing from boot on hardware that needs save/restore as the CPU may idle
> prior to the ETMv4 driver starting and adding PM hooks to save/restore.
>
> Signed-off-by: Andrew Murray <andrew.murray@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++++++---
> drivers/hwtracing/coresight/coresight.c | 2 +-
> include/linux/coresight.h | 7 +++++
> 3 files changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 35a524eec36d..c5d527f7cbd5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -42,11 +42,12 @@ MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
> #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
> #define PARAM_PM_SAVE_NEVER 1 /* never save any state */
> #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
> +#define PARAM_PM_SAVE_EXTERNAL 3 /* save all state (keeps power on) */
>
> static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
> module_param(pm_save_enable, int, 0444);
> MODULE_PARM_DESC(pm_save_enable,
> - "Save/restore state on power down: 1 = never, 2 = self-hosted");
> + "Save/restore state on power down: 1 = never, 2 = self-hosted, 3 = self-hosted/external");
>
> /* The number of ETMv4 currently registered */
> static int etm4_count;
> @@ -1331,6 +1332,22 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> CS_LOCK(drvdata->base);
> }
>
> +static bool etm4_coresight_in_use(struct etmv4_drvdata *drvdata)
> +{
> + /* Self-hosted session in progress? */
> + if (local_read(&drvdata->mode))
> + return true;
> +
> + /* External agents can be detected through claim tags however we
> + * only read these tags if the trace unit is powered.
> + */
Multi-line comment format error
> + if (drvdata->csdev && pm_runtime_active(drvdata->csdev->dev.parent))
> + if (coresight_is_claimed_any(drvdata->base))
> + return true;
> +
> + return false;
> +}
> +
> static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
> void *v)
> {
> @@ -1350,8 +1367,8 @@ static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
>
> switch (cmd) {
> case CPU_PM_ENTER:
> - /* save the state if self-hosted coresight is in use */
> - if (local_read(&drvdata->mode))
> + /* Save the state if coresight is in use */
> + if (etm4_coresight_in_use(drvdata))
> if (etm4_cpu_save(drvdata))
> return NOTIFY_BAD;
> break;
> @@ -1488,7 +1505,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
> goto err_arch_supported;
> }
>
> - pm_runtime_put(&adev->dev);
> + if (pm_save_enable != PARAM_PM_SAVE_EXTERNAL)
> + pm_runtime_put(&adev->dev);
> +
> dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
> drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
>
> diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
> index e6ca899fea4e..474b7372864e 100644
> --- a/drivers/hwtracing/coresight/coresight.c
> +++ b/drivers/hwtracing/coresight/coresight.c
> @@ -140,7 +140,7 @@ static inline bool coresight_is_claimed_self_hosted(void __iomem *base)
> return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED;
> }
>
> -static inline bool coresight_is_claimed_any(void __iomem *base)
> +bool coresight_is_claimed_any(void __iomem *base)
> {
> return coresight_read_claim_tags(base) != 0;
> }
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 44e552de419c..65bfd2cb0283 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -286,6 +286,8 @@ extern void coresight_disclaim_device_unlocked(void __iomem *base);
> extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
> struct device *dev);
>
> +extern bool coresight_is_claimed_any(void __iomem *base);
> +
> extern bool coresight_loses_context_with_cpu(struct device *dev);
> #else
> static inline struct coresight_device *
> @@ -309,6 +311,11 @@ static inline int coresight_claim_device(void __iomem *base)
> static inline void coresight_disclaim_device(void __iomem *base) {}
> static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
>
> +static inline bool coresight_is_claimed_any(void __iomem *base)
> +{
> + return false;
> +}
> +
> static inline bool coresight_loses_context_with_cpu(struct device *dev)
> {
> return false;
> --
> 2.21.0
>
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* Re: [PATCH v5 2/3] dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu
From: Mathieu Poirier @ 2019-08-20 21:59 UTC (permalink / raw)
To: Andrew Murray
Cc: Al.Grant, Suzuki K Poulose, Alexander Shishkin, coresight,
Sudeep Holla, Leo Yan, linux-arm-kernel, Mike Leach
In-Reply-To: <20190816154615.39854-3-andrew.murray@arm.com>
On Fri, Aug 16, 2019 at 04:46:14PM +0100, Andrew Murray wrote:
> Some coresight components, because of choices made during hardware
> integration, require their state to be saved and restored across CPU low
> power states.
>
> The software has no reliable method of detecting when save/restore is
> required thus let's add a binding to inform the kernel.
>
> Signed-off-by: Andrew Murray <andrew.murray@arm.com>
> ---
> Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index fcc3bacfd8bc..d02c42d21f2f 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -87,6 +87,15 @@ its hardware characteristcs.
>
> * port or ports: see "Graph bindings for Coresight" below.
>
> +* Optional properties for all components:
> +
> + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
> + hardware will lose register context on CPU power down (e.g. CPUIdle).
> + An example of where this may be needed are systems which contain a
> + coresight component and CPU in the same power domain. When the CPU
> + powers down the coresight component also powers down and loses its
> + context. This property is currently only used for the ETM 4.x driver.
> +
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
When you resend this set make sure to include the device tree mailing list as
instructed by get_maintainer.pl. Since this set did not CC the DT list, none of
the maintainers over there will look at your patches.
> * Optional properties for ETM/PTMs:
>
> * arm,cp14: must be present if the system accesses ETM/PTM management
> --
> 2.21.0
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v5 1/3] coresight: etm4x: save/restore state across CPU low power states
From: Mathieu Poirier @ 2019-08-20 21:55 UTC (permalink / raw)
To: Andrew Murray
Cc: Al.Grant, Suzuki K Poulose, Alexander Shishkin, coresight,
Sudeep Holla, Leo Yan, linux-arm-kernel, Mike Leach
In-Reply-To: <20190816154615.39854-2-andrew.murray@arm.com>
Hi Andrew,
On Fri, Aug 16, 2019 at 04:46:13PM +0100, Andrew Murray wrote:
> Some hardware will ignore bit TRCPDCR.PU which is used to signal
> to hardware that power should not be removed from the trace unit.
> Let's mitigate against this by conditionally saving and restoring
> the trace unit state when the CPU enters low power states.
>
> This patchset introduces a firmware property named
> 'arm,coresight-loses-context-with-cpu' - when this is present the
> hardware state will be conditionally saved and restored.
>
> A module parameter 'pm_save_enable' is also introduced which can
> be configured to override the firmware property. This can be set
> to never allow save/restore or to conditionally allow it (only for
> self-hosted). The default value is determined by firmware.
>
> We avoid saving the hardware state when self-hosted coresight isn't
> in use to reduce PM latency - we can't determine this by reading the
> claim tags (TRCCLAIMCLR) as these are 'trace' registers which need
> power and clocking, something we can't easily provide in the PM
> context. Therefore we rely on the existing drvdata->mode internal
> state that is set when self-hosted coresight is used (and powered).
>
> Signed-off-by: Andrew Murray <andrew.murray@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 318 ++++++++++++++++++
> drivers/hwtracing/coresight/coresight-etm4x.h | 64 ++++
> drivers/hwtracing/coresight/coresight.c | 6 +
> include/linux/coresight.h | 6 +
> 4 files changed, 394 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index a128b5063f46..35a524eec36d 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -18,6 +18,7 @@
> #include <linux/stat.h>
> #include <linux/clk.h>
> #include <linux/cpu.h>
> +#include <linux/cpu_pm.h>
> #include <linux/coresight.h>
> #include <linux/coresight-pmu.h>
> #include <linux/pm_wakeup.h>
> @@ -26,6 +27,7 @@
> #include <linux/uaccess.h>
> #include <linux/perf_event.h>
> #include <linux/pm_runtime.h>
> +#include <linux/property.h>
> #include <asm/sections.h>
> #include <asm/local.h>
> #include <asm/virt.h>
> @@ -37,6 +39,15 @@ static int boot_enable;
> module_param(boot_enable, int, 0444);
> MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
>
> +#define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
> +#define PARAM_PM_SAVE_NEVER 1 /* never save any state */
> +#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
> +
> +static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
> +module_param(pm_save_enable, int, 0444);
> +MODULE_PARM_DESC(pm_save_enable,
> + "Save/restore state on power down: 1 = never, 2 = self-hosted");
> +
> /* The number of ETMv4 currently registered */
> static int etm4_count;
> static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
> @@ -54,6 +65,14 @@ static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
> isb();
> }
>
> +static void etm4_os_lock(struct etmv4_drvdata *drvdata)
> +{
> + /* Writing 0x1 to TRCOSLAR locks the trace registers */
> + writel_relaxed(0x1, drvdata->base + TRCOSLAR);
> + drvdata->os_unlock = false;
> + isb();
> +}
> +
> static bool etm4_arch_supported(u8 arch)
> {
> /* Mask out the minor version number */
> @@ -1085,6 +1104,288 @@ static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
> drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
> }
>
> +#ifdef CONFIG_CPU_PM
> +static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> +{
> + int i, ret = 0;
> + struct etmv4_save_state *state;
> + struct device *etm_dev = &drvdata->csdev->dev;
> +
> + /*
> + * As recommended by 3.4.1 ("The procedure when powering down the PE")
> + * of ARM IHI 0064D
> + */
> + dsb(sy);
> + isb();
> +
> + CS_UNLOCK(drvdata->base);
> +
> + /* Lock the OS lock to disable trace and external debugger access */
> + etm4_os_lock(drvdata);
> +
> + /* wait for TRCSTATR.PMSTABLE to go up */
> + if (coresight_timeout(drvdata->base, TRCSTATR,
> + TRCSTATR_PMSTABLE_BIT, 1)) {
Indentation problems
> + dev_err(etm_dev,
> + "timeout while waiting for PM Stable Status\n");
> + etm4_os_unlock(drvdata);
> + ret = -EBUSY;
> + goto out;
> + }
> +
> + state = drvdata->save_state;
> +
> + state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR);
> + state->trcprocselr = readl(drvdata->base + TRCPROCSELR);
> + state->trcconfigr = readl(drvdata->base + TRCCONFIGR);
> + state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
> + state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
> + state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
> + state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
> + state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
> + state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
> + state->trcccctlr = readl(drvdata->base + TRCCCCTLR);
> + state->trcbbctlr = readl(drvdata->base + TRCBBCTLR);
> + state->trctraceidr = readl(drvdata->base + TRCTRACEIDR);
> + state->trcqctlr = readl(drvdata->base + TRCQCTLR);
> +
> + state->trcvictlr = readl(drvdata->base + TRCVICTLR);
> + state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR);
> + state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR);
> + state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR);
> + state->trcvdctlr = readl(drvdata->base + TRCVDCTLR);
> + state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
> + state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
> +
> + for (i = 0; i < drvdata->nrseqstate; i++)
> + state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
> +
> + state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
> + state->trcseqstr = readl(drvdata->base + TRCSEQSTR);
> + state->trcextinselr = readl(drvdata->base + TRCEXTINSELR);
> +
> + for (i = 0; i < drvdata->nr_cntr; i++) {
> + state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i));
> + state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i));
> + state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i));
> + }
> +
> + for (i = 0; i < drvdata->nr_resource * 2; i++)
> + state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i));
> +
> + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i));
> + state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i));
> + state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i));
> + }
> +
> + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i));
> + state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i));
> + }
> +
> + /*
> + * Data trace stream is architecturally prohibited for A profile cores
> + * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
> + * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
> + * unit") of ARM IHI 0064D.
> + */
> +
> + for (i = 0; i < drvdata->numcidc; i++)
> + state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i));
> +
> + for (i = 0; i < drvdata->numvmidc; i++)
> + state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i));
> +
> + state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
> + state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
> +
> + state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0);
> + state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1);
> +
> + state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR);
> +
> + state->trcpdcr = readl(drvdata->base + TRCPDCR);
> +
> + /* wait for TRCSTATR.IDLE to go up */
> + if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
> + dev_err(etm_dev,
> + "timeout while waiting for Idle Trace Status\n");
> + etm4_os_unlock(drvdata);
> + ret = -EBUSY;
> + goto out;
> + }
> +
> + drvdata->state_needs_restore = true;
> +
> + /*
> + * Power can be removed from the trace unit now. We do this to
> + * potentially save power on systems that respect the TRCPDCR_PU
> + * despite requesting software to save/restore state.
> + */
> + writel_relaxed((state->trcpdcr & ~TRCPDCR_PU),
> + drvdata->base + TRCPDCR);
> +
> +out:
> + CS_LOCK(drvdata->base);
> + return ret;
> +}
> +
> +static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> +{
> + int i;
> + struct etmv4_save_state *state = drvdata->save_state;
> +
> + CS_UNLOCK(drvdata->base);
> +
> + writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
> +
> + writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR);
> + writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR);
> + writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR);
> + writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
> + writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
> + writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
> + writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
> + writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
> + writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
> + writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);
> + writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR);
> + writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR);
> + writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR);
> +
> + writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR);
> + writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR);
> + writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR);
> + writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR);
> + writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR);
> + writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
> + writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
> +
> + for (i = 0; i < drvdata->nrseqstate; i++)
> + writel_relaxed(state->trcseqevr[i],
> + drvdata->base + TRCSEQEVRn(i));
> +
> + writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR);
> + writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR);
> + writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR);
> +
> + for (i = 0; i < drvdata->nr_cntr; i++) {
> + writel_relaxed(state->trccntrldvr[i],
> + drvdata->base + TRCCNTRLDVRn(i));
> + writel_relaxed(state->trccntctlr[i],
> + drvdata->base + TRCCNTCTLRn(i));
> + writel_relaxed(state->trccntvr[i],
> + drvdata->base + TRCCNTVRn(i));
> + }
> +
> + for (i = 0; i < drvdata->nr_resource * 2; i++)
> + writel_relaxed(state->trcrsctlr[i],
> + drvdata->base + TRCRSCTLRn(i));
> +
> + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + writel_relaxed(state->trcssccr[i],
> + drvdata->base + TRCSSCCRn(i));
> + writel_relaxed(state->trcsscsr[i],
> + drvdata->base + TRCSSCSRn(i));
> + writel_relaxed(state->trcsspcicr[i],
> + drvdata->base + TRCSSPCICRn(i));
> + }
> +
> + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
> + writel_relaxed(state->trcacvr[i],
> + drvdata->base + TRCACVRn(i));
> + writel_relaxed(state->trcacatr[i],
> + drvdata->base + TRCACATRn(i));
> + }
> +
> + for (i = 0; i < drvdata->numcidc; i++)
> + writel_relaxed(state->trccidcvr[i],
> + drvdata->base + TRCCIDCVRn(i));
> +
> + for (i = 0; i < drvdata->numvmidc; i++)
> + writel_relaxed(state->trcvmidcvr[i],
> + drvdata->base + TRCVMIDCVRn(i));
> +
> + writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
> + writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1);
> +
> + writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0);
> + writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1);
> +
> + writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET);
> +
> + writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR);
> +
> + drvdata->state_needs_restore = false;
> +
> + /*
> + * As recommended by section 4.3.7 ("Synchronization when using the
> + * memory-mapped interface") of ARM IHI 0064D
> + */
> + dsb(sy);
> + isb();
> +
> + /* Unlock the OS lock to re-enable trace and external debug access */
> + etm4_os_unlock(drvdata);
> + CS_LOCK(drvdata->base);
> +}
> +
> +static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
> + void *v)
> +{
> + struct etmv4_drvdata *drvdata;
> + unsigned int cpu = smp_processor_id();
> +
> + if (!etmdrvdata[cpu])
> + return 0;
> +
> + drvdata = etmdrvdata[cpu];
> +
> + if (!drvdata->save_state)
> + return NOTIFY_OK;
> +
> + if (WARN_ON_ONCE(drvdata->cpu != cpu))
> + return NOTIFY_BAD;
> +
> + switch (cmd) {
> + case CPU_PM_ENTER:
> + /* save the state if self-hosted coresight is in use */
> + if (local_read(&drvdata->mode))
> + if (etm4_cpu_save(drvdata))
> + return NOTIFY_BAD;
> + break;
> + case CPU_PM_EXIT:
Implicit fallthroughs are coming to an end. Please add a
/* fallthrough */
> + case CPU_PM_ENTER_FAILED:
> + /* trcclaimset is set when there is state to restore */
As far as I can tell the above comment doesn't apply anymore.
> + if (drvdata->state_needs_restore)
> + etm4_cpu_restore(drvdata);
> + break;
> + default:
> + return NOTIFY_DONE;
> + }
> +
> + return NOTIFY_OK;
> +}
> +
> +static struct notifier_block etm4_cpu_pm_nb = {
> + .notifier_call = etm4_cpu_pm_notify,
> +};
> +
> +static int etm4_cpu_pm_register(void)
> +{
> + return cpu_pm_register_notifier(&etm4_cpu_pm_nb);
> +}
> +
> +static void etm4_cpu_pm_unregister(void)
> +{
> + cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
> +}
> +#else
> +static int etm4_cpu_pm_register(void) { return 0; }
> +static void etm4_cpu_pm_unregister(void) { }
> +#endif
> +
> static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
> {
> int ret;
> @@ -1101,6 +1402,17 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>
> dev_set_drvdata(dev, drvdata);
>
> + if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
> + pm_save_enable = coresight_loses_context_with_cpu(dev) ?
> + PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
> +
> + if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
> + drvdata->save_state = devm_kmalloc(dev,
> + sizeof(struct etmv4_save_state), GFP_KERNEL);
> + if (!drvdata->save_state)
> + return -ENOMEM;
> + }
> +
> /* Validity for the resource is already checked by the AMBA core */
> base = devm_ioremap_resource(dev, res);
> if (IS_ERR(base))
> @@ -1135,6 +1447,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
> if (ret < 0)
> goto err_arch_supported;
> hp_online = ret;
> +
> + ret = etm4_cpu_pm_register();
> + if (ret)
> + goto err_arch_supported;
> }
>
> cpus_read_unlock();
> @@ -1185,6 +1501,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>
> err_arch_supported:
> if (--etm4_count == 0) {
> + etm4_cpu_pm_unregister();
> +
> cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
> if (hp_online)
> cpuhp_remove_state_nocalls(hp_online);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 4523f10ddd0f..546d790cb01b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -175,6 +175,7 @@
> ETM_MODE_EXCL_USER)
>
> #define TRCSTATR_IDLE_BIT 0
> +#define TRCSTATR_PMSTABLE_BIT 1
> #define ETM_DEFAULT_ADDR_COMP 0
>
> /* PowerDown Control Register bits */
> @@ -281,6 +282,65 @@ struct etmv4_config {
> u32 ext_inp;
> };
>
> +/**
> + * struct etm4_save_state - state to be preserved when ETM is without power
> + */
> +struct etmv4_save_state {
> + u32 trcprgctlr;
> + u32 trcprocselr;
> + u32 trcconfigr;
> + u32 trcauxctlr;
> + u32 trceventctl0r;
> + u32 trceventctl1r;
> + u32 trcstallctlr;
> + u32 trctsctlr;
> + u32 trcsyncpr;
> + u32 trcccctlr;
> + u32 trcbbctlr;
> + u32 trctraceidr;
> + u32 trcqctlr;
> +
> + u32 trcvictlr;
> + u32 trcviiectlr;
> + u32 trcvissctlr;
> + u32 trcvipcssctlr;
> + u32 trcvdctlr;
> + u32 trcvdsacctlr;
> + u32 trcvdarcctlr;
> +
> + u32 trcseqevr[ETM_MAX_SEQ_STATES];
> + u32 trcseqrstevr;
> + u32 trcseqstr;
> + u32 trcextinselr;
> + u32 trccntrldvr[ETMv4_MAX_CNTR];
> + u32 trccntctlr[ETMv4_MAX_CNTR];
> + u32 trccntvr[ETMv4_MAX_CNTR];
> +
> + u32 trcrsctlr[ETM_MAX_RES_SEL * 2];
> +
> + u32 trcssccr[ETM_MAX_SS_CMP];
> + u32 trcsscsr[ETM_MAX_SS_CMP];
> + u32 trcsspcicr[ETM_MAX_SS_CMP];
> +
> + u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
> + u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
> + u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
> + u32 trcvmidcvr[ETM_MAX_VMID_CMP];
> + u32 trccidcctlr0;
> + u32 trccidcctlr1;
> + u32 trcvmidcctlr0;
> + u32 trcvmidcctlr1;
> +
> + u32 trcclaimset;
> +
> + u32 cntr_val[ETMv4_MAX_CNTR];
> + u32 seq_state;
> + u32 vinst_ctrl;
> + u32 ss_status[ETM_MAX_SS_CMP];
> +
> + u32 trcpdcr;
> +};
> +
> /**
> * struct etm4_drvdata - specifics associated to an ETM component
> * @base: Memory mapped base address for this component.
> @@ -336,6 +396,8 @@ struct etmv4_config {
> * @atbtrig: If the implementation can support ATB triggers
> * @lpoverride: If the implementation can support low-power state over.
> * @config: structure holding configuration parameters.
> + * @save_state: State to be preserved across power loss
> + * @state_needs_restore: True when there is context to restore after PM exit
> */
> struct etmv4_drvdata {
> void __iomem *base;
> @@ -381,6 +443,8 @@ struct etmv4_drvdata {
> bool atbtrig;
> bool lpoverride;
> struct etmv4_config config;
> + struct etmv4_save_state *save_state;
> + bool state_needs_restore;
> };
>
> /* Address comparator access types */
> diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
> index 6453c67a4d01..e6ca899fea4e 100644
> --- a/drivers/hwtracing/coresight/coresight.c
> +++ b/drivers/hwtracing/coresight/coresight.c
> @@ -1308,6 +1308,12 @@ static inline int coresight_search_device_idx(struct coresight_dev_list *dict,
> return -ENOENT;
> }
>
> +bool coresight_loses_context_with_cpu(struct device *dev)
> +{
> + return fwnode_property_present(dev_fwnode(dev),
> + "arm,coresight-loses-context-with-cpu");
> +}
> +
> /*
> * coresight_alloc_device_name - Get an index for a given device in the
> * device index list specific to a driver. An index is allocated for a
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index a2b68823717b..44e552de419c 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -285,6 +285,8 @@ extern void coresight_disclaim_device(void __iomem *base);
> extern void coresight_disclaim_device_unlocked(void __iomem *base);
> extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
> struct device *dev);
> +
> +extern bool coresight_loses_context_with_cpu(struct device *dev);
> #else
> static inline struct coresight_device *
> coresight_register(struct coresight_desc *desc) { return NULL; }
> @@ -307,6 +309,10 @@ static inline int coresight_claim_device(void __iomem *base)
> static inline void coresight_disclaim_device(void __iomem *base) {}
> static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
>
> +static inline bool coresight_loses_context_with_cpu(struct device *dev)
> +{
> + return false;
> +}
> #endif
>
> extern int coresight_get_cpu(struct device *dev);
> --
> 2.21.0
>
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^ permalink raw reply
* Re: [PATCH] soc: amlogic: meson-gx-socinfo: Add of_node_put() before return
From: Kevin Hilman @ 2019-08-20 21:55 UTC (permalink / raw)
To: Neil Armstrong, Nishka Dasgupta, linux-arm-kernel, linux-amlogic
In-Reply-To: <c30d200e-1bee-f61a-8721-ec58a8b5f93a@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> On 19/08/2019 09:27, Nishka Dasgupta wrote:
>> The variable np in function meson_gx_socinfo_init takes the return value
>> of of_find_compatible_node, which gets a node but does not put it. If
>> this node is not put it may cause a memory leak. Hence put np after its
>> usefulness has been exhausted.
>> Issue found with Coccinelle.
>>
>> Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
>> ---
>> drivers/soc/amlogic/meson-gx-socinfo.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
>> index bca34954518e..13695a72c695 100644
>> --- a/drivers/soc/amlogic/meson-gx-socinfo.c
>> +++ b/drivers/soc/amlogic/meson-gx-socinfo.c
>> @@ -138,8 +138,10 @@ static int __init meson_gx_socinfo_init(void)
>> }
>>
>> /* check if chip-id is available */
>> - if (!of_property_read_bool(np, "amlogic,has-chip-id"))
>> + if (!of_property_read_bool(np, "amlogic,has-chip-id")) {
>> + of_node_put(np);
>> return -ENODEV;
>> + }
>>
>> /* node should be a syscon */
>> regmap = syscon_node_to_regmap(np);
>>
>
> Thanks !
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>
> Would need :
> Fixes: a9daaba2965e ("soc: Add Amlogic SoC Information driver")
Thanks.
Queued for v5.4 with Neil's tag and the Fixes tag.
Kevin
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^ permalink raw reply
* Re: [PATCH] ARM: UNWINDER_FRAME_POINTER implementation for Clang
From: Nick Desaulniers @ 2019-08-20 21:39 UTC (permalink / raw)
To: Nathan Huckleberry
Cc: Tri Vo, Russell King, LKML, clang-built-linux,
Miles Chen (陳民樺), Linux ARM
In-Reply-To: <20190820194351.107486-1-nhuck@google.com>
On Tue, Aug 20, 2019 at 12:44 PM Nathan Huckleberry <nhuck@google.com> wrote:
>
> The stackframe setup when compiled with clang is different.
> Since the stack unwinder expects the gcc stackframe setup it
> fails to print backtraces. This patch adds support for the
> clang stackframe setup.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/35
> Cc: clang-built-linux@googlegroups.com
> Suggested-by: Tri Vo <trong@google.com>
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
> Changes from RFC
> * Push extra register to satisfy 8 byte alignment requirement
> * Add clarifying comments
> * Separate code into its own file
Thanks for the patch! The added comments and moving the implementation
to its own file make it easier to review.
>
> arch/arm/Kconfig.debug | 4 +-
> arch/arm/Makefile | 5 +-
> arch/arm/lib/Makefile | 8 +-
> arch/arm/lib/backtrace-clang.S | 224 +++++++++++++++++++++++++++++++++
> 4 files changed, 237 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm/lib/backtrace-clang.S
>
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index 85710e078afb..92fca7463e21 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -56,7 +56,7 @@ choice
>
> config UNWINDER_FRAME_POINTER
> bool "Frame pointer unwinder"
> - depends on !THUMB2_KERNEL && !CC_IS_CLANG
> + depends on !THUMB2_KERNEL
> select ARCH_WANT_FRAME_POINTERS
> select FRAME_POINTER
> help
> @@ -1872,7 +1872,7 @@ config DEBUG_UNCOMPRESS
> When this option is set, the selected DEBUG_LL output method
> will be re-used for normal decompressor output on multiplatform
> kernels.
> -
> +
Probably can drop the added newline?
>
> config UNCOMPRESS_INCLUDE
> string
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index c3624ca6c0bc..729e223b83fe 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -36,7 +36,10 @@ KBUILD_CFLAGS += $(call cc-option,-mno-unaligned-access)
> endif
>
> ifeq ($(CONFIG_FRAME_POINTER),y)
> -KBUILD_CFLAGS +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
> +KBUILD_CFLAGS +=-fno-omit-frame-pointer
> + ifeq ($(CONFIG_CC_IS_GCC),y)
> + KBUILD_CFLAGS += -mapcs -mno-sched-prolog
> + endif
While I can appreciate the indentation, it's unusual to indent
additional depths of kernel Makefiles. At least the rest of this file
does not do so. Of course, the other Makefile you touch below does
two spaces. At least try to keep the file internally consistent, even
if the kernel itself is inconsistent.
> endif
>
> ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index b25c54585048..e10a769c72ec 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -5,7 +5,7 @@
> # Copyright (C) 1995-2000 Russell King
> #
>
> -lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
> +lib-y := changebit.o csumipv6.o csumpartial.o \
> csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
> delay.o delay-loop.o findbit.o memchr.o memcpy.o \
> memmove.o memset.o setbit.o \
> @@ -19,6 +19,12 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
> mmu-y := clear_user.o copy_page.o getuser.o putuser.o \
> copy_from_user.o copy_to_user.o
>
> +ifdef CONFIG_CC_IS_CLANG
> + lib-y += backtrace-clang.o
> +else
> + lib-y += backtrace.o
> +endif
The indentation should match the above (from this file). Looks like 1
tab after lib-y. See L34(CONFIG_CPU_32v3) for what I would have
expected.
> +
> # using lib_ here won't override already available weak symbols
> obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
>
> diff --git a/arch/arm/lib/backtrace-clang.S b/arch/arm/lib/backtrace-clang.S
> new file mode 100644
> index 000000000000..2b02014dbdd1
> --- /dev/null
> +++ b/arch/arm/lib/backtrace-clang.S
> @@ -0,0 +1,224 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * linux/arch/arm/lib/backtrace-clang.S
> + *
> + * Copyright (C) 2019 Nathan Huckleberry
> + *
> + */
> +#include <linux/kern_levels.h>
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> + .text
> +
> +/* fp is 0 or stack frame */
ah, I see that the reference implementation uses an assembly comment
here. Ok (sorry for the noise).
> +
> +#define frame r4
> +#define sv_fp r5
> +#define sv_pc r6
> +#define mask r7
> +#define sv_lr r8
> +
> +ENTRY(c_backtrace)
> +
> +#if !defined(CONFIG_FRAME_POINTER) || !defined(CONFIG_PRINTK)
> + ret lr
> +ENDPROC(c_backtrace)
> +#else
> +
> +
> +/*
> + * Clang does not store pc or sp in function prologues
> + * so we don't know exactly where the function
> + * starts.
> + * We can treat the current frame's lr as the saved pc and the
> + * preceding frame's lr as the lr, but we can't
preceding frame's lr as the current frame's lr, ...
> + * trace the most recent call.
> + * Inserting a false stack frame allows us to reference the
> + * function called last in the stacktrace.
> + * If the call instruction was a bl we can look at the callers
> + * branch instruction to calculate the saved pc.
> + * We can recover the pc in most cases, but in cases such as
> + * calling function pointers we cannot. In this
> + * case, default to using the lr. This will be
> + * some address in the function, but will not
> + * be the function start.
> + * Unfortunately due to the stack frame layout we can't dump
> + * r0 - r3, but these are less frequently saved.
The use of tabs vs spaces in these comments is inconsistent. Not that
I can see whitespace, but:
https://github.com/nickdesaulniers/dotfiles/blob/37359525f5a403b4ed2d3f9d1bbbee2da8ec8115/.vimrc#L35-L41
Also, I don't think you need to tab indent every line after the first.
Where did that format come from?
> + *
> + * Stack frame layout:
> + * <larger addresses>
> + * saved lr
> + * frame => saved fp
> + * optionally saved caller registers (r4 - r10)
> + * optionally saved arguments (r0 - r3)
> + * <top of stack frame>
> + * <smaller addresses>
> + *
> + * Functions start with the following code sequence:
> + * corrected pc => stmfd sp!, {..., fp, lr}
> + * add fp, sp, #x
> + * stmfd sp!, {r0 - r3} (optional)
> + *
> + *
> + *
> + *
> + *
> + *
> + * The diagram below shows an example stack setup
> + * for dump_stack.
> + *
> + * The frame for c_backtrace has pointers to the
> + * code of dump_stack. This is why the frame of
> + * c_backtrace is used to for the pc calculation
> + * of dump_stack. This is why we must move back
> + * a frame to print dump_stack.
> + *
> + * The stored locals for dump_stack are in dump_stack's
> + * frame. This means that to fully print dump_stack's frame
> + * we need the both the frame for dump_stack (for locals) and the
we need both the ...
(There's an extra `the` in the sentence).
> + * frame that was called by dump_stack (for pc).
> + *
> + * To print locals we must know where the function start is. If
> + * we read the function prologue opcodes we can determine
> + * which variables are stored in the stack frame.
> + *
> + * To find the function start of dump_stack we can look at the
> + * stored LR of show_stack. It points at the instruction
> + * directly after the bl dump_stack. We can then read the
> + * offset from the bl opcode to determine where the branch takes us.
> + * The address calculated must be the start of dump_stack.
> + *
> + * c_backtrace frame dump_stack:
> + * {[LR] } ============| ...
> + * {[FP] } =======| | bl c_backtrace
> + * | |=> ...
> + * {[R4-R10]} |
> + * {[R0-R3] } | show_stack:
> + * dump_stack frame | ...
> + * {[LR] } =============| bl dump_stack
> + * {[FP] } <=======| |=> ...
> + * {[R4-R10]}
> + * {[R0-R3] }
> + */
> +
> +stmfd sp!, {r4 - r9, fp, lr} @ Save an extra register
> + @ to ensure 8 byte alignment
> +movs frame, r0 @ if frame pointer is zero
> +beq no_frame @ we have no stack frames
> +
> +tst r1, #0x10 @ 26 or 32-bit mode?
> +moveq mask, #0xfc000003
Should we be using different masks for ARM vs THUMB as per the
reference implementation?
> +movne mask, #0 @ mask for 32-bit
> +
> +/*
> + * Switches the current frame to be the frame for dump_stack.
> + */
> + add frame, sp, #24 @ switch to false frame
> +for_each_frame: tst frame, mask @ Check for address exceptions
> + bne no_frame
> +
> +/*
> + * sv_fp is the stack frame with the locals for the current considered
> + * function.
> + * sv_pc is the saved lr frame the frame above. This is a pointer to a
> + * code address within the current considered function, but
> + * it is not the function start. This value gets updated to be
> + * the function start later if it is possible.
> + */
> +1001: ldr sv_pc, [frame, #4] @ get saved 'pc'
> +1002: ldr sv_fp, [frame, #0] @ get saved fp
The reference implementation applies the mask to sv_pc and sv_fp. I
assume we want to, too?
> +
> + teq sv_fp, #0 @ make sure next frame exists
> + beq no_frame
> +
> +/*
> + * sv_lr is the lr from the function that called the current function. This
> + * is a pointer to a code address in the current function's caller.
> + * sv_lr-4 is the instruction used to call the current function.
> + * This sv_lr can be used to calculate the function start if the function
> + * was called using a bl instruction. If the function start
> + * can be recovered sv_pc is overwritten with the function start.
> + * If the current function was called using a function pointer we cannot
> + * recover the function start and instead continue with sv_pc as
> + * an arbitrary value within the current function. If this is the case
> + * we cannot print registers for the current function, but the stacktrace
> + * is still printed properly.
> + */
> +1003: ldr sv_lr, [sv_fp, #4] @ get saved lr from next frame
> +
> + ldr r0, [sv_lr, #-4] @ get call instruction
> + ldr r3, .Ldsi+8
I wonder what `dsi` stands for, it could use a better name. Maybe put
that mask in a more descriptively named section and use that instead
of `.Ldsi+8`?
> + and r2, r3, r0 @ is this a bl call
> + teq r2, r3
> + bne finished_setup @ give up if it's not
> + and r0, #0xffffff @ get call offset 24-bit int
> + lsl r0, r0, #8 @ sign extend offset
> + asr r0, r0, #8
It's too bad this should work for older ARM versions, v6 added
dedicated instructions for this:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cihfifdd.html
> + ldr sv_pc, [sv_fp, #4] @ get lr address
> + add sv_pc, sv_pc, #-4 @ get call instruction address
> + add sv_pc, sv_pc, #8 @ take care of prefetch
> + add sv_pc, sv_pc, r0, lsl #2 @ find function start
> +
> +finished_setup:
> +
> + bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
> +
> +/*
> + * Print the function (sv_pc) and where it was called
> + * from (sv_lr).
> + */
> +1004: mov r0, sv_pc
> +
> + mov r1, sv_lr
> + mov r2, frame
> + bic r1, r1, mask @ mask PC/LR for the mode
> + bl dump_backtrace_entry
> +
> +/*
> + * Test if the function start is a stmfd instruction
> + * to determine which registers were stored in the function
> + * prologue.
> + * If we could not recover the sv_pc because we were called through
> + * a function pointer the comparison will fail and no registers
> + * will print.
> + */
> +1005: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, lr}
> + ldr r3, .Ldsi @ instruction exists,
> + teq r3, r1, lsr #11
> + ldr r0, [frame] @ locals are stored in
> + @ the preceding frame
> + subeq r0, r0, #4
> + bleq dump_backtrace_stm @ dump saved registers
Do we need to do anything to test .Ldsi+4? Otherwise looks like we
define it but don't use it?
> +
> +/*
> + * If we are out of frames or if the next frame
> + * is invalid.
> + */
> + teq sv_fp, #0 @ zero saved fp means
> + beq no_frame @ no further frames
> +
> + cmp sv_fp, frame @ next frame must be
> + mov frame, sv_fp @ above the current frame
> + bhi for_each_frame
> +
> +1006: adr r0, .Lbad
> + mov r1, frame
> + bl printk
> +no_frame: ldmfd sp!, {r4 - r9, fp, pc}
> +ENDPROC(c_backtrace)
> + .pushsection __ex_table,"a"
> + .align 3
> + .long 1001b, 1006b
> + .long 1002b, 1006b
> + .long 1003b, 1006b
> + .long 1004b, 1006b
> + .long 1005b, 1006b
> + .popsection
> +
> +.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
> + .align
> +.Ldsi: .word 0xe92d4800 >> 11 @ stmfd sp!, {... fp, lr}
> + .word 0xe92d0000 >> 11 @ stmfd sp!, {}
> + .word 0x0b000000 @ bl if these bits are set
> +
> +#endif
> --
> 2.23.0.rc1.153.gdeed80330f-goog
>
--
Thanks,
~Nick Desaulniers
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^ permalink raw reply
* Re: [PATCH v3 2/9] soc: samsung: Convert exynos-chipid driver to use the regmap API
From: Sylwester Nawrocki @ 2019-08-20 21:38 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, linux-samsung-soc@vger.kernel.org, Arnd Bergmann,
linux-pm, vireshk, Bartłomiej Żołnierkiewicz,
linux-kernel@vger.kernel.org, Jon Hunter, robh+dt, kgene,
Sylwester Nawrocki, pankaj.dubey, linux-tegra, linux-arm-kernel,
Marek Szyprowski
In-Reply-To: <CAJKOXPf597CMx=M2JmSTWe2GzBfcHFefgzSJbJ+njZGp-WfR1A@mail.gmail.com>
On 8/20/19 21:37, Krzysztof Kozlowski wrote:
>>> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
>>> @@ -51,29 +48,24 @@ static const char * __init product_id_to_soc_id(unsigned int product_id)
>>> int __init exynos_chipid_early_init(void)
>>> {
>>> struct soc_device_attribute *soc_dev_attr;
>>> - void __iomem *exynos_chipid_base;
>>> struct soc_device *soc_dev;
>>> struct device_node *root;
>>> - struct device_node *np;
>>> + struct regmap *regmap;
>>> u32 product_id;
>>> u32 revision;
>>> + int ret;
>>>
>>> - /* look up for chipid node */
>>> - np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
>>> - if (!np)
>>> - return -ENODEV;
>>> -
>>> - exynos_chipid_base = of_iomap(np, 0);
>>> - of_node_put(np);
>>> -
>>> - if (!exynos_chipid_base) {
>>> - pr_err("Failed to map SoC chipid\n");
>>> - return -ENXIO;
>>> + regmap = syscon_regmap_lookup_by_compatible("samsung,exynos4210-chipid");
>>> + if (IS_ERR(regmap)) {
>>> + pr_err("Failed to get CHIPID regmap\n");
>>> + return PTR_ERR(regmap);
>>> }
>> Following this change, I am now seeing the above error on our Tegra
>> boards where this driver is enabled. This is triggering a kernel
>> warnings test we have to fail. Hence, I don't think that you can remove
>> the compatible node test here, unless you have a better way to determine
>> if this is a samsung device.
>
> Right, this is really wrong... I missed that it is not a probe but
> early init. And this init will be called on every board... Probably it
> should be converted to a regular driver.
I'm also inclined to have it converted to a regular driver. We already
have "exynos-asv" driver matching on the chipid node (patch 3/9).
The ASV patches will not be merged soon anyway, all this needs some more
thought. Krzysztof, can we abandon the chipid patches for now? Your
pull request doesn't appear to be merged to arm-soc yet. Sorry about
that.
--
Regards,
Sylwester
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^ permalink raw reply
* [v7 2/2] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:35 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij, linux-gpio
Cc: linux-aspeed, linux-kernel, Bartosz Golaszewski, Joel Stanley,
Hongwei Zhang, linux-arm-kernel
In-Reply-To: <1564603297-1391-1-git-send-email-hongweiz@ami.com>
Hello Linus,
Thanks for your review! I just submitted v8 to the list, please help to review it again.
Since you have already merged the dt-binding document [v7 1/2], and I don't have your
update to this file, so to avoid confusion, I only include the driver code in v8.
Regards,
--Hongwei
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Wednesday, August 14, 2019 4:09 AM
> To: Hongwei Zhang
> Cc: Andrew Jeffery; open list:GPIO SUBSYSTEM; Joel Stanley; linux-aspeed; Bartosz Golaszewski;
> linux-kernel@vger.kernel.org; Linux ARM
> Subject: Re: [v7 2/2] gpio: aspeed: Add SGPIO driver
>
> Hi Hongwei,
>
> thanks for your patch!
>
> I have now merged the bindings so you only need to respin this patch.
>
> On Wed, Jul 31, 2019 at 10:02 PM Hongwei Zhang <hongweiz@ami.com> wrote:
>
> > Add SGPIO driver support for Aspeed AST2500 SoC.
> >
> > Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> I guess I need to go with this, there are some minor things I still want to be fixed:
>
> > +static void __aspeed_sgpio_set(struct gpio_chip *gc, unsigned int
> > +offset, int val)
>
> I don't like __underscore_functions because their semantic is ambiguous.
>
done, please see v8.
> Rename this something like aspeed_sgpio_commit() or whatever best fits the actual use.
>
> > +static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
> > + struct platform_device *pdev) {
> (...)
> > + rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_sgpio_irqchip,
> > + 0, handle_bad_irq, IRQ_TYPE_NONE);
> (...)
> > + gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_sgpio_irqchip,
> > + gpio->irq,
> > + aspeed_sgpio_irq_handler);
>
> We do not set up chained irqchips like this anymore, sorry.
>
> I am currently rewriting all existing chained drivers to pass an initialized irqchip when registering the
> whole gpio chip.
> See drivers/gpio/TODO.
>
> Here are examples:
> https://lore.kernel.org/linux-gpio/20190811080539.15647-1-linus.walleij@linaro.org/
> https://lore.kernel.org/linux-gpio/20190812132554.18313-1-linus.walleij@linaro.org/
>
done, please see v8.
> > + /* set all SGPIO pins as input (1). */
> > + memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
>
> Do the irqchip set-up here, before adding the gpio_chip.
>
> > + rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
> > + if (rc < 0)
> > + return rc;
> > +
> > + return aspeed_sgpio_setup_irqs(gpio, pdev);
>
> Yours,
> Linus Walleij
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^ permalink raw reply
* Re: [PATCH RFC] dt-bindings: regulator: define a mux regulator
From: Uwe Kleine-König @ 2019-08-20 21:23 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Liam Girdwood,
linux-kernel@vger.kernel.org, Mark Brown, Sascha Hauer,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_JsqLg19883syn66P6zUkLPpQ8FYpeFj2QYvSp1UsWOhVKyQ@mail.gmail.com>
Hello Rob,
On Tue, Aug 20, 2019 at 11:39:27AM -0500, Rob Herring wrote:
> On Tue, Aug 20, 2019 at 10:25 AM Uwe Kleine-König
> <u.kleine-koenig@pengutronix.de> wrote:
> >
> > A mux regulator is used to provide current on one of several outputs. It
> > might look as follows:
> >
> > ,------------.
> > --<OUT0 A0 <--
> > --<OUT1 A1 <--
> > --<OUT2 A2 <--
> > --<OUT3 |
> > --<OUT4 EN <--
> > --<OUT5 |
> > --<OUT6 IN <--
> > --<OUT7 |
> > `------------'
> >
> > Depending on which address is encoded on the three address inputs A0, A1
> > and A2 the current provided on IN is provided on one of the eight
> > outputs.
> >
> > What is new here is that the binding makes use of a #regulator-cells
> > property. This uses the approach known from other bindings (e.g. gpio)
> > to allow referencing all eight outputs with phandle arguments. This
> > requires an extention in of_get_regulator to use a new variant of
> > of_parse_phandle_with_args that has a cell_count_default parameter that
> > is used in absence of a $cell_name property. Even if we'd choose to
> > update all regulator-bindings to add #regulator-cells = <0>; we still
> > needed something to implement compatibility to the currently defined
> > bindings.
> >
> > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > ---
> > Hello,
> >
> > the obvious alternative is to add (here) eight subnodes to represent the
> > eight outputs. This is IMHO less pretty, but wouldn't need to introduce
> > #regulator-cells.
>
> I'm okay with #regulator-cells approach.
OK, then I will look into that in more detail; unless the regulator guys
don't agree with this approach of course.
> > Apart from reg = <..> and a phandle there is (I think) nothing that
> > needs to be specified in the subnodes because all properties of an
> > output (apart from the address) apply to all outputs.
> >
> > What do you think?
> >
> > Best regards
> > Uwe
> >
> > .../bindings/regulator/mux-regulator.yaml | 52 +++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/regulator/mux-regulator.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/regulator/mux-regulator.yaml b/Documentation/devicetree/bindings/regulator/mux-regulator.yaml
> > new file mode 100644
> > index 000000000000..f06dbb969090
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/regulator/mux-regulator.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> (GPL-2.0-only OR BSD-2-Clause) is preferred.
OK.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/regulator/mux-regulator.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MUX regulators
> > +
> > +properties:
> > + compatible:
> > + const: XXX,adb708
>
> ? I assume you will split this into a common and specific schemas. I
> suppose there could be differing ways to control the mux just like all
> other muxes.
Not sure if a specific schema is necessary. I wrote XXX because I was
offline while I authored the binding and so couldn't determine the right
vendor to use.
> > + enable-gpios:
> > + maxItems: 1
> > +
> > + address-gpios:
> > + description: Array of typically three GPIO pins used to select the
> > + regulator's output. The least significant address GPIO must be listed
> > + first. The others follow in order of significance.
> > + minItems: 1
> > +
> > + "#regulator-cells":
>
> How is this not required?
It should. For the RFC patch I didn't took the time to iron all the
details. My main concern was/is how the binding should look like and if
an #regulator-cells with a default would be acceptable.
Best regards and thanks for your feedback,
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [v8 1/1] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:05 UTC (permalink / raw)
To: Linus Walleij, Andrew Jeffery, linux-gpio
Cc: devicetree, linux-aspeed, linux-kernel, Bartosz Golaszewski,
Rob Herring, Joel Stanley, Hongwei Zhang, linux-arm-kernel
In-Reply-To: <1566335128-31498-1-git-send-email-hongweiz@ami.com>
Add SGPIO driver support for Aspeed AST2500 SoC.
Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/sgpio-aspeed.c | 533 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 533 insertions(+)
create mode 100644 drivers/gpio/sgpio-aspeed.c
diff --git a/drivers/gpio/sgpio-aspeed.c b/drivers/gpio/sgpio-aspeed.c
new file mode 100644
index 0000000..7e99860
--- /dev/null
+++ b/drivers/gpio/sgpio-aspeed.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 American Megatrends International LLC.
+ *
+ * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/hashtable.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+
+#define MAX_NR_SGPIO 80
+
+#define ASPEED_SGPIO_CTRL 0x54
+
+#define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
+#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
+#define ASPEED_SGPIO_ENABLE BIT(0)
+
+struct aspeed_sgpio {
+ struct gpio_chip chip;
+ struct clk *pclk;
+ spinlock_t lock;
+ void __iomem *base;
+ uint32_t dir_in[3];
+ int irq;
+};
+
+struct aspeed_sgpio_bank {
+ uint16_t val_regs;
+ uint16_t rdata_reg;
+ uint16_t irq_regs;
+ const char names[4][3];
+};
+
+/*
+ * Note: The "value" register returns the input value when the GPIO is
+ * configured as an input.
+ *
+ * The "rdata" register returns the output value when the GPIO is
+ * configured as an output.
+ */
+static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
+ {
+ .val_regs = 0x0000,
+ .rdata_reg = 0x0070,
+ .irq_regs = 0x0004,
+ .names = { "A", "B", "C", "D" },
+ },
+ {
+ .val_regs = 0x001C,
+ .rdata_reg = 0x0074,
+ .irq_regs = 0x0020,
+ .names = { "E", "F", "G", "H" },
+ },
+ {
+ .val_regs = 0x0038,
+ .rdata_reg = 0x0078,
+ .irq_regs = 0x003C,
+ .names = { "I", "J" },
+ },
+};
+
+enum aspeed_sgpio_reg {
+ reg_val,
+ reg_rdata,
+ reg_irq_enable,
+ reg_irq_type0,
+ reg_irq_type1,
+ reg_irq_type2,
+ reg_irq_status,
+};
+
+#define GPIO_VAL_VALUE 0x00
+#define GPIO_IRQ_ENABLE 0x00
+#define GPIO_IRQ_TYPE0 0x04
+#define GPIO_IRQ_TYPE1 0x08
+#define GPIO_IRQ_TYPE2 0x0C
+#define GPIO_IRQ_STATUS 0x10
+
+static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
+ const struct aspeed_sgpio_bank *bank,
+ const enum aspeed_sgpio_reg reg)
+{
+ switch (reg) {
+ case reg_val:
+ return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
+ case reg_rdata:
+ return gpio->base + bank->rdata_reg;
+ case reg_irq_enable:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
+ case reg_irq_type0:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
+ case reg_irq_type1:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
+ case reg_irq_type2:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
+ case reg_irq_status:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+ default:
+ /* acturally if code runs to here, it's an error case */
+ BUG_ON(1);
+ }
+}
+
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_OFFSET(x) ((x) & 0x1f)
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
+
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+{
+ unsigned int bank = GPIO_BANK(offset);
+
+ WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
+ return &aspeed_sgpio_banks[bank];
+}
+
+static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ unsigned long flags;
+ enum aspeed_sgpio_reg reg;
+ bool is_input;
+ int rc = 0;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ is_input = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
+ reg = is_input ? reg_val : reg_rdata;
+ rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return rc;
+}
+
+static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr;
+ u32 reg = 0;
+
+ addr = bank_reg(gpio, bank, reg_val);
+ reg = ioread32(addr);
+
+ if (val)
+ reg |= GPIO_BIT(offset);
+ else
+ reg &= ~GPIO_BIT(offset);
+
+ iowrite32(reg, addr);
+}
+
+static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ sgpio_set_value(gc, offset, val);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+ gpio->dir_in[GPIO_BANK(offset)] |= GPIO_BIT(offset);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ gpio->dir_in[GPIO_BANK(offset)] &= ~GPIO_BIT(offset);
+ sgpio_set_value(gc, offset, val);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ int dir_status;
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+ dir_status = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return dir_status;
+
+}
+
+static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
+ struct aspeed_sgpio **gpio,
+ const struct aspeed_sgpio_bank **bank,
+ u32 *bit, int *offset)
+{
+ struct aspeed_sgpio *internal;
+
+ *offset = irqd_to_hwirq(d);
+ internal = irq_data_get_irq_chip_data(d);
+ WARN_ON(!internal);
+
+ *gpio = internal;
+ *bank = to_bank(*offset);
+ *bit = GPIO_BIT(*offset);
+}
+
+static void aspeed_sgpio_irq_ack(struct irq_data *d)
+{
+ const struct aspeed_sgpio_bank *bank;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ void __iomem *status_addr;
+ int offset;
+ u32 bit;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+
+ status_addr = bank_reg(gpio, bank, reg_irq_status);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ iowrite32(bit, status_addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
+{
+ const struct aspeed_sgpio_bank *bank;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ u32 reg, bit;
+ void __iomem *addr;
+ int offset;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+ addr = bank_reg(gpio, bank, reg_irq_enable);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(addr);
+ if (set)
+ reg |= bit;
+ else
+ reg &= ~bit;
+
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void aspeed_sgpio_irq_mask(struct irq_data *d)
+{
+ aspeed_sgpio_irq_set_mask(d, false);
+}
+
+static void aspeed_sgpio_irq_unmask(struct irq_data *d)
+{
+ aspeed_sgpio_irq_set_mask(d, true);
+}
+
+static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 type0 = 0;
+ u32 type1 = 0;
+ u32 type2 = 0;
+ u32 bit, reg;
+ const struct aspeed_sgpio_bank *bank;
+ irq_flow_handler_t handler;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ void __iomem *addr;
+ int offset;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_EDGE_BOTH:
+ type2 |= bit;
+ /* fall through */
+ case IRQ_TYPE_EDGE_RISING:
+ type0 |= bit;
+ /* fall through */
+ case IRQ_TYPE_EDGE_FALLING:
+ handler = handle_edge_irq;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ type0 |= bit;
+ /* fall through */
+ case IRQ_TYPE_LEVEL_LOW:
+ type1 |= bit;
+ handler = handle_level_irq;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ addr = bank_reg(gpio, bank, reg_irq_type0);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type0;
+ iowrite32(reg, addr);
+
+ addr = bank_reg(gpio, bank, reg_irq_type1);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type1;
+ iowrite32(reg, addr);
+
+ addr = bank_reg(gpio, bank, reg_irq_type2);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type2;
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ irq_set_handler_locked(d, handler);
+
+ return 0;
+}
+
+static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *ic = irq_desc_get_chip(desc);
+ struct aspeed_sgpio *data = gpiochip_get_data(gc);
+ unsigned int i, p, girq;
+ unsigned long reg;
+
+ chained_irq_enter(ic, desc);
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
+
+ reg = ioread32(bank_reg(data, bank, reg_irq_status));
+
+ for_each_set_bit(p, ®, 32) {
+ girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
+ generic_handle_irq(girq);
+ }
+
+ }
+
+ chained_irq_exit(ic, desc);
+}
+
+static struct irq_chip aspeed_sgpio_irqchip = {
+ .name = "aspeed-sgpio",
+ .irq_ack = aspeed_sgpio_irq_ack,
+ .irq_mask = aspeed_sgpio_irq_mask,
+ .irq_unmask = aspeed_sgpio_irq_unmask,
+ .irq_set_type = aspeed_sgpio_set_type,
+};
+
+static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
+ struct platform_device *pdev)
+{
+ int rc, i;
+ const struct aspeed_sgpio_bank *bank;
+ struct gpio_irq_chip *irq;
+
+ rc = platform_get_irq(pdev, 0);
+ if (rc < 0)
+ return rc;
+
+ gpio->irq = rc;
+
+ /* Disable IRQ and clear Interrupt status registers for all SPGIO Pins. */
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ bank = &aspeed_sgpio_banks[i];
+ /* disable irq enable bits */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
+ /* clear status bits */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
+ }
+
+ irq = &gpio->chip.irq;
+ irq->chip = &aspeed_sgpio_irqchip;
+ irq->handler = handle_bad_irq;
+ irq->default_type = IRQ_TYPE_NONE;
+ irq->parent_handler = aspeed_sgpio_irq_handler;
+ irq->parent_handler_data = gpio;
+ irq->parents = &gpio->irq;
+ irq->num_parents = 1;
+
+ /* set IRQ settings and Enable Interrupt */
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ bank = &aspeed_sgpio_banks[i];
+ /* set falling or level-low irq */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
+ /* trigger type is edge */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
+ /* dual edge trigger mode. */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2));
+ /* enable irq */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable));
+ }
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_sgpio_of_table[] = {
+ { .compatible = "aspeed,ast2400-sgpio" },
+ { .compatible = "aspeed,ast2500-sgpio" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
+
+static int __init aspeed_sgpio_probe(struct platform_device *pdev)
+{
+ struct aspeed_sgpio *gpio;
+ u32 nr_gpios, sgpio_freq, sgpio_clk_div;
+ int rc;
+ unsigned long apb_freq;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+
+ gpio->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(gpio->base))
+ return PTR_ERR(gpio->base);
+
+ rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Could not read ngpios property\n");
+ return -EINVAL;
+ } else if (nr_gpios > MAX_NR_SGPIO) {
+ dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
+ MAX_NR_SGPIO, nr_gpios);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Could not read bus-frequency property\n");
+ return -EINVAL;
+ }
+
+ gpio->pclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(gpio->pclk)) {
+ dev_err(&pdev->dev, "devm_clk_get failed\n");
+ return PTR_ERR(gpio->pclk);
+ }
+
+ apb_freq = clk_get_rate(gpio->pclk);
+
+ /*
+ * From the datasheet,
+ * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
+ * period = 2 * (GPIO254[31:16] + 1) / PCLK
+ * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
+ * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
+ * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
+ * GPIO254[31:16] = PCLK / (frequency * 2) - 1
+ */
+ if (sgpio_freq == 0)
+ return -EINVAL;
+
+ sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
+
+ if (sgpio_clk_div > (1 << 16) - 1)
+ return -EINVAL;
+
+ iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
+ FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
+ ASPEED_SGPIO_ENABLE,
+ gpio->base + ASPEED_SGPIO_CTRL);
+
+ spin_lock_init(&gpio->lock);
+
+ gpio->chip.parent = &pdev->dev;
+ gpio->chip.ngpio = nr_gpios;
+ gpio->chip.direction_input = aspeed_sgpio_dir_in;
+ gpio->chip.direction_output = aspeed_sgpio_dir_out;
+ gpio->chip.get_direction = aspeed_sgpio_get_direction;
+ gpio->chip.request = NULL;
+ gpio->chip.free = NULL;
+ gpio->chip.get = aspeed_sgpio_get;
+ gpio->chip.set = aspeed_sgpio_set;
+ gpio->chip.set_config = NULL;
+ gpio->chip.label = dev_name(&pdev->dev);
+ gpio->chip.base = -1;
+
+ /* set all SGPIO pins as input (1). */
+ memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
+
+ aspeed_sgpio_setup_irqs(gpio, pdev);
+
+ rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+static struct platform_driver aspeed_sgpio_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = aspeed_sgpio_of_table,
+ },
+};
+
+module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
+MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
+MODULE_LICENSE("GPL");
--
2.7.4
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^ permalink raw reply related
* [v8] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:05 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij, linux-gpio
Cc: Mark Rutland, devicetree, linux-aspeed, linux-kernel,
Bartosz Golaszewski, Rob Herring, Joel Stanley, Hongwei Zhang,
linux-arm-kernel
Hello,
This short series introduce dt-binding document and a driver for the
Aspeed AST2500 SGPIO controller. Please review.
[v8]: Changes between v7 and v8:
- v7 updates based on Linus' feedback
- since Linus has already merged sgpio-aspeed.txt, I only include
the driver here to avoid confusion.
[v7]: Changes between v6 and v7:
- fix missing variable 'reg' assign issue in aspeed_sgpio_set()
- v6 feedback updates
[v6]: Changes between v5 and v6:
- fix a bug in aspeed_sgpio_dir_out()
- v5 feedback updates, some comments cleanup
The related SGPM pinmux dt-binding document, dts, and pinctrl driver
updates have been accepted and merged:
_http://patchwork.ozlabs.org/patch/1110210/
Hongwei Zhang (1):
gpio: aspeed: Add SGPIO driver
drivers/gpio/sgpio-aspeed.c | 533 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 533 insertions(+)
create mode 100644 drivers/gpio/sgpio-aspeed.c
--
2.7.4
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* Re: [PATCH 0/6] Add ethernet support for Orange Pi 3
From: David Miller @ 2019-08-20 20:56 UTC (permalink / raw)
To: megous
Cc: mark.rutland, joabreu, alexandre.torgue, devicetree, netdev,
linux-kernel, mripard, wens, robh+dt, mcoquelin.stm32,
peppe.cavallaro, linux-stm32, linux-arm-kernel
In-Reply-To: <20190820145343.29108-1-megous@megous.com>
It looks like there will be some updates to this series either involving
adding -supply to the property names or adjusting some of the kernel log
messages.
Seriously, I would prefer less verbiage in the logs rather than more.
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* Re: [PATCH 10/14] arm64: dts: meson-g12a: fix reset controller compatible
From: Martin Blumenstingl @ 2019-08-20 20:42 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-11-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:32 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-g12a-u200.dt.yaml: reset-controller@1004: compatible:0: 'amlogic,meson-g12a-reset' is not one of ['amlogic,meson8b-reset', 'amlogic,meson-gxbb-reset', 'amlogic,meson-axg-reset']
> meson-g12a-sei510.dt.yaml: reset-controller@1004: compatible:0: 'amlogic,meson-g12a-reset' is not one of ['amlogic,meson8b-reset', 'amlogic,meson-gxbb-reset', 'amlogic,meson-axg-reset']
note to self: reference where the decision against a g12a reset
compatible string was made -> [0]
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[0] https://lkml.org/lkml/2019/2/7/358
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* Re: [PATCH 08/14] arm64: dts: meson-gxl: fix internal phy compatible
From: Martin Blumenstingl @ 2019-08-20 20:38 UTC (permalink / raw)
To: Neil Armstrong, jbrunet
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-9-narmstrong@baylibre.com>
adding Jerome
On Wed, Aug 14, 2019 at 4:31 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxl-s805x-libretech-ac.dt.yaml: ethernet-phy@8: compatible: ['ethernet-phy-id0181.4400', 'ethernet-phy-ieee802.3-c22'] is not valid under any of the given schemas
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index ee1ecdbcc958..43eb158bee24 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -709,7 +709,7 @@
> #size-cells = <0>;
>
> internal_phy: ethernet-phy@8 {
> - compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
> + compatible = "ethernet-phy-id0181.4400";
on G12A there was a specific reason (iirc it was because the PHY ID
can be any arbitrary value programmed into some register) why we added
it with a compatible string
Jerome, do we have the same situation on GXL/GXM as well?
if not I prefer to drop the compatible string because it's probably
from a time where the PHY dt-bindings stated "add the PHY ID
compatible string if you know it" while the actual suggestion was
"only add it if reading the ID doesn't work for some reason"
Martin
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* Re: [PATCH 14/14] arm64: dts: meson: fix boards regulators states format
From: Martin Blumenstingl @ 2019-08-20 20:35 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-15-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:34 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxbb-odroidc2.dt.yaml: gpio-regulator-tf_io: states:0: Additional items are not allowed (1800000, 1 were unexpected)
> meson-gxbb-odroidc2.dt.yaml: gpio-regulator-tf_io: states:0: [3300000, 0, 1800000, 1] is too long
> meson-gxbb-nexbox-a95x.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
> meson-gxbb-nexbox-a95x.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
> meson-gxbb-p200.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
> meson-gxbb-p200.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
> meson-gxl-s905x-hwacom-amazetv.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
> meson-gxl-s905x-hwacom-amazetv.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
> meson-gxbb-p201.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
> meson-gxbb-p201.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
> meson-g12b-odroid-n2.dt.yaml: gpio-regulator-tf_io: states:0: Additional items are not allowed (1800000, 1 were unexpected)
> meson-g12b-odroid-n2.dt.yaml: gpio-regulator-tf_io: states:0: [3300000, 0, 1800000, 1] is too long
> meson-gxl-s905x-nexbox-a95x.dt.yaml: gpio-regulator: states:0: Additional items are not allowed (3300000, 1 were unexpected)
> meson-gxl-s905x-nexbox-a95x.dt.yaml: gpio-regulator: states:0: [1800000, 0, 3300000, 1] is too long
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
note to self: NanoPi K2 and the Le Potato board .dts are already doing
it "right"
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* Re: [PATCH 6/6] arm64: dts: add support for SM1 based SEI Robotics SEI610
From: Kevin Hilman @ 2019-08-20 20:32 UTC (permalink / raw)
To: Martin Blumenstingl, Neil Armstrong
Cc: linux-amlogic, linux-kernel, linux-arm-kernel
In-Reply-To: <CAFBinCCNN_DBiriJRjw-AA-OCMFc+UgYi4oSJasJSypYFSbw9g@mail.gmail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> Hi Neil,
>
> On Tue, Aug 20, 2019 at 4:43 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Add support for the Amlogic SM1 Based SEI610 board.
>>
>> The SM1 SoC is a derivative of the G12A SoC Family with :
>> - Cortex-A55 core instead of A53
>> - more power domains, including USB & PCIe
>> - a neural network co-processor (NNA)
>> - a CSI input and image processor
>> - some changes in the audio complex, thus not yet enabled
>>
>> The SEI610 board is a derivative of the SEI510 board with :
>> - removed ADC based touch button, replaced with 3x GPIO buttons
>> - physical switch disabling on-board MICs
>> - USB-C port for USB 2.0 OTG
>> - On-board FTDI USB2SERIAL port for Linux console
>>
>> Audio, Display and USB support will be added later when support of the
>> corresponding power domains will be added, for now they are kept disabled.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> I don't have any details about this board but overall this looks sane, so:
> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> [...]
>> + /* Used by Tuner, RGB Led & IR Emitter LED array */
>> + vddao_3v3_t: regultor-vddao_3v3_t {
> that should be regulator-vddao_3v3_t - maybe Kevin can fix this up, if
> not then we can still fix it with a follow-up patch
I fixed it up while applying,
Kevin
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* Re: [PATCH 11/14] arm64: dts: meson-g12a-x96-max: fix compatible
From: Martin Blumenstingl @ 2019-08-20 20:32 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-12-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:33 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-g12a-x96-max.dt.yaml: /: compatible: ['amediatech,x96-max', 'amlogic,u200', 'amlogic,g12a'] is not valid under any of the given schemas
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[...]
> - compatible = "amediatech,x96-max", "amlogic,u200", "amlogic,g12a";
> + compatible = "amediatech,x96-max", "amlogic,g12a";
only partially related: I wonder if we should add a s905x2 compatible
string here and to the .dts filename (just like we separate the GXL
variants s905x, s905d, s905w, ...)
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* Re: [PATCH 04/14] arm64: dts: meson-gx: fix spifc compatible
From: Martin Blumenstingl @ 2019-08-20 20:29 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-5-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:31 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxl-s805x-libretech-ac.dt.yaml: spi@8c80: compatible:0: 'amlogic,meson-gx-spifc' is not one of ['amlogic,meson6-spifc', 'amlogic,meson-gxbb-spifc']
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Re: [PATCH 02/14] arm64: dts: meson-gx: drop the vpu dmc memory cell
From: Martin Blumenstingl @ 2019-08-20 20:28 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-3-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:31 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxl-s805x-libretech-ac.dt.yaml: vpu@d0100000: reg-names: Additional items are not allowed ('dmc' was unexpected)
> meson-gxl-s805x-libretech-ac.dt.yaml: vpu@d0100000: reg-names: ['vpu', 'hhi', 'dmc'] is too long
if you have to re-send it for whatever reason I would add:
"
The 'dmc' register area was replaced by the amlogic,canvas property
which was introduced in commit f1726043426c73 ("arm64: dts: meson-gx:
add dmcbus and canvas nodes.") and commit cf34287986d0b6 ("arm64: dts:
meson-gx: Add canvas provider node to the vpu")
"
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Re: [PATCH v6 3/4] dt-bindings: arm: fsl: Add Kontron i.MX6UL N6310 compatibles
From: Rob Herring @ 2019-08-20 20:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland, devicetree, Shawn Guo, Sascha Hauer,
linux-kernel@vger.kernel.org, Schrempf Frieder, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190820202142.GA15866@kozik-lap>
On Tue, Aug 20, 2019 at 3:21 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Tue, Aug 20, 2019 at 03:04:57PM -0500, Rob Herring wrote:
> > On Tue, Aug 20, 2019 at 1:36 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >
> > > On Tue, 20 Aug 2019 at 18:59, Rob Herring <robh+dt@kernel.org> wrote:
> > > >
> > > > On Tue, Aug 20, 2019 at 10:35 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > > > >
> > > > > Add the compatibles for Kontron i.MX6UL N6310 SoM and boards.
> > > > >
> > > > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> > > > >
> > > > > ---
> > > > >
> > > > > Changes since v5:
> > > > > New patch
> > > > > ---
> > > > > Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++
> > > > > 1 file changed, 3 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > index 7294ac36f4c0..d07b3c06d7cf 100644
> > > > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > > > @@ -161,6 +161,9 @@ properties:
> > > > > items:
> > > > > - enum:
> > > > > - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
> > > > > + - kontron,imx6ul-n6310-som # Kontron N6310 SOM
> > > > > + - kontron,imx6ul-n6310-s # Kontron N6310 S Board
> > > > > + - kontron,imx6ul-n6310-s-43 # Kontron N6310 S 43 Board
> > > >
> > > > This doesn't match what is in your dts files. Run 'make dtbs_check' and see.
> > >
> > > You mean the name does not match? I thought that '#' is a comment in YAML...
> >
> > No, the number of compatible strings is the problem.
>
> I see. If I understand the schema correctly, this should look like:
Looks correct, but a couple of comments.
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 7294ac36f4c0..eb263d1ccf13 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -161,6 +161,22 @@ properties:
> items:
> - enum:
> - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
> + - kontron,imx6ul-n6310-som # Kontron N6310 SOM
Is the SOM ever used alone? If not, then no point in listing this here.
> + - const: fsl,imx6ul
> +
> + - description: Kontron N6310 S Board
> + items:
> + - enum:
> + - kontron,imx6ul-n6310-s
This could be a 'const' instead. It depends if you think there will
ever be more than one entry.
> + - const: kontron,imx6ul-n6310-som
> + - const: fsl,imx6ul
> +
> + - description: Kontron N6310 S 43 Board
> + items:
> + - enum:
> + - kontron,imx6ul-n6310-s-43
> + - const: kontron,imx6ul-n6310-s
> + - const: kontron,imx6ul-n6310-som
> - const: fsl,imx6ul
>
> - description: i.MX6ULL based Boards
>
>
> It passes the dtbs_check. Is it correct?
>
> Best regards,
> Krzysztof
>
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* Re: [PATCH 07/14] arm64: dts: meson-gx: fix periphs bus node name
From: Martin Blumenstingl @ 2019-08-20 20:25 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-8-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:32 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxbb-nanopi-k2.dt.yaml: periphs@c8834000: $nodename:0: 'periphs@c8834000' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
> meson-gxl-s805x-libretech-ac.dt.yaml: periphs@c8834000: $nodename:0: 'periphs@c8834000' does not match '^(bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Re: [PATCH 12/14] arm64: dts: meson-gxbb-nanopi-k2: add missing model
From: Martin Blumenstingl @ 2019-08-20 20:25 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic
In-Reply-To: <20190814142918.11636-13-narmstrong@baylibre.com>
On Wed, Aug 14, 2019 at 4:33 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This fixes the following DT schemas check errors:
> meson-gxbb-nanopi-k2.dt.yaml: /: 'model' is a required property
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
> index c34c1c90ccb6..1a36d2bd2d21 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
> @@ -10,6 +10,7 @@
>
> / {
> compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
> + model = "Nanopi K2";
this should be "FriendlyARM NanoPi K2" to be consistent with other
boards (for example meson-gxbb-odroidc2.dts)
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