* Re: [PATCH] ARM: dts: imx6dl: SolidRun: add phy node with 100Mb/s max-speed
From: Russell King - ARM Linux admin @ 2019-09-15 14:15 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Baruch Siach, Shawn Guo, Sascha Hauer, tinywrkb, open list,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190915140639.GC25745@shell.armlinux.org.uk>
On Sun, Sep 15, 2019 at 03:06:39PM +0100, Russell King - ARM Linux admin wrote:
> On Sun, Sep 15, 2019 at 03:56:52PM +0200, Andrew Lunn wrote:
> > > Tinywrkb confirmed to me in private communication that revert of
> > > 5502b218e001 fixes Ethernet for him on effected system.
> > >
> > > He also referred me to an old Cubox-i spec that lists 10/100 Ethernet
> > > only for i.MX6 Solo/DualLite variants of Cubox-i. It turns out that
> > > there was a plan to use a different 10/100 PHY for Solo/DualLite
> > > SOMs. This plan never materialized. All SolidRun i.MX6 SOMs use the same
> > > AR8035 PHY that supports 1Gb.
> > >
> > > Commit 5502b218e001 might be triggering a hardware issue on the affected
> > > Cubox-i. I could not reproduce the issue here with Cubox-i and a Dual
> > > SOM variant running v5.3-rc8. I have no Solo/DualLite variant handy at
> > > the moment.
> >
> > Could somebody with an affected device show us the output of ethtool
> > with and without 5502b218e001. Does one show 1G has been negotiated,
> > and the other 100Mbps? If this is true, how does it get 100Mbps
> > without that patch? We are missing a piece of the puzzle.
>
> Hang on. 5502b218e001 is in 5.2 already - it was merged as part of the
> v5.1 merge window. That means my imx6 Solo Hummingboard is already
> running it with the AR8035 PHY, and it works fine.
>
> # dmesg
> ...
> OF: fdt: Machine model: SolidRun HummingBoard Solo/DualLite
> ...
> # ethtool eth0
> Settings for eth0:
> Supported ports: [ TP MII ]
> Supported link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
> Supported pause frame use: Symmetric
> Supports auto-negotiation: Yes
> Supported FEC modes: Not reported
> Advertised link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
> Advertised pause frame use: Symmetric
> Advertised auto-negotiation: Yes
> Advertised FEC modes: Not reported
> Link partner advertised link modes: 10baseT/Half 10baseT/Full
> 100baseT/Half 100baseT/Full
> 1000baseT/Full
> Link partner advertised pause frame use: Symmetric
> Link partner advertised auto-negotiation: Yes
> Link partner advertised FEC modes: Not reported
> Speed: 1000Mb/s
> Duplex: Full
> Port: MII
> PHYAD: 0
> Transceiver: internal
> Auto-negotiation: on
> Supports Wake-on: d
> Wake-on: d
> Link detected: yes
For some further testing, by changing the advertisment on the DSA
switch (other end of this platform's link):
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
...
Speed: 100Mb/s
Duplex: Full
===============
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half
...
Speed: 100Mb/s
Duplex: Half
===============
Link partner advertised link modes: 10baseT/Half 10baseT/Full
...
Speed: 10Mb/s
Duplex: Full
===============
Link partner advertised link modes: 10baseT/Half
...
Speed: 10Mb/s
Duplex: Half
So it looks like the commit works as it should. So there's something
else going on.
Note that the FEC does *not* support 1000baseT/Half.
--
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* Re: [PATCH] ARM: dts: imx6dl: SolidRun: add phy node with 100Mb/s max-speed
From: Andrew Lunn @ 2019-09-15 14:42 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Baruch Siach, Shawn Guo, Sascha Hauer, tinywrkb, open list,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190915141552.GD25745@shell.armlinux.org.uk>
> > OF: fdt: Machine model: SolidRun HummingBoard Solo/DualLite
> > ...
> > # ethtool eth0
> > Settings for eth0:
> > Supported ports: [ TP MII ]
> > Supported link modes: 10baseT/Half 10baseT/Full
> > 100baseT/Half 100baseT/Full
> > 1000baseT/Full
> > Supported pause frame use: Symmetric
> > Supports auto-negotiation: Yes
> > Supported FEC modes: Not reported
> > Advertised link modes: 10baseT/Half 10baseT/Full
> > 100baseT/Half 100baseT/Full
> > 1000baseT/Full
> > Advertised pause frame use: Symmetric
> > Advertised auto-negotiation: Yes
> > Advertised FEC modes: Not reported
> > Link partner advertised link modes: 10baseT/Half 10baseT/Full
> > 100baseT/Half 100baseT/Full
> > 1000baseT/Full
> > Link partner advertised pause frame use: Symmetric
> > Link partner advertised auto-negotiation: Yes
> > Link partner advertised FEC modes: Not reported
> > Speed: 1000Mb/s
> > Duplex: Full
> > Port: MII
> > PHYAD: 0
> > Transceiver: internal
> > Auto-negotiation: on
> > Supports Wake-on: d
> > Wake-on: d
> > Link detected: yes
> Note that the FEC does *not* support 1000baseT/Half.
Hi Russell
fec_main.c has code to mask it out. And it is not listed in the modes
you have above. So as you say, this all looks to be working.
I'm wondering if there is an older variant of the hardware with
100Mbps magnetics, and the boot loader is setting something in the
PHY? It could be we are now stomping over that?
We need to see output like yours, but on a device which is
experiencing the problem.
Andrew
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^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6dl: SolidRun: add phy node with 100Mb/s max-speed
From: Russell King - ARM Linux admin @ 2019-09-15 14:58 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Baruch Siach, Shawn Guo, Sascha Hauer, tinywrkb, open list,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, linux-arm-kernel
In-Reply-To: <20190915144252.GA17261@lunn.ch>
On Sun, Sep 15, 2019 at 04:42:52PM +0200, Andrew Lunn wrote:
> > > OF: fdt: Machine model: SolidRun HummingBoard Solo/DualLite
> > > ...
> > > # ethtool eth0
> > > Settings for eth0:
> > > Supported ports: [ TP MII ]
> > > Supported link modes: 10baseT/Half 10baseT/Full
> > > 100baseT/Half 100baseT/Full
> > > 1000baseT/Full
> > > Supported pause frame use: Symmetric
> > > Supports auto-negotiation: Yes
> > > Supported FEC modes: Not reported
> > > Advertised link modes: 10baseT/Half 10baseT/Full
> > > 100baseT/Half 100baseT/Full
> > > 1000baseT/Full
> > > Advertised pause frame use: Symmetric
> > > Advertised auto-negotiation: Yes
> > > Advertised FEC modes: Not reported
> > > Link partner advertised link modes: 10baseT/Half 10baseT/Full
> > > 100baseT/Half 100baseT/Full
> > > 1000baseT/Full
> > > Link partner advertised pause frame use: Symmetric
> > > Link partner advertised auto-negotiation: Yes
> > > Link partner advertised FEC modes: Not reported
> > > Speed: 1000Mb/s
> > > Duplex: Full
> > > Port: MII
> > > PHYAD: 0
> > > Transceiver: internal
> > > Auto-negotiation: on
> > > Supports Wake-on: d
> > > Wake-on: d
> > > Link detected: yes
>
> > Note that the FEC does *not* support 1000baseT/Half.
>
> Hi Russell
>
> fec_main.c has code to mask it out. And it is not listed in the modes
> you have above. So as you say, this all looks to be working.
>
> I'm wondering if there is an older variant of the hardware with
> 100Mbps magnetics, and the boot loader is setting something in the
> PHY? It could be we are now stomping over that?
Not according to Rabeeh, the SolidRun CTO:
< rabeeh> all i.MX6 based machines from SolidRun are 1Gbps phys
< rabeeh> i thought that we fixed that information, documentation wise;
but seems not
Even the Carrier1 board that pre-dates Hummingboards had the AR8035
with 1G magnetics.
The schematics I have for the Cubox-i state that the RJ45 jack (which
contains the magnetics) is to be "Gigabit".
There was a 10/100M option for the microsom, which is selected by where
a resistor pack is fitted, having the effect of configuring the AR8035
differently. I seem to recall the 10/100M option in the early days was
to use a different Atheros PHY.
However, I'm not aware of 10/100M option making it into production, and
Rabeeh's comment (who was involved in the design) confirms that.
--
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* Re: [PATCH] arm: fix page faults in do_alignment
From: Russell King - ARM Linux admin @ 2019-09-15 18:34 UTC (permalink / raw)
To: Eric W. Biederman
Cc: kstewart, gustavo, gregkh, linux-kernel, Jing Xiangfeng, linux-mm,
sakari.ailus, bhelgaas, tglx, linux-arm-kernel
In-Reply-To: <20190906151759.GM13294@shell.armlinux.org.uk>
On Fri, Sep 06, 2019 at 04:17:59PM +0100, Russell King - ARM Linux admin wrote:
> On Mon, Sep 02, 2019 at 12:36:56PM -0500, Eric W. Biederman wrote:
> > Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
> >
> > > On Fri, Aug 30, 2019 at 04:02:48PM -0500, Eric W. Biederman wrote:
> > >> Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
> > >>
> > >> > On Fri, Aug 30, 2019 at 02:45:36PM -0500, Eric W. Biederman wrote:
> > >> >> Russell King - ARM Linux admin <linux@armlinux.org.uk> writes:
> > >> >>
> > >> >> > On Fri, Aug 30, 2019 at 09:31:17PM +0800, Jing Xiangfeng wrote:
> > >> >> >> The function do_alignment can handle misaligned address for user and
> > >> >> >> kernel space. If it is a userspace access, do_alignment may fail on
> > >> >> >> a low-memory situation, because page faults are disabled in
> > >> >> >> probe_kernel_address.
> > >> >> >>
> > >> >> >> Fix this by using __copy_from_user stead of probe_kernel_address.
> > >> >> >>
> > >> >> >> Fixes: b255188 ("ARM: fix scheduling while atomic warning in alignment handling code")
> > >> >> >> Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com>
> > >> >> >
> > >> >> > NAK.
> > >> >> >
> > >> >> > The "scheduling while atomic warning in alignment handling code" is
> > >> >> > caused by fixing up the page fault while trying to handle the
> > >> >> > mis-alignment fault generated from an instruction in atomic context.
> > >> >> >
> > >> >> > Your patch re-introduces that bug.
> > >> >>
> > >> >> And the patch that fixed scheduling while atomic apparently introduced a
> > >> >> regression. Admittedly a regression that took 6 years to track down but
> > >> >> still.
> > >> >
> > >> > Right, and given the number of years, we are trading one regression for
> > >> > a different regression. If we revert to the original code where we
> > >> > fix up, we will end up with people complaining about a "new" regression
> > >> > caused by reverting the previous fix. Follow this policy and we just
> > >> > end up constantly reverting the previous revert.
> > >> >
> > >> > The window is very small - the page in question will have had to have
> > >> > instructions read from it immediately prior to the handler being entered,
> > >> > and would have had to be made "old" before subsequently being unmapped.
> > >>
> > >> > Rather than excessively complicating the code and making it even more
> > >> > inefficient (as in your patch), we could instead retry executing the
> > >> > instruction when we discover that the page is unavailable, which should
> > >> > cause the page to be paged back in.
> > >>
> > >> My patch does not introduce any inefficiencies. It onlys moves the
> > >> check for user_mode up a bit. My patch did duplicate the code.
> > >>
> > >> > If the page really is unavailable, the prefetch abort should cause a
> > >> > SEGV to be raised, otherwise the re-execution should replace the page.
> > >> >
> > >> > The danger to that approach is we page it back in, and it gets paged
> > >> > back out before we're able to read the instruction indefinitely.
> > >>
> > >> I would think either a little code duplication or a function that looks
> > >> at user_mode(regs) and picks the appropriate kind of copy to do would be
> > >> the best way to go. Because what needs to happen in the two cases for
> > >> reading the instruction are almost completely different.
> > >
> > > That is what I mean. I'd prefer to avoid that with the large chunk of
> > > code. How about instead adding a local replacement for
> > > probe_kernel_address() that just sorts out the reading, rather than
> > > duplicating all the code to deal with thumb fixup.
> >
> > So something like this should be fine?
> >
> > Jing Xiangfeng can you test this please? I think this fixes your issue
> > but I don't currently have an arm development box where I could test this.
>
> Sorry, only just got around to this again. What I came up with is this:
I've heard nothing, so I've done nothing...
> 8<===
> From: Russell King <rmk+kernel@armlinux.org.uk>
> Subject: [PATCH] ARM: mm: fix alignment
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> ---
> arch/arm/mm/alignment.c | 44 ++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index 6067fa4de22b..529f54d94709 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -765,6 +765,36 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
> return NULL;
> }
>
> +static int alignment_get_arm(struct pt_regs *regs, u32 *ip, unsigned long *inst)
> +{
> + u32 instr = 0;
> + int fault;
> +
> + if (user_mode(regs))
> + fault = get_user(instr, ip);
> + else
> + fault = probe_kernel_address(ip, instr);
> +
> + *inst = __mem_to_opcode_arm(instr);
> +
> + return fault;
> +}
> +
> +static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst)
> +{
> + u16 instr = 0;
> + int fault;
> +
> + if (user_mode(regs))
> + fault = get_user(instr, ip);
> + else
> + fault = probe_kernel_address(ip, instr);
> +
> + *inst = __mem_to_opcode_thumb16(instr);
> +
> + return fault;
> +}
> +
> static int
> do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> {
> @@ -772,10 +802,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> unsigned long instr = 0, instrptr;
> int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
> unsigned int type;
> - unsigned int fault;
> u16 tinstr = 0;
> int isize = 4;
> int thumb2_32b = 0;
> + int fault;
>
> if (interrupts_enabled(regs))
> local_irq_enable();
> @@ -784,15 +814,14 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
>
> if (thumb_mode(regs)) {
> u16 *ptr = (u16 *)(instrptr & ~1);
> - fault = probe_kernel_address(ptr, tinstr);
> - tinstr = __mem_to_opcode_thumb16(tinstr);
> +
> + fault = alignment_get_thumb(regs, ptr, &tinstr);
> if (!fault) {
> if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
> IS_T32(tinstr)) {
> /* Thumb-2 32-bit */
> - u16 tinst2 = 0;
> - fault = probe_kernel_address(ptr + 1, tinst2);
> - tinst2 = __mem_to_opcode_thumb16(tinst2);
> + u16 tinst2;
> + fault = alignment_get_thumb(regs, ptr + 1, &tinst2);
> instr = __opcode_thumb32_compose(tinstr, tinst2);
> thumb2_32b = 1;
> } else {
> @@ -801,8 +830,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
> }
> }
> } else {
> - fault = probe_kernel_address((void *)instrptr, instr);
> - instr = __mem_to_opcode_arm(instr);
> + fault = alignment_get_arm(regs, (void *)instrptr, &instr);
> }
>
> if (fault) {
> --
> 2.7.4
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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> According to speedtest.net: 11.9Mbps down 500kbps up
>
> _______________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
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* [PATCH] crypto: sun4i-ss: erase key after use
From: Corentin Labbe @ 2019-09-15 18:35 UTC (permalink / raw)
To: davem, herbert, mripard, wens
Cc: linux-kernel, stable, linux-sunxi, Corentin Labbe, linux-crypto,
linux-arm-kernel
When a TFM is unregistered, the sun4i-ss driver does not clean the key used,
leaking it in memory.
This patch adds this absent key cleaning.
Fixes: 6298e948215f ("crypto: sunxi-ss - Add Allwinner Security System crypto accelerator")
Cc: <stable@vger.kernel.org> # 4.3+
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
index fa4b1b47822e..60d99370a4ec 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
@@ -503,6 +503,8 @@ int sun4i_ss_cipher_init(struct crypto_tfm *tfm)
void sun4i_ss_cipher_exit(struct crypto_tfm *tfm)
{
struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
+
+ memzero_explicit(op->key, op->keylen);
crypto_free_sync_skcipher(op->fallback_tfm);
}
--
2.21.0
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^ permalink raw reply related
* Re: [PATCH v2] net: stmmac: socfpga: re-use the `interface` parameter from platform data
From: David Miller @ 2019-09-15 18:51 UTC (permalink / raw)
To: alexandru.ardelean
Cc: alexandre.torgue, netdev, linux-kernel, joabreu, mcoquelin.stm32,
peppe.cavallaro, linux-stm32, linux-arm-kernel
In-Reply-To: <20190912132850.10585-1-alexandru.ardelean@analog.com>
From: Alexandru Ardelean <alexandru.ardelean@analog.com>
Date: Thu, 12 Sep 2019 16:28:50 +0300
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index c141fe783e87..5b6213207c43 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
...
> +static inline int socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
Please do not use the inline keyword in foo.c files, let the compiler device.
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* [PATCH] iommu/arm-smmu: Axe a useless test in 'arm_smmu_master_alloc_smes()'
From: Christophe JAILLET @ 2019-09-15 19:34 UTC (permalink / raw)
To: will, robin.murphy, joro
Cc: Christophe JAILLET, iommu, kernel-janitors, linux-kernel,
linux-arm-kernel
'ommu_group_get_for_dev()' never returns NULL, so this test can be removed.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
---
drivers/iommu/arm-smmu.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index c3ef0cc8f764..6fae8cdbe985 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1038,8 +1038,6 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
}
group = iommu_group_get_for_dev(dev);
- if (!group)
- group = ERR_PTR(-ENOMEM);
if (IS_ERR(group)) {
ret = PTR_ERR(group);
goto out_err;
--
2.20.1
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* Re: [PATCH] crypto: sun4i-ss: erase key after use
From: Eric Biggers @ 2019-09-15 20:16 UTC (permalink / raw)
To: Corentin Labbe
Cc: herbert, linux-sunxi, linux-kernel, mripard, wens, linux-crypto,
stable, davem, linux-arm-kernel
In-Reply-To: <20190915183536.3835-1-clabbe.montjoie@gmail.com>
On Sun, Sep 15, 2019 at 08:35:36PM +0200, Corentin Labbe wrote:
> When a TFM is unregistered, the sun4i-ss driver does not clean the key used,
> leaking it in memory.
> This patch adds this absent key cleaning.
>
> Fixes: 6298e948215f ("crypto: sunxi-ss - Add Allwinner Security System crypto accelerator")
> Cc: <stable@vger.kernel.org> # 4.3+
> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> ---
> drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
> index fa4b1b47822e..60d99370a4ec 100644
> --- a/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
> +++ b/drivers/crypto/sunxi-ss/sun4i-ss-cipher.c
> @@ -503,6 +503,8 @@ int sun4i_ss_cipher_init(struct crypto_tfm *tfm)
> void sun4i_ss_cipher_exit(struct crypto_tfm *tfm)
> {
> struct sun4i_tfm_ctx *op = crypto_tfm_ctx(tfm);
> +
> + memzero_explicit(op->key, op->keylen);
> crypto_free_sync_skcipher(op->fallback_tfm);
> }
>
> --
> 2.21.0
>
It's already zeroed by the kzfree() in crypto_destroy_tfm().
- Eric
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* Re: [PATCH v1] ubifs: support page statistics in vmstat
From: Richard Weinberger @ 2019-09-15 22:05 UTC (permalink / raw)
To: Stanley Chu
Cc: linger.lee, Artem Bityutskiy, Richard Weinberger, kuohong.wang,
Adrian Hunter, linux-mtd, chienwei.chang, matthias.bgg,
linux-mediatek, linux-arm-kernel
In-Reply-To: <CAFLxGvwLTTN+S=Bd0gZWKJbjvanCe_HV_dfmoZzyb1hzWkkGpQ@mail.gmail.com>
On Sun, Jul 21, 2019 at 10:15 PM Richard Weinberger
<richard.weinberger@gmail.com> wrote:
>
> On Thu, Jul 18, 2019 at 2:04 PM Stanley Chu <stanley.chu@mediatek.com> wrote:
> >
> > Currently PGPGIN and PGPGOUT statistics in vmstat is only
> > hooked in submit_bio() for block device I/O path.
> >
> > This patch adds this feature for ubifs as well.
>
> While I think updating these counter for raw flash makes sense,
> I wonder whether UBIFS is the right layer.
> Why not directly in MTD or at least UBI?
Ping?
--
Thanks,
//richard
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* Re: [RESEND PATCH] ARM: module: Drop 'rel->r_offset < 0' statement
From: Austin Kim @ 2019-09-15 22:21 UTC (permalink / raw)
To: Russell King - ARM Linux admin, allison, info, matthias.schiffer
Cc: linux-kernel, linux-arm-kernel
In-Reply-To: <20190911141552.rtpdazx3ekfgsh3v@raspberrypi>
Hello, Maintainer(Russell King)...
Would you please update the feedback for this patch?
2019년 9월 11일 (수) 오후 11:16, Austin Kim <austindh.kim@gmail.com>님이 작성:
>
> Since rel->r_offset is declared as Elf32_Addr,
> this value is always non-negative.
> typedef struct elf32_rel {
> Elf32_Addr r_offset;
> Elf32_Word r_info;
> } Elf32_Rel;
>
> typedef __u32 Elf32_Addr;
> typedef unsigned int __u32;
>
> Drop 'rel->r_offset < 0' statement which is always false.
> Also change %u to %d in pr_err() for rel->r_offset.
>
> Signed-off-by: Austin Kim <austindh.kim@gmail.com>
> ---
> arch/arm/kernel/module.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index deef17f34..f805bcbda 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -92,8 +92,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
> sym = ((Elf32_Sym *)symsec->sh_addr) + offset;
> symname = strtab + sym->st_name;
>
> - if (rel->r_offset < 0 || rel->r_offset > dstsec->sh_size - sizeof(u32)) {
> - pr_err("%s: section %u reloc %u sym '%s': out of bounds relocation, offset %d size %u\n",
> + if (rel->r_offset > dstsec->sh_size - sizeof(u32)) {
> + pr_err("%s: section %u reloc %u sym '%s': out of bounds relocation, offset %u size %u\n",
> module->name, relindex, i, symname,
> rel->r_offset, dstsec->sh_size);
> return -ENOEXEC;
> --
> 2.11.0
>
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* [arm:cex7 21/21] drivers/bus/fsl-mc/fsl-mc-uapi.c:14:10: fatal error: uapi/linux/fsl_mc.h: No such file or directory
From: kbuild test robot @ 2019-09-15 23:09 UTC (permalink / raw)
To: Russell King; +Cc: kbuild-all, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 1062 bytes --]
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git cex7
head: ea40d247d6cf45a3b72960cc3bd9b9db691f404a
commit: ea40d247d6cf45a3b72960cc3bd9b9db691f404a [21/21] fsl-mc: add uapi interface for restool
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
git checkout ea40d247d6cf45a3b72960cc3bd9b9db691f404a
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/bus/fsl-mc/fsl-mc-uapi.c:14:10: fatal error: uapi/linux/fsl_mc.h: No such file or directory
#include <uapi/linux/fsl_mc.h>
^~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +14 drivers/bus/fsl-mc/fsl-mc-uapi.c
> 14 #include <uapi/linux/fsl_mc.h>
15 #undef fsl_mc_command
16
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 68833 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
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* RE: [PATCH] imx_v6_v7_defconfig: Build USB_CONFIGFS into kernel
From: Peter Chen @ 2019-09-16 0:37 UTC (permalink / raw)
To: Leonard Crestez, Shawn Guo
Cc: Aisheng Dong, Fabio Estevam, dl-linux-imx, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <e4cc32cf4814aa0d63e72a824fb09f6b637b792c.1568290456.git.leonard.crestez@nxp.com>
>
> Some imx chips don't have chips and a limited number of USB controllers.
> For such cases NXP suggests configuring the USB controller as an ethernet gadget
> for network boot testing.
>
> Switch USB_CONFIGFS to be built into the kernel so that we can configure the
> ethernet gadget without also deploying modules.
>
Yes, it could support NFS using USB Ethernet Gadget if the board doesn't have local Ethernet.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Peter
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> arch/arm/configs/imx_v6_v7_defconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/configs/imx_v6_v7_defconfig
> b/arch/arm/configs/imx_v6_v7_defconfig
> index ade4a2dd1a18..5debac5b038e 100644
> --- a/arch/arm/configs/imx_v6_v7_defconfig
> +++ b/arch/arm/configs/imx_v6_v7_defconfig
> @@ -325,11 +325,11 @@ CONFIG_USB_TEST=m
> CONFIG_USB_EHSET_TEST_FIXTURE=m
> CONFIG_NOP_USB_XCEIV=y
> CONFIG_USB_MXS_PHY=y
> CONFIG_USB_GADGET=y
> CONFIG_USB_FSL_USB2=y
> -CONFIG_USB_CONFIGFS=m
> +CONFIG_USB_CONFIGFS=y
> CONFIG_USB_CONFIGFS_SERIAL=y
> CONFIG_USB_CONFIGFS_ACM=y
> CONFIG_USB_CONFIGFS_OBEX=y
> CONFIG_USB_CONFIGFS_NCM=y
> CONFIG_USB_CONFIGFS_ECM=y
> --
> 2.17.1
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* Re: [RFC PATCH V4 2/4] media: platform: Add Mediatek sensor interface driver KConfig
From: Yingjoe Chen @ 2019-09-16 1:18 UTC (permalink / raw)
To: Louis Kuo
Cc: devicetree, Sean.Cheng, laurent.pinchart+renesas, Rynn.Wu,
christie.yu, srv_heupstream, Jerry-ch.Chen, tfiga, keiichiw,
jungo.lin, sj.huang, yuzhao, hans.verkuil, zwisler, frederic.chen,
matthias.bgg, linux-mediatek, mchehab, linux-arm-kernel,
linux-media
In-Reply-To: <20190915065004.20257-3-louis.kuo@mediatek.com>
On Sun, 2019-09-15 at 14:50 +0800, Louis Kuo wrote:
> This patch adds KConfig for sensor interface driver. Sensor interface
> driver
> is a MIPI-CSI2 host driver, namely, a HW camera interface controller.
> It support a widely adopted, simple, high-speed protocol primarily
> intended
> for point-to-point image and video transmission between cameras and host
> devices.
>
> Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> ---
> drivers/media/platform/mtk-isp/Kconfig | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 drivers/media/platform/mtk-isp/Kconfig
Please squash this into driver patch.
> diff --git a/drivers/media/platform/mtk-isp/Kconfig b/drivers/media/platform/mtk-isp/Kconfig
> new file mode 100644
> index 000000000000..bc7fd01808b3
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/Kconfig
> @@ -0,0 +1,17 @@
> +config MTK_SENINF
> + bool "Mediatek mipi csi2 driver"
MediaTek
> + depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
> + depends on MEDIA_CAMERA_SUPPORT
> + select V4L2_FWNODE
> +
> + default n
Do not add 'default n'
Remove the extra blank line.
> + help
> + This driver provides a mipi-csi2 host driver used as a
> + interface to connect camera with Mediatek's
MediaTek
> + MT8183 SOCs. It is able to handle multiple cameras
> + at the same time.
> +
> + Choose y if you want to use Mediatek SoCs to create image
MediaTek
> + capture application such as video recording and still image
> + capture.
> +
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* Re: [RFC PATCH V4 1/4] media: platform: mtk-isp: Add Mediatek sensor interface driver
From: Yingjoe Chen @ 2019-09-16 1:28 UTC (permalink / raw)
To: Louis Kuo
Cc: devicetree, Sean.Cheng, laurent.pinchart+renesas, Rynn.Wu,
christie.yu, srv_heupstream, Jerry-ch.Chen, tfiga, keiichiw,
jungo.lin, sj.huang, yuzhao, hans.verkuil, zwisler, frederic.chen,
matthias.bgg, linux-mediatek, mchehab, linux-arm-kernel,
linux-media
In-Reply-To: <20190915065004.20257-2-louis.kuo@mediatek.com>
On Sun, 2019-09-15 at 14:50 +0800, Louis Kuo wrote:
> This patch adds Mediat:ek's sensor interface driver. Sensor interface
> driver
> is a MIPI-CSI2 host driver, namely, a HW camera interface controller.
> It support a widely adopted, simple, high-speed protocol primarily
> intended
> for point-to-point image and video transmission between cameras and host
> devices.
Please properly wrap the commit text and fix typo.
>
> The mtk-isp directory will contain drivers for multiple IP blocks found in
> Mediatek ISP system. It will include ISP Pass 1 driver, sensor interface
> driver, DIP driver and face detection driver.
>
> Signed-off-by: Louis Kuo <louis.kuo@mediatek.com>
> ---
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/mtk-isp/Makefile | 3 +
> .../media/platform/mtk-isp/isp_50/Makefile | 5 +
> .../platform/mtk-isp/isp_50/seninf/Makefile | 6 +
> .../mtk-isp/isp_50/seninf/mtk_seninf.c | 1011 +++++++++++++++++
> .../mtk-isp/isp_50/seninf/mtk_seninf_def.h | 59 +
> .../mtk-isp/isp_50/seninf/mtk_seninf_reg.h | 853 ++++++++++++++
> 7 files changed, 1939 insertions(+)
> create mode 100644 drivers/media/platform/mtk-isp/Makefile
> create mode 100644 drivers/media/platform/mtk-isp/isp_50/Makefile
> create mode 100644 drivers/media/platform/mtk-isp/isp_50/seninf/Makefile
> create mode 100644 drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf.c
> create mode 100644 drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf_def.h
> create mode 100644 drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf_reg.h
>
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index 7cbbd925124c..b0f4543f2f86 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -73,6 +73,8 @@ obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/
>
> obj-y += omap/
>
> +obj-y += mtk-isp/
> +
> obj-$(CONFIG_VIDEO_AM437X_VPFE) += am437x/
>
> obj-$(CONFIG_VIDEO_XILINX) += xilinx/
> diff --git a/drivers/media/platform/mtk-isp/Makefile b/drivers/media/platform/mtk-isp/Makefile
> new file mode 100644
> index 000000000000..c17fb3fc3340
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += isp_50/
> diff --git a/drivers/media/platform/mtk-isp/isp_50/Makefile b/drivers/media/platform/mtk-isp/isp_50/Makefile
> new file mode 100644
> index 000000000000..8b4a792328e5
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/isp_50/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +ifeq ($(CONFIG_MTK_SENINF),y)
> +obj-y += seninf/
> +endif
Please use 'obj-$(CONFIG_MTK_SENINF) += seninf/' instead.
In fact, as Sakari mention in previous review, you should just remove
the check.
You should address all comments in previous run, otherwise what's the
point for resend and the review?
> diff --git a/drivers/media/platform/mtk-isp/isp_50/seninf/Makefile b/drivers/media/platform/mtk-isp/isp_50/seninf/Makefile
> new file mode 100644
> index 000000000000..bf193feb0ce9
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/isp_50/seninf/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +MODULE = mtk_seninf
> +LIB_FILES = mtk_seninf
> +
> +obj-$(CONFIG_MTK_SENINF) += mtk_seninf.o
> diff --git a/drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf.c b/drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf.c
> new file mode 100644
> index 000000000000..3253510cf7fd
> --- /dev/null
> +++ b/drivers/media/platform/mtk-isp/isp_50/seninf/mtk_seninf.c
> @@ -0,0 +1,1011 @@
> +// SPDX-License-Identifier: GPL-2.0
<...>
> +
> +static struct platform_driver seninf_pdrv = {
> + .driver = {
> + .name = "seninf",
> + .pm = &runtime_pm_ops,
> + .of_match_table = of_match_ptr(mtk_seninf_of_match),
> + },
> + .probe = seninf_probe,
> + .remove = seninf_remove,
> +};
> +
> +module_platform_driver(seninf_pdrv);
> +
> +MODULE_DESCRIPTION("MTK seninf driver");
> +MODULE_AUTHOR("Louis Kuo <louis.kuo@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("MTK:mtk_seninf");
You don't need MODULE_* since this can't be built as module now.
However, I think this should be able to build as module.
Joe.C
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* Re: [PATCH V7 1/3] mm/hotplug: Reorder memblock_[free|remove]() calls in try_remove_memory()
From: Balbir Singh @ 2019-09-16 1:44 UTC (permalink / raw)
To: Anshuman Khandual, linux-mm, linux-kernel, linux-arm-kernel, akpm,
catalin.marinas, will
Cc: mark.rutland, mhocko, david, ira.weiny, steve.capper, mgorman,
steven.price, broonie, cai, ard.biesheuvel, cpandya, arunks,
dan.j.williams, Robin.Murphy, logang, valentin.schneider,
suzuki.poulose, osalvador
In-Reply-To: <1567503958-25831-2-git-send-email-anshuman.khandual@arm.com>
On 3/9/19 7:45 pm, Anshuman Khandual wrote:
> Memory hot remove uses get_nid_for_pfn() while tearing down linked sysfs
I could not find this path in the code, the only called for get_nid_for_pfn()
was register_mem_sect_under_node() when the system is under boot.
> entries between memory block and node. It first checks pfn validity with
> pfn_valid_within() before fetching nid. With CONFIG_HOLES_IN_ZONE config
> (arm64 has this enabled) pfn_valid_within() calls pfn_valid().
>
> pfn_valid() is an arch implementation on arm64 (CONFIG_HAVE_ARCH_PFN_VALID)
> which scans all mapped memblock regions with memblock_is_map_memory(). This
> creates a problem in memory hot remove path which has already removed given
> memory range from memory block with memblock_[remove|free] before arriving
> at unregister_mem_sect_under_nodes(). Hence get_nid_for_pfn() returns -1
> skipping subsequent sysfs_remove_link() calls leaving node <-> memory block
> sysfs entries as is. Subsequent memory add operation hits BUG_ON() because
> of existing sysfs entries.
>
> [ 62.007176] NUMA: Unknown node for memory at 0x680000000, assuming node 0
> [ 62.052517] ------------[ cut here ]------------
This seems like arm64 is not ready for probe_store() via drivers/base/memory.c/ode.c
> [ 62.053211] kernel BUG at mm/memory_hotplug.c:1143!
> [ 62.053868] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
> [ 62.054589] Modules linked in:
> [ 62.054999] CPU: 19 PID: 3275 Comm: bash Not tainted 5.1.0-rc2-00004-g28cea40b2683 #41
> [ 62.056274] Hardware name: linux,dummy-virt (DT)
> [ 62.057166] pstate: 40400005 (nZcv daif +PAN -UAO)
> [ 62.058083] pc : add_memory_resource+0x1cc/0x1d8
> [ 62.058961] lr : add_memory_resource+0x10c/0x1d8
> [ 62.059842] sp : ffff0000168b3ce0
> [ 62.060477] x29: ffff0000168b3ce0 x28: ffff8005db546c00
> [ 62.061501] x27: 0000000000000000 x26: 0000000000000000
> [ 62.062509] x25: ffff0000111ef000 x24: ffff0000111ef5d0
> [ 62.063520] x23: 0000000000000000 x22: 00000006bfffffff
> [ 62.064540] x21: 00000000ffffffef x20: 00000000006c0000
> [ 62.065558] x19: 0000000000680000 x18: 0000000000000024
> [ 62.066566] x17: 0000000000000000 x16: 0000000000000000
> [ 62.067579] x15: ffffffffffffffff x14: ffff8005e412e890
> [ 62.068588] x13: ffff8005d6b105d8 x12: 0000000000000000
> [ 62.069610] x11: ffff8005d6b10490 x10: 0000000000000040
> [ 62.070615] x9 : ffff8005e412e898 x8 : ffff8005e412e890
> [ 62.071631] x7 : ffff8005d6b105d8 x6 : ffff8005db546c00
> [ 62.072640] x5 : 0000000000000001 x4 : 0000000000000002
> [ 62.073654] x3 : ffff8005d7049480 x2 : 0000000000000002
> [ 62.074666] x1 : 0000000000000003 x0 : 00000000ffffffef
> [ 62.075685] Process bash (pid: 3275, stack limit = 0x00000000d754280f)
> [ 62.076930] Call trace:
> [ 62.077411] add_memory_resource+0x1cc/0x1d8
> [ 62.078227] __add_memory+0x70/0xa8
> [ 62.078901] probe_store+0xa4/0xc8
> [ 62.079561] dev_attr_store+0x18/0x28
> [ 62.080270] sysfs_kf_write+0x40/0x58
> [ 62.080992] kernfs_fop_write+0xcc/0x1d8
> [ 62.081744] __vfs_write+0x18/0x40
> [ 62.082400] vfs_write+0xa4/0x1b0
> [ 62.083037] ksys_write+0x5c/0xc0
> [ 62.083681] __arm64_sys_write+0x18/0x20
> [ 62.084432] el0_svc_handler+0x88/0x100
> [ 62.085177] el0_svc+0x8/0xc
>
> Re-ordering memblock_[free|remove]() with arch_remove_memory() solves the
> problem on arm64 as pfn_valid() behaves correctly and returns positive
> as memblock for the address range still exists. arch_remove_memory()
> removes applicable memory sections from zone with __remove_pages() and
> tears down kernel linear mapping. Removing memblock regions afterwards
> is safe because there is no other memblock (bootmem) allocator user that
> late. So nobody is going to allocate from the removed range just to blow
> up later. Also nobody should be using the bootmem allocated range else
> we wouldn't allow to remove it. So reordering is indeed safe.
>
> Reviewed-by: David Hildenbrand <david@redhat.com>
> Reviewed-by: Oscar Salvador <osalvador@suse.de>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
> Acked-by: Michal Hocko <mhocko@suse.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
Honestly, the issue is not clear from the changelog, largely
because I can't find the use of get_nid_for_pfn() being used
in memory hotunplug. I can see why using pfn_valid() after
memblock_free/remove is bad on the architecture.
I think the checks to pfn_valid() can be avoided from the
remove paths if we did the following
memblock_isolate_regions()
for each isolate_region {
memblock_free
memblock_remove
arch_memory_remove
# ensure that __remove_memory can avoid calling pfn_valid
}
Having said that, your patch is easier and if your assumption
about not using the memblocks is valid (after arch_memory_remove())
then might be the least resistant way forward
Balbir Singh.
> mm/memory_hotplug.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
> index c73f09913165..355c466e0621 100644
> --- a/mm/memory_hotplug.c
> +++ b/mm/memory_hotplug.c
> @@ -1770,13 +1770,13 @@ static int __ref try_remove_memory(int nid, u64 start, u64 size)
>
> /* remove memmap entry */
> firmware_map_remove(start, start + size, "System RAM");
> - memblock_free(start, size);
> - memblock_remove(start, size);
>
> /* remove memory block devices before removing memory */
> remove_memory_block_devices(start, size);
>
> arch_remove_memory(nid, start, size, NULL);
> + memblock_free(start, size);
> + memblock_remove(start, size);
> __release_memory_resource(start, size);
>
> try_offline_node(nid);
>
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* [PATCH 2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
.../bindings/pci/layerscape-pcie-gen4.txt | 28 +++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
index b40fb5d..414a86c 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
@@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller
This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
the common properties defined in mobiveil-pcie.txt.
+HOST MODE
+=========
Required properties:
- compatible: should contain the platform identifier such as:
"fsl,lx2160a-pcie"
@@ -23,7 +25,20 @@ Required properties:
- msi-parent : See the generic MSI binding described in
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-Example:
+DEVICE MODE
+=========
+Required properties:
+- compatible: should contain the platform identifier such as:
+ "fsl,lx2160a-pcie-ep"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+ "regs": PCIe controller registers.
+ "addr_space" EP device CPU address.
+- apio-wins: number of requested apio outbound windows.
+
+Optional Property:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+RC Example:
pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
@@ -50,3 +65,14 @@ Example:
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
+
+EP Example:
+
+ pcie_ep@3400000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ status = "disabled";
+ };
--
2.9.5
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^ permalink raw reply related
* [PATCH 0/6] Add the Mobiveil EP and Layerscape Gen4 EP driver support
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
This patch set are for adding Mobiveil EP driver and adding PCIe Gen4
EP driver of NXP Layerscape platform.
This patch set depends on:
https://patchwork.kernel.org/project/linux-pci/list/?series=159139
Xiaowei Bao (6):
PCI: mobiveil: Add the EP driver support
dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
PCI: mobiveil: Add workaround for unsupported request error
arm64: dts: lx2160a: Add PCIe EP node
misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device
support
.../bindings/pci/layerscape-pcie-gen4.txt | 28 +-
MAINTAINERS | 3 +
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++
drivers/misc/pci_endpoint_test.c | 2 +
drivers/pci/controller/mobiveil/Kconfig | 22 +-
drivers/pci/controller/mobiveil/Makefile | 2 +
.../controller/mobiveil/pcie-layerscape-gen4-ep.c | 169 ++++++
drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 568 +++++++++++++++++++++
drivers/pci/controller/mobiveil/pcie-mobiveil.c | 99 +++-
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 72 +++
10 files changed, 1009 insertions(+), 12 deletions(-)
create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
--
2.9.5
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^ permalink raw reply
* [PATCH 4/6] PCI: mobiveil: Add workaround for unsupported request error
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
index 7bfec51..5bc9ed7 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
@@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
int win_idx;
u8 bar;
+ u32 val;
+
+ /*
+ * Errata: unsupported request error on inbound posted write
+ * transaction, PCIe controller reports advisory error instead
+ * of uncorrectable error message to RC.
+ * workaround: set the bit20(unsupported_request_Error_severity) with
+ * value 1 in uncorrectable_Error_Severity_Register, make the
+ * unsupported request error generate the fatal error.
+ */
+ val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
+ val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
+ csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
ep->bar_num = PCIE_LX2_BAR_NUM;
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 7308fa4..a40707e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -123,6 +123,10 @@
#define GPEX_BAR_SIZE_UDW 0x4DC
#define GPEX_BAR_SELECT 0x4E0
+#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c
+#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20
+#define CFG_UNCORRECTABLE_ERROR_MASK 0x108
+
/* starting offset of INTX bits in status register */
#define PAB_INTX_START 5
--
2.9.5
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^ permalink raw reply related
* [PATCH 5/6] arm64: dts: lx2160a: Add PCIe EP node
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
Add the LX2160A PCIe EP node.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index f60e5ac..18330df 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1005,6 +1005,15 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -1032,6 +1041,15 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -1059,6 +1077,16 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <256>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1086,6 +1114,15 @@
status = "disabled";
};
+ pcie_ep@3700000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ status = "disabled";
+ };
+
pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1113,6 +1150,16 @@
status = "disabled";
};
+ pcie_ep@3800000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <256>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1140,5 +1187,14 @@
status = "disabled";
};
+ pcie_ep@3900000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ status = "disabled";
+ };
+
};
};
--
2.9.5
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^ permalink raw reply related
* [PATCH 3/6] PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
mode if select this config opteration.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
MAINTAINERS | 2 +
drivers/pci/controller/mobiveil/Kconfig | 17 ++-
drivers/pci/controller/mobiveil/Makefile | 1 +
.../controller/mobiveil/pcie-layerscape-gen4-ep.c | 156 +++++++++++++++++++++
4 files changed, 173 insertions(+), 3 deletions(-)
create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
diff --git a/MAINTAINERS b/MAINTAINERS
index b997056..0858b54 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12363,11 +12363,13 @@ F: drivers/pci/controller/dwc/*layerscape*
PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+M: Xiaowei Bao <xiaowei.bao@nxp.com>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
F: drivers/pci/controller/mobibeil/pcie-layerscape-gen4.c
+F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
PCI DRIVER FOR GENERIC OF HOSTS
M: Will Deacon <will@kernel.org>
diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig
index 2054950..0696b6e 100644
--- a/drivers/pci/controller/mobiveil/Kconfig
+++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -27,13 +27,24 @@ config PCIE_MOBIVEIL_PLAT
for address translation and it is a PCIe Gen4 IP.
config PCIE_LAYERSCAPE_GEN4
- bool "Freescale Layerscape PCIe Gen4 controller"
+ bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
depends on PCI
depends on OF && (ARM64 || ARCH_LAYERSCAPE)
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_MOBIVEIL_HOST
help
Say Y here if you want PCIe Gen4 controller support on
- Layerscape SoCs. The PCIe controller can work in RC or
- EP mode according to RCW[HOST_AGT_PEX] setting.
+ Layerscape SoCs. And the PCIe controller work in RC mode
+ by setting the RCW[HOST_AGT_PEX] to 0.
+
+config PCIE_LAYERSCAPE_GEN4_EP
+ bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
+ depends on PCI
+ depends on OF && (ARM64 || ARCH_LAYERSCAPE)
+ depends on PCI_ENDPOINT
+ select PCIE_MOBIVEIL_EP
+ help
+ Say Y here if you want PCIe Gen4 controller support on
+ Layerscape SoCs. And the PCIe controller work in EP mode
+ by setting the RCW[HOST_AGT_PEX] to 1.
endmenu
diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile
index 686d41f..6f54856 100644
--- a/drivers/pci/controller/mobiveil/Makefile
+++ b/drivers/pci/controller/mobiveil/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
+obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4_EP) += pcie-layerscape-gen4-ep.o
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
new file mode 100644
index 0000000..7bfec51
--- /dev/null
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe controller EP driver for Freescale Layerscape SoCs
+ *
+ * Copyright (C) 2019 NXP Semiconductor.
+ *
+ * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-mobiveil.h"
+
+#define PCIE_LX2_BAR_NUM 4
+
+#define to_ls_pcie_g4_ep(x) dev_get_drvdata((x)->dev)
+
+struct ls_pcie_g4_ep {
+ struct mobiveil_pcie *mv_pci;
+};
+
+static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
+ { .compatible = "fsl,lx2160a-pcie-ep",},
+ { },
+};
+
+static const struct pci_epc_features ls_pcie_g4_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = true,
+ .reserved_bar = (1 << BAR_4) | (1 << BAR_5),
+};
+
+static const struct pci_epc_features*
+ls_pcie_g4_ep_get_features(struct mobiveil_pcie_ep *ep)
+{
+ return &ls_pcie_g4_epc_features;
+}
+
+static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
+{
+ struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
+ int win_idx;
+ u8 bar;
+
+ ep->bar_num = PCIE_LX2_BAR_NUM;
+
+ for (bar = BAR_0; bar < ep->epc->max_functions * ep->bar_num; bar++)
+ mobiveil_pcie_ep_reset_bar(mv_pci, bar);
+
+ for (win_idx = 0; win_idx < ep->apio_wins; win_idx++)
+ mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
+}
+
+static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
+ case PCI_EPC_IRQ_MSI:
+ return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
+ interrupt_num);
+ case PCI_EPC_IRQ_MSIX:
+ return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
+ interrupt_num);
+ default:
+ dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
+ }
+
+ return 0;
+}
+
+static const struct mobiveil_pcie_ep_ops pcie_ep_ops = {
+ .ep_init = ls_pcie_g4_ep_init,
+ .raise_irq = ls_pcie_g4_ep_raise_irq,
+ .get_features = ls_pcie_g4_ep_get_features,
+};
+
+static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_ep,
+ struct platform_device *pdev)
+{
+ struct mobiveil_pcie *mv_pci = ls_ep->mv_pci;
+ struct device *dev = &pdev->dev;
+ struct mobiveil_pcie_ep *ep;
+ struct resource *res;
+ int ret;
+
+ ep = &mv_pci->ep;
+ ep->ops = &pcie_ep_ops;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+ if (!res)
+ return -EINVAL;
+
+ ep->phys_base = res->start;
+ ep->addr_size = resource_size(res);
+
+ ret = mobiveil_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize layerscape endpoint\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mobiveil_pcie *mv_pci;
+ struct ls_pcie_g4_ep *ls_ep;
+ struct resource *res;
+ int ret;
+
+ ls_ep = devm_kzalloc(dev, sizeof(*ls_ep), GFP_KERNEL);
+ if (!ls_ep)
+ return -ENOMEM;
+
+ mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
+ if (!mv_pci)
+ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
+ if (IS_ERR(mv_pci->csr_axi_slave_base))
+ return PTR_ERR(mv_pci->csr_axi_slave_base);
+
+ mv_pci->pdev = pdev;
+ ls_ep->mv_pci = mv_pci;
+
+ platform_set_drvdata(pdev, ls_ep);
+
+ ret = ls_pcie_gen4_add_pcie_ep(ls_ep, pdev);
+
+ return ret;
+}
+
+static struct platform_driver ls_pcie_g4_ep_driver = {
+ .driver = {
+ .name = "layerscape-pcie-gen4-ep",
+ .of_match_table = ls_pcie_g4_ep_of_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);
--
2.9.5
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^ permalink raw reply related
* [PATCH 1/6] PCI: mobiveil: Add the EP driver support
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
Add the EP driver support for Mobiveil base on endpoint framework.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
MAINTAINERS | 1 +
drivers/pci/controller/mobiveil/Kconfig | 5 +
drivers/pci/controller/mobiveil/Makefile | 1 +
drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 568 +++++++++++++++++++++
drivers/pci/controller/mobiveil/pcie-mobiveil.c | 99 +++-
drivers/pci/controller/mobiveil/pcie-mobiveil.h | 68 +++
6 files changed, 734 insertions(+), 8 deletions(-)
create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e6a4de0..b997056 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12409,6 +12409,7 @@ F: drivers/ntb/hw/mscc/
PCI DRIVER FOR MOBIVEIL PCIE IP
M: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+M: Xiaowei Bao <xiaowei.bao@nxp.com>
L: linux-pci@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
diff --git a/drivers/pci/controller/mobiveil/Kconfig b/drivers/pci/controller/mobiveil/Kconfig
index c823be8..2054950 100644
--- a/drivers/pci/controller/mobiveil/Kconfig
+++ b/drivers/pci/controller/mobiveil/Kconfig
@@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_MOBIVEIL
+config PCIE_MOBIVEIL_EP
+ bool
+ depends on PCI_ENDPOINT
+ select PCIE_MOBIVEIL
+
config PCIE_MOBIVEIL_PLAT
bool "Mobiveil AXI PCIe controller"
depends on ARCH_ZYNQMP || COMPILE_TEST
diff --git a/drivers/pci/controller/mobiveil/Makefile b/drivers/pci/controller/mobiveil/Makefile
index 99d879d..686d41f 100644
--- a/drivers/pci/controller/mobiveil/Makefile
+++ b/drivers/pci/controller/mobiveil/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
+obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
new file mode 100644
index 0000000..6e558dd
--- /dev/null
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mobiveil PCIe Endpoint controller driver
+ *
+ * Copyright (C) 2019 NXP Semiconductor.
+ * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
+ */
+
+#include <linux/of.h>
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+#include <linux/platform_device.h>
+#include "pcie-mobiveil.h"
+
+static void mobiveil_pcie_ep_func_select(struct mobiveil_pcie *pcie, u8 func_no)
+{
+ u32 func_num;
+
+ /*
+ * select to access the config space of func_no by setting func_no
+ * to FUNC_SEL_SHIFT bit of PAB_CTRL register.
+ */
+ func_num = csr_readl(pcie, PAB_CTRL);
+ func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
+ func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
+ csr_writel(pcie, func_num, PAB_CTRL);
+}
+
+static void mobiveil_pcie_ep_func_deselect(struct mobiveil_pcie *pcie)
+{
+ u32 func_num;
+
+ /*
+ * clear the FUNC_SEL_SHIFT bits when access other registers except
+ * config space register.
+ */
+ func_num = csr_readl(pcie, PAB_CTRL);
+ func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
+ csr_writel(pcie, func_num, PAB_CTRL);
+}
+
+static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
+{
+ csr_writel(pcie, bar, GPEX_BAR_SELECT);
+ csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
+ csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
+}
+
+void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
+{
+ __mobiveil_pcie_ep_reset_bar(pcie, bar);
+}
+
+static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
+ u8 func_no, u8 cap_ptr, u8 cap)
+{
+ u8 cap_id, next_cap_ptr;
+ u16 reg;
+
+ if (!cap_ptr)
+ return 0;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = csr_readw(pcie, cap_ptr);
+ cap_id = (reg & 0x00ff);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ if (cap_id > PCI_CAP_ID_MAX)
+ return 0;
+
+ if (cap_id == cap)
+ return cap_ptr;
+
+ next_cap_ptr = (reg & 0xff00) >> 8;
+ return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
+ next_cap_ptr, cap);
+}
+
+static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie_ep *ep,
+ u8 func_no, u8 cap)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ u8 next_cap_ptr;
+ u16 reg;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
+ next_cap_ptr = (reg & 0x00ff);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
+ next_cap_ptr, cap);
+}
+
+static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
+ struct pci_epf_header *hdr)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
+ csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
+ csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
+ csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
+ csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
+ PCI_CLASS_DEVICE);
+ csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
+ csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
+ csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
+ csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ return 0;
+}
+
+static void mobiveil_pcie_ep_inbound_win(struct mobiveil_pcie_ep *ep,
+ u8 func_no, enum pci_barno bar,
+ dma_addr_t cpu_addr)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
+}
+
+static int mobiveil_pcie_ep_outbound_win(struct mobiveil_pcie_ep *ep,
+ phys_addr_t phys_addr,
+ u64 pci_addr, u8 func_no,
+ size_t size)
+{
+ u32 free_win;
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ free_win = find_first_zero_bit(ep->apio_wins_map, ep->apio_wins);
+ if (free_win >= ep->apio_wins) {
+ dev_err(&pcie->pdev->dev, "No free outbound window\n");
+ return -EINVAL;
+ }
+
+ program_ob_windows_ep(pcie, func_no, free_win, phys_addr,
+ pci_addr, MEM_WINDOW_TYPE, size);
+
+ set_bit(free_win, ep->apio_wins_map);
+ ep->apio_addr[free_win] = phys_addr;
+
+ return 0;
+}
+
+static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
+ struct pci_epf_bar *epf_bar)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ enum pci_barno bar = epf_bar->barno;
+
+ if (bar < ep->bar_num) {
+ __mobiveil_pcie_ep_reset_bar(pcie, func_no * ep->bar_num + bar);
+
+ mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
+ }
+}
+
+static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
+ struct pci_epf_bar *epf_bar)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ enum pci_barno bar = epf_bar->barno;
+ size_t size = epf_bar->size;
+
+ if (bar < ep->bar_num) {
+ mobiveil_pcie_ep_inbound_win(ep, func_no, bar,
+ epf_bar->phys_addr);
+
+ csr_writel(pcie, func_no * ep->bar_num + bar,
+ GPEX_BAR_SELECT);
+ csr_writel(pcie, lower_32_bits(~(size - 1)),
+ GPEX_BAR_SIZE_LDW);
+ csr_writel(pcie, upper_32_bits(~(size - 1)),
+ GPEX_BAR_SIZE_UDW);
+ }
+
+ return 0;
+}
+
+static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
+ phys_addr_t addr,
+ u32 *atu_index)
+{
+ u32 index;
+
+ for (index = 0; index < ep->apio_wins; index++) {
+ if (ep->apio_addr[index] != addr)
+ continue;
+ *atu_index = index;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
+ phys_addr_t addr)
+{
+ int ret;
+ u32 atu_index;
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
+ if (ret < 0)
+ return;
+
+ mobiveil_pcie_disable_ob_win(pcie, atu_index);
+ clear_bit(atu_index, ep->apio_wins_map);
+}
+
+static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
+ phys_addr_t addr,
+ u64 pci_addr, size_t size)
+{
+ int ret;
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ ret = mobiveil_pcie_ep_outbound_win(ep, addr, pci_addr, func_no, size);
+ if (ret) {
+ dev_err(&pcie->pdev->dev, "Failed to enable address\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ u32 val, reg;
+ u8 msi_cap;
+
+ msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ if (!msi_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = msi_cap + PCI_MSI_FLAGS;
+ val = csr_readw(pcie, reg);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ if (!(val & PCI_MSI_FLAGS_ENABLE))
+ return -EINVAL;
+
+ val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+ return val;
+}
+
+static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
+ u8 func_no, u8 interrupts)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ u32 val, reg;
+ u8 msi_cap;
+
+ msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ if (!msi_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = msi_cap + PCI_MSI_FLAGS;
+ val = csr_readw(pcie, reg);
+ val &= ~PCI_MSI_FLAGS_QMASK;
+ val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
+ csr_writew(pcie, val, reg);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ return 0;
+}
+
+static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ u32 val, reg;
+ u8 msix_cap;
+
+ msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+ if (!msix_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = msix_cap + PCI_MSIX_FLAGS;
+ val = csr_readw(pcie, reg);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ if (!(val & PCI_MSIX_FLAGS_ENABLE))
+ return -EINVAL;
+
+ val &= PCI_MSIX_FLAGS_QSIZE;
+
+ return val;
+}
+
+static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
+ u16 interrupts)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ u32 val, reg;
+ u8 msix_cap;
+
+ msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+ if (!msix_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = msix_cap + PCI_MSIX_FLAGS;
+ val = csr_readw(pcie, reg);
+ val &= ~PCI_MSIX_FLAGS_QSIZE;
+ val |= interrupts;
+ csr_writew(pcie, val, reg);
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ return 0;
+}
+
+static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+
+ if (!ep->ops->raise_irq)
+ return -EINVAL;
+
+ return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
+}
+
+static const struct pci_epc_features*
+mobiveil_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+ struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
+
+ if (!ep->ops->get_features)
+ return NULL;
+
+ return ep->ops->get_features(ep);
+}
+
+static const struct pci_epc_ops epc_ops = {
+ .write_header = mobiveil_pcie_ep_write_header,
+ .set_bar = mobiveil_pcie_ep_set_bar,
+ .clear_bar = mobiveil_pcie_ep_clear_bar,
+ .map_addr = mobiveil_pcie_ep_map_addr,
+ .unmap_addr = mobiveil_pcie_ep_unmap_addr,
+ .set_msi = mobiveil_pcie_ep_set_msi,
+ .get_msi = mobiveil_pcie_ep_get_msi,
+ .set_msix = mobiveil_pcie_ep_set_msix,
+ .get_msix = mobiveil_pcie_ep_get_msix,
+ .raise_irq = mobiveil_pcie_ep_raise_irq,
+ .get_features = mobiveil_pcie_ep_get_features,
+};
+
+int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+
+ dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
+
+ return -EINVAL;
+}
+
+int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
+ u8 interrupt_num)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ struct pci_epc *epc = ep->epc;
+ u16 msg_ctrl, msg_data;
+ u32 msg_addr_lower, msg_addr_upper, reg;
+ u64 msg_addr;
+ bool has_upper;
+ int ret;
+ u8 msi_cap;
+
+ msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSI);
+ if (!msi_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_select(pcie, func_no);
+
+ reg = msi_cap + PCI_MSI_FLAGS;
+ msg_ctrl = csr_readw(pcie, reg);
+ has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
+ reg = msi_cap + PCI_MSI_ADDRESS_LO;
+ msg_addr_lower = csr_readl(pcie, reg);
+ if (has_upper) {
+ reg = msi_cap + PCI_MSI_ADDRESS_HI;
+ msg_addr_upper = csr_readl(pcie, reg);
+ reg = msi_cap + PCI_MSI_DATA_64;
+ msg_data = csr_readw(pcie, reg);
+ } else {
+ msg_addr_upper = 0;
+ reg = msi_cap + PCI_MSI_DATA_32;
+ msg_data = csr_readw(pcie, reg);
+ }
+ msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
+ msg_addr, epc->mem->page_size);
+ if (ret)
+ return ret;
+
+ writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+
+ mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
+
+ return 0;
+}
+
+int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num)
+{
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ struct pci_epc *epc = ep->epc;
+ u32 msg_addr_upper, msg_addr_lower;
+ u32 msg_data;
+ u64 msg_addr;
+ u8 msix_cap;
+ int ret;
+
+ msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
+ PCI_CAP_ID_MSIX);
+ if (!msix_cap)
+ return -EINVAL;
+
+ mobiveil_pcie_ep_func_deselect(pcie);
+
+ msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
+ PCI_MSIX_ENTRY_LOWER_ADDR +
+ (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
+ msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
+ PCI_MSIX_ENTRY_UPPER_ADDR +
+ (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
+ msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+ msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
+ PCI_MSIX_ENTRY_DATA +
+ (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
+
+ ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
+ msg_addr, epc->mem->page_size);
+ if (ret)
+ return ret;
+
+ writel(msg_data, ep->msi_mem);
+
+ mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
+
+ return 0;
+}
+
+void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
+{
+ struct pci_epc *epc = ep->epc;
+
+ pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
+ epc->mem->page_size);
+
+ pci_epc_mem_exit(epc);
+}
+
+int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
+{
+ int ret;
+ void *addr;
+ struct pci_epc *epc;
+ struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
+ struct device *dev = &pcie->pdev->dev;
+ struct device_node *np = dev->of_node;
+
+ if (!pcie->csr_axi_slave_base) {
+ dev_err(dev, "csr_base is not populated\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(np, "apio-wins", &ep->apio_wins);
+ if (ret < 0) {
+ dev_err(dev, "Unable to read apio-wins property\n");
+ return ret;
+ }
+
+ if (ep->apio_wins > MAX_IATU_OUT) {
+ dev_err(dev, "Invalid apio-wins\n");
+ return -EINVAL;
+ }
+ ep->apio_wins_map = devm_kcalloc(dev,
+ BITS_TO_LONGS(ep->apio_wins),
+ sizeof(long),
+ GFP_KERNEL);
+ if (!ep->apio_wins_map)
+ return -ENOMEM;
+
+ addr = devm_kcalloc(dev, ep->apio_wins, sizeof(phys_addr_t),
+ GFP_KERNEL);
+ if (!addr)
+ return -ENOMEM;
+
+ ep->apio_addr = addr;
+
+ mobiveil_pcie_enable_bridge_pio(pcie);
+ mobiveil_pcie_enable_engine_apio(pcie);
+ mobiveil_pcie_enable_engine_ppio(pcie);
+ mobiveil_pcie_enable_msi_ep(pcie);
+
+ epc = devm_pci_epc_create(dev, &epc_ops);
+ if (IS_ERR(epc)) {
+ dev_err(dev, "Failed to create epc device\n");
+ return PTR_ERR(epc);
+ }
+
+ ep->epc = epc;
+ epc_set_drvdata(epc, ep);
+
+ ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
+ if (ret < 0)
+ epc->max_functions = 1;
+
+ if (ep->ops->ep_init)
+ ep->ops->ep_init(ep);
+
+ ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
+ ep->page_size);
+ if (ret < 0) {
+ dev_err(dev, "Failed to initialize address space\n");
+ return ret;
+ }
+
+ ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
+ epc->mem->page_size);
+ if (!ep->msi_mem) {
+ dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 94b23be..6d47164 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -168,18 +168,12 @@ void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
/*
* routine to program the outbound windows
*/
-void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
- u64 pci_addr, u32 type, u64 size)
+void __program_ob_windows(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
+ u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
{
u32 value;
u64 size64 = ~(size - 1);
- if (win_num >= pcie->apio_wins) {
- dev_err(&pcie->pdev->dev,
- "ERROR: max outbound windows reached !\n");
- return;
- }
-
/*
* program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
* to 4 KB in PAB_AXI_AMAP_CTRL register
@@ -192,6 +186,7 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
+ csr_writel(pcie, func_no, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
/*
* program AXI window base with appropriate value in
* PAB_AXI_AMAP_AXI_WIN0 register
@@ -205,10 +200,98 @@ void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
PAB_AXI_AMAP_PEX_WIN_L(win_num));
csr_writel(pcie, upper_32_bits(pci_addr),
PAB_AXI_AMAP_PEX_WIN_H(win_num));
+}
+
+void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
+ u64 pci_addr, u32 type, u64 size)
+{
+ if (win_num >= pcie->apio_wins) {
+ dev_err(&pcie->pdev->dev,
+ "ERROR: max outbound windows reached !\n");
+ return;
+ }
+
+ __program_ob_windows(pcie, 0, win_num, cpu_addr,
+ pci_addr, type, size);
pcie->ob_wins_configured++;
}
+void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
+ u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
+{
+ if (size & (size - 1))
+ size = 1 << (1 + ilog2(size));
+
+ __program_ob_windows(pcie, func_no, win_num, cpu_addr,
+ pci_addr, type, size);
+}
+
+void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
+ int bar, u64 phys)
+{
+ csr_writel(pcie, upper_32_bits(phys),
+ PAB_EXT_PEX_BAR_AMAP(func_no, bar));
+ csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
+ PAB_PEX_BAR_AMAP(func_no, bar));
+}
+
+void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
+ u8 func_no, u8 bar)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
+ val &= ~(1 << 0);
+ csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
+}
+
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
+ val &= ~(1 << WIN_ENABLE_SHIFT);
+ csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
+}
+
+void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_CTRL);
+ val |= 1 << AMBA_PIO_ENABLE_SHIFT;
+ val |= 1 << PEX_PIO_ENABLE_SHIFT;
+ csr_writel(pcie, val, PAB_CTRL);
+}
+
+void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
+ val |= APIO_EN_MASK;
+ csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
+}
+
+void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
+ val |= 1 << PIO_ENABLE_SHIFT;
+ csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
+}
+
+void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
+{
+ u32 val;
+
+ val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
+ val |= PAB_INTP_PAMR;
+ csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
+}
+
int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
{
int retries;
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index b7e9603..7308fa4 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -15,8 +15,12 @@
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/msi.h>
+#include <linux/pci-epc.h>
+#include <linux/pci-epf.h>
+
#include "../../pci.h"
+#define MAX_IATU_OUT 256
/* register offsets and bit positions */
/*
@@ -42,6 +46,9 @@
#define PAGE_SEL_MASK 0x3f
#define PAGE_LO_MASK 0x3ff
#define PAGE_SEL_OFFSET_SHIFT 10
+#define FUNC_SEL_SHIFT 19
+#define FUNC_SEL_MASK 0x1ff
+#define MSI_SW_CTRL_EN BIT(29)
#define PAB_ACTIVITY_STAT 0x81c
@@ -52,6 +59,7 @@
#define PIO_ENABLE_SHIFT 0
#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
+#define PAB_INTP_PAMR BIT(0)
#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
#define PAB_INTP_RESET BIT(1)
#define PAB_INTP_MSI BIT(3)
@@ -72,6 +80,8 @@
#define WIN_TYPE_MASK 0x3
#define WIN_SIZE_MASK 0xfffffc00
+#define PAB_AXI_AMAP_PCI_HDR_PARAM(win) PAB_EXT_REG_ADDR(0x5ba0, win)
+
#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
@@ -101,6 +111,18 @@
#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
+/* PPIO WINs EP mode */
+#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
+#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
+#define PEX_BAR_AMAP_EN BIT(0)
+
+#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
+
+#define GPEX_BAR_ENABLE 0x4D4
+#define GPEX_BAR_SIZE_LDW 0x4D8
+#define GPEX_BAR_SIZE_UDW 0x4DC
+#define GPEX_BAR_SELECT 0x4E0
+
/* starting offset of INTX bits in status register */
#define PAB_INTX_START 5
@@ -138,6 +160,7 @@
((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
struct mobiveil_pcie;
+struct mobiveil_pcie_ep;
struct mobiveil_msi { /* MSI information */
struct mutex lock; /* protect bitmap variable */
@@ -170,6 +193,28 @@ struct mobiveil_pab_ops {
int (*host_init)(struct mobiveil_pcie *pcie);
};
+struct mobiveil_pcie_ep_ops {
+ void (*ep_init)(struct mobiveil_pcie_ep *ep);
+ int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type, u16 interrupt_num);
+ const struct pci_epc_features* (*get_features)
+ (struct mobiveil_pcie_ep *ep);
+};
+
+struct mobiveil_pcie_ep {
+ struct pci_epc *epc;
+ const struct mobiveil_pcie_ep_ops *ops;
+ phys_addr_t phys_base;
+ size_t addr_size;
+ size_t page_size;
+ phys_addr_t *apio_addr;
+ unsigned long *apio_wins_map;
+ u32 apio_wins;
+ void __iomem *msi_mem;
+ phys_addr_t msi_mem_phys;
+ u8 bar_num;
+};
+
struct mobiveil_pcie {
struct platform_device *pdev;
struct list_head *resources;
@@ -183,8 +228,12 @@ struct mobiveil_pcie {
const struct mobiveil_pab_ops *ops;
struct root_port rp;
struct pci_host_bridge *bridge;
+ struct mobiveil_pcie_ep ep;
};
+#define to_mobiveil_pcie_from_ep(endpoint) \
+ container_of((endpoint), struct mobiveil_pcie, ep)
+
int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
@@ -226,4 +275,23 @@ static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
csr_write(pcie, val, off, 0x1);
}
+void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
+ int bar, u64 phys);
+void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_num, int win_num,
+ u64 cpu_addr, u64 pci_addr, u32 type, u64 size);
+void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
+ u8 func_no, u8 bar);
+void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num);
+int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
+int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
+int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
+ u8 interrupt_num);
+int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
+ u16 interrupt_num);
+void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, u8 bar);
+u8 mobiveil_pcie_ep_get_bar_num(struct mobiveil_pcie_ep *ep, u8 func_no);
+void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
+void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
+void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
+void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
#endif /* _PCIE_MOBIVEIL_H */
--
2.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 6/6] misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support
From: Xiaowei Bao @ 2019-09-16 2:17 UTC (permalink / raw)
To: Zhiqiang.Hou, bhelgaas, robh+dt, mark.rutland, shawnguo,
leoyang.li, kishon, lorenzo.pieralisi, Minghuan.Lian,
andrew.murray, mingkai.hu, linux-pci, linux-arm-kernel,
devicetree, linux-kernel
Cc: Xiaowei Bao
In-Reply-To: <20190916021742.22844-1-xiaowei.bao@nxp.com>
Add the layerscape PCIE GEN4 EP device support in pci_endpoint_test driver.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 6e208a0..8b145a7 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -65,6 +65,7 @@
#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
#define PCI_DEVICE_ID_TI_AM654 0xb00c
+#define PCI_DEVICE_ID_LX2160A 0x8d80
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)
@@ -793,6 +794,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LX2160A) },
{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
.driver_data = (kernel_ulong_t)&am654_data
--
2.9.5
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* RE: [PATCH V3 2/5] input: keyboard: imx_sc: Add i.MX system controller key support
From: Anson Huang @ 2019-09-16 2:44 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: mark.rutland@arm.com, ulf.hansson@linaro.org, Jacky Bai,
catalin.marinas@arm.com, Peng Fan, stefan@agner.ch,
bjorn.andersson@linaro.org, Leonard Crestez, will@kernel.org,
festevam@gmail.com, yuehaibing@huawei.com,
marcin.juszkiewicz@linaro.org, jagan@amarulasolutions.com,
linux-input@vger.kernel.org, ronald@innovation.ch, dl-linux-imx,
devicetree@vger.kernel.org, arnd@arndb.de, s.hauer@pengutronix.de,
mripard@kernel.org, m.felsch@pengutronix.de, robh+dt@kernel.org,
tglx@linutronix.de, andriy.shevchenko@linux.intel.com,
Daniel Baluta, linux-arm-kernel@lists.infradead.org, Aisheng Dong,
Andy Duan, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, dinguyen@kernel.org,
kernel@pengutronix.de, olof@lixom.net, shawnguo@kernel.org
In-Reply-To: <20190912202239.GB636@penguin>
Hi, Dmitry
> On Tue, Sep 03, 2019 at 05:36:37PM -0400, Anson Huang wrote:
> > i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
> > inside, the system controller is in charge of controlling power, clock
> > and scu key etc..
> >
> > Adds i.MX system controller key driver support, Linux kernel has to
> > communicate with system controller via MU (message unit) IPC to get
> > scu key's status.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> > Changes since V2:
> > - use private platform data instead of global data;
> > - use "key" instead of "pwrkey";
> > - fix some data format.
> > ---
> > drivers/input/keyboard/Kconfig | 7 ++
> > drivers/input/keyboard/Makefile | 1 +
> > drivers/input/keyboard/imx_sc_key.c | 178
> > ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 186 insertions(+)
> > create mode 100644 drivers/input/keyboard/imx_sc_key.c
> >
> > diff --git a/drivers/input/keyboard/Kconfig
> > b/drivers/input/keyboard/Kconfig index 2e6d288..607acf2 100644
> > --- a/drivers/input/keyboard/Kconfig
> > +++ b/drivers/input/keyboard/Kconfig
> > @@ -469,6 +469,13 @@ config KEYBOARD_IMX
> > To compile this driver as a module, choose M here: the
> > module will be called imx_keypad.
> >
> > +config KEYBOARD_IMX_SC_KEY
> > + tristate "IMX SCU Key Driver"
> > + depends on IMX_SCU
> > + help
> > + This is the system controller key driver for NXP i.MX SoCs with
> > + system controller inside.
> > +
> > config KEYBOARD_NEWTON
> > tristate "Newton keyboard"
> > select SERIO
> > diff --git a/drivers/input/keyboard/Makefile
> > b/drivers/input/keyboard/Makefile index 9510325..f5b1752 100644
> > --- a/drivers/input/keyboard/Makefile
> > +++ b/drivers/input/keyboard/Makefile
> > @@ -29,6 +29,7 @@ obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o
> > obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o
> > obj-$(CONFIG_KEYBOARD_IPAQ_MICRO) += ipaq-micro-keys.o
> > obj-$(CONFIG_KEYBOARD_IMX) += imx_keypad.o
> > +obj-$(CONFIG_KEYBOARD_IMX_SC_KEY) += imx_sc_key.o
> > obj-$(CONFIG_KEYBOARD_HP6XX) += jornada680_kbd.o
> > obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o
> > obj-$(CONFIG_KEYBOARD_LKKBD) += lkkbd.o
> > diff --git a/drivers/input/keyboard/imx_sc_key.c
> > b/drivers/input/keyboard/imx_sc_key.c
> > new file mode 100644
> > index 0000000..e69479b
> > --- /dev/null
> > +++ b/drivers/input/keyboard/imx_sc_key.c
> > @@ -0,0 +1,178 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2019 NXP.
> > + */
> > +
> > +#include <linux/device.h>
> > +#include <linux/err.h>
> > +#include <linux/firmware/imx/sci.h>
> > +#include <linux/init.h>
> > +#include <linux/input.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define DEBOUNCE_TIME 100
> > +#define REPEAT_INTERVAL 60
> > +
> > +#define SC_IRQ_BUTTON 1
> > +#define SC_IRQ_GROUP_WAKE 3
> > +#define IMX_SC_MISC_FUNC_GET_BUTTON_STATUS 18
> > +
> > +struct imx_key_drv_data {
> > + int keycode;
> > + bool keystate; /* 1: pressed, 0: release */
> > + bool delay_check;
> > + struct delayed_work check_work;
> > + struct input_dev *input;
> > + struct imx_sc_ipc *key_ipc_handle;
> > + struct notifier_block key_notifier;
> > +};
> > +
> > +struct imx_sc_msg_key {
> > + struct imx_sc_rpc_msg hdr;
> > + u8 state;
> > +};
> > +
> > +static int imx_sc_key_notify(struct notifier_block *nb,
> > + unsigned long event, void *group) {
> > + struct imx_key_drv_data *priv =
> > + container_of(nb,
> > + struct imx_key_drv_data,
> > + key_notifier);
> > +
> > + if ((event & SC_IRQ_BUTTON) && (*(u8 *)group ==
> SC_IRQ_GROUP_WAKE)
> > + && !priv->delay_check) {
> > + priv->delay_check = 1;
> > + schedule_delayed_work(&priv->check_work,
> > + msecs_to_jiffies(REPEAT_INTERVAL));
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void imx_sc_check_for_events(struct work_struct *work) {
> > + struct imx_key_drv_data *priv =
> > + container_of(work,
> > + struct imx_key_drv_data,
> > + check_work.work);
> > + struct input_dev *input = priv->input;
> > + struct imx_sc_msg_key msg;
> > + struct imx_sc_rpc_msg *hdr = &msg.hdr;
> > + bool state;
> > + int ret;
> > +
> > + hdr->ver = IMX_SC_RPC_VERSION;
> > + hdr->svc = IMX_SC_RPC_SVC_MISC;
> > + hdr->func = IMX_SC_MISC_FUNC_GET_BUTTON_STATUS;
> > + hdr->size = 1;
> > +
> > + ret = imx_scu_call_rpc(priv->key_ipc_handle, &msg, true);
> > + if (ret) {
> > + dev_err(&input->dev, "read imx sc key failed, ret %d\n", ret);
> > + return;
> > + }
> > +
> > + state = (bool)msg.state;
> > +
> > + if (!state && !priv->keystate)
> > + state = true;
> > +
> > + if (state ^ priv->keystate) {
> > + pm_wakeup_event(input->dev.parent, 0);
> > + priv->keystate = state;
> > + input_event(input, EV_KEY, priv->keycode, state);
> > + input_sync(input);
> > + if (!state)
> > + priv->delay_check = 0;
> > + pm_relax(priv->input->dev.parent);
> > + }
> > +
> > + if (state)
> > + schedule_delayed_work(&priv->check_work,
> > + msecs_to_jiffies(DEBOUNCE_TIME));
>
> Hmm, I am not quite sure follow the code. Judging by the name, you are
> trying to handle debounce, but if I understand this correctly you already sent
> out the press event for now.
>
> Could you please explain what you are trying to do here.
The name is kind of confused, the "DEBOUNCE_TIME" here should be "REPEAT_INTERVAL"
actually, the "DEBOUNCE_TIME" should be used in the irq hanlder instead.
As the SCU ONLY send out interrupt when the key is pressed, so here we have to repeat
the delay work to loop check the button release event, the press event is sent out once the
key state is valid, and then start to check until key is released.
I will switch the "DEBOUNCE_TIME" and "REPEAT_INTERVAL" in V4.
>
> > +}
> > +
> > +static int imx_sc_key_probe(struct platform_device *pdev) {
> > + struct device_node *np = pdev->dev.of_node;
> > + static struct imx_key_drv_data *priv;
> > + struct input_dev *input;
> > + int ret;
> > +
> > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + ret = imx_scu_get_handle(&priv->key_ipc_handle);
> > + if (ret)
> > + return ret;
> > +
> > + if (of_property_read_u32(np, "linux,keycode", &priv->keycode)) {
> > + dev_err(&pdev->dev, "missing KEY_POWER in DT\n");
> > + return -EINVAL;
> > + }
> > +
> > + INIT_DELAYED_WORK(&priv->check_work,
> imx_sc_check_for_events);
> > +
> > + input = devm_input_allocate_device(&pdev->dev);
> > + if (!input) {
> > + dev_err(&pdev->dev, "failed to allocate the input device\n");
> > + return -ENOMEM;
> > + }
> > +
> > + input->name = pdev->name;
> > + input->phys = "imx-sc-key/input0";
> > + input->id.bustype = BUS_HOST;
> > +
> > + input_set_capability(input, EV_KEY, priv->keycode);
> > +
> > + ret = input_register_device(input);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to register input device\n");
> > + return ret;
> > + }
> > +
> > + priv->input = input;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = imx_scu_irq_group_enable(SC_IRQ_GROUP_WAKE,
> SC_IRQ_BUTTON, true);
> > + if (ret) {
> > + dev_warn(&pdev->dev, "enable scu group irq failed\n");
> > + return ret;
> > + }
> > +
> > + priv->key_notifier.notifier_call = imx_sc_key_notify;
> > + ret = imx_scu_irq_register_notifier(&priv->key_notifier);
> > + if (ret) {
> > + imx_scu_irq_group_enable(SC_IRQ_GROUP_WAKE,
> SC_IRQ_BUTTON, false);
> > + dev_warn(&pdev->dev, "register scu notifier failed\n");
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static const struct of_device_id imx_sc_key_ids[] = {
> > + { .compatible = "fsl,imx-sc-key" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx_sc_key_ids);
> > +
> > +static struct platform_driver imx_sc_key_driver = {
> > + .driver = {
> > + .name = "imx-sc-key",
> > + .of_match_table = imx_sc_key_ids,
> > + },
> > + .probe = imx_sc_key_probe,
>
> You need a remove() handler to disable the itq group, remove the notifier,
> cancel the delayed work, etc.
I will add it in V4.
Thanks,
Anson
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* linux-next: manual merge of the akpm-current tree with the dma-mapping tree
From: Mark Brown @ 2019-09-16 2:46 UTC (permalink / raw)
To: Andrew Morton, Christoph Hellwig, Matthew Wilcox
Cc: Linux Next Mailing List, Linux Kernel Mailing List,
linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 531 bytes --]
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
arch/arm/include/asm/xen/page-coherent.h
between commits:
bef4d2037d2143a ("xen/arm: consolidate page-coherent.h")
60d8cd572f655aa ("arm64/xen: fix xen-swiotlb cache flushing")
from the dma-mapping tree and commit:
46d5fa030cd9225 ("mm: introduce compound_nr()")
from the akpm-current tree. The former appear to make the latter
redundant so I resolved by dropping the relevant portions of the
commit from the akpm tree.
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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* [PATCH V4 1/5] dt-bindings: fsl: scu: add scu key binding
From: Anson Huang @ 2019-09-16 2:52 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
catalin.marinas, will, dmitry.torokhov, aisheng.dong, ulf.hansson,
fugang.duan, peng.fan, leonard.crestez, daniel.baluta, olof,
mripard, arnd, jagan, dinguyen, bjorn.andersson,
marcin.juszkiewicz, andriy.shevchenko, yuehaibing, cw00.choi,
enric.balletbo, m.felsch, ping.bai, ronald, stefan, devicetree,
linux-kernel, linux-arm-kernel, linux-input
Cc: Linux-imx
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and scu key event etc. management, Linux kernel has
to communicate with system controller via MU (message unit) IPC
to get scu key event, add binding doc for i.MX system controller
key driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
.../devicetree/bindings/arm/freescale/fsl,scu.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index c149fad..5eab7d0 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -157,6 +157,15 @@ Required properties:
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
+SCU key bindings based on SCU Message Protocol
+------------------------------------------------------------
+
+Required properties:
+- compatible: should be:
+ "fsl,imx8qxp-sc-key"
+ followed by "fsl,imx-sc-key";
+- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
+
Example (imx8qxp):
-------------
aliases {
@@ -220,6 +229,11 @@ firmware {
compatible = "fsl,imx8qxp-sc-rtc";
};
+ scu_key: scu-key {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycode = <KEY_POWER>;
+ };
+
watchdog {
compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
timeout-sec = <60>;
--
2.7.4
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