* Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi iova address
From: Auger Eric @ 2020-05-28 11:48 UTC (permalink / raw)
To: Shameerali Kolothum Thodi, Jean-Philippe Brucker
Cc: Will Deacon, Joerg Roedel, iommu@lists.linux-foundation.org,
Linux Kernel Mailing List, Alex Williamson, Srinath Mannam,
BCM Kernel Feedback, Robin Murphy, Linux ARM
In-Reply-To: <25ad278ae9ed4833aeb7b625fcb89d88@huawei.com>
On 5/28/20 11:15 AM, Shameerali Kolothum Thodi wrote:
>
>
>> -----Original Message-----
>> From: Auger Eric [mailto:eric.auger@redhat.com]
>> Sent: 28 May 2020 09:54
>> To: Jean-Philippe Brucker <jean-philippe@linaro.org>
>> Cc: Will Deacon <will@kernel.org>; Joerg Roedel <joro@8bytes.org>;
>> iommu@lists.linux-foundation.org; Shameerali Kolothum Thodi
>> <shameerali.kolothum.thodi@huawei.com>; Linux Kernel Mailing List
>> <linux-kernel@vger.kernel.org>; Alex Williamson
>> <alex.williamson@redhat.com>; Srinath Mannam
>> <srinath.mannam@broadcom.com>; BCM Kernel Feedback
>> <bcm-kernel-feedback-list@broadcom.com>; Robin Murphy
>> <robin.murphy@arm.com>; Linux ARM <linux-arm-kernel@lists.infradead.org>
>> Subject: Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi
>> iova address
>>
>> Hi,
>>
>> On 5/28/20 10:38 AM, Jean-Philippe Brucker wrote:
>>> [+ Shameer]
>>>
>>> On Thu, May 28, 2020 at 09:43:46AM +0200, Auger Eric wrote:
>>>> Hi,
>>>>
>>>> On 5/28/20 9:23 AM, Jean-Philippe Brucker wrote:
>>>>> On Thu, May 28, 2020 at 10:45:14AM +0530, Srinath Mannam wrote:
>>>>>> On Wed, May 27, 2020 at 11:00 PM Robin Murphy
>> <robin.murphy@arm.com> wrote:
>>>>>>>
>>>>>> Thanks Robin for your quick response.
>>>>>>> On 2020-05-27 17:03, Srinath Mannam wrote:
>>>>>>>> This patch gives the provision to change default value of MSI IOVA base
>>>>>>>> to platform's suitable IOVA using module parameter. The present
>>>>>>>> hardcoded MSI IOVA base may not be the accessible IOVA ranges of
>> platform.
>>>>>>>
>>>>>>> That in itself doesn't seem entirely unreasonable; IIRC the current
>>>>>>> address is just an arbitrary choice to fit nicely into Qemu's memory
>>>>>>> map, and there was always the possibility that it wouldn't suit
>> everything.
>>>>>>>
>>>>>>>> Since commit aadad097cd46 ("iommu/dma: Reserve IOVA for PCIe
>> inaccessible
>>>>>>>> DMA address"), inaccessible IOVA address ranges parsed from
>> dma-ranges
>>>>>>>> property are reserved.
>>>>>
>>>>> I don't understand why we only reserve the PCIe windows for DMA
>> domains.
>>>>> Shouldn't VFIO also prevent userspace from mapping them?
>>>>
>>>> VFIO prevents userspace from DMA mapping iovas within reserved regions:
>>>> 9b77e5c79840 vfio/type1: check dma map request is within a valid iova
>> range
>>>
>>> Right but I was asking specifically about the IOVA reservation introduced
>>> by commit aadad097cd46. They are not registered as reserved regions within
>>> the IOMMU core, they are only taken into account by dma-iommu.c when
>>> creating a DMA domain. As VFIO uses UNMANAGED domains, it isn't aware
>> of
>>> those regions and they won't be seen by vfio_iommu_resv_exclude().
>>>
>>> It looks like the PCIe regions used to be common until cd2c9fcf5c66
>>> ("iommu/dma: Move PCI window region reservation back into dma specific
>>> path.") But I couldn't find the justification for this commit.
>>
>> Yes I noticed that as well when debugging the above mentioned case
>> before and after cd2c9fcf5c66. I do not remember about the rationale of
>> removing the DMA host brige windows from the resv regions. Did it break
>> a legacy case?
>>>
>
> I think yes. And going through the ML discussions, this was done so because with the
> " vfio/type1: Add support for valid iova list management" series you reported
> an issue with Seattle platform. See the full discussion here,
>
> https://lore.kernel.org/patchwork/patch/889012/
Hey thank you for reminding me of the Seattle case :-) Now I also recall
that, if I am not wrong, this also caused some trouble on some x86
platforms as well, reported by Alex? Maybe we should still report PCI
host bridge windows in the reserved regions, if possible/feasible tag
them differently from other reserved regions and not reject any VFIO
DMA_MAP colliding with them?
Thanks
Eric
>
> Cheers,
> Shameer
>
>>> The thing is, if VFIO isn't aware of the reserved PCIe windows, then
>>> allowing VFIO or userspace to choose MSI_IOVA_BASE won't solve the
>> problem
>>> reported by Srinath, because they could well choose an IOVA within the
>>> PCIe window...
>> I agree with you
>>
>> Thanks
>>
>> Eric
>>>
>>> Thanks,
>>> Jean
>>>
>>>> but it does not prevent the SW MSI region chosen by the kernel from
>>>> colliding with other reserved regions (esp. PCIe host bridge windows).
>>>>
>>>> If they were
>>>>> part of the common reserved regions then we could have VFIO choose a
>>>>> SW_MSI region among the remaining free space.
>>>> As Robin said this was the initial chosen approach
>>>> [PATCH 10/10] vfio: allow the user to register reserved iova range for
>>>> MSI mapping
>>>> https://patchwork.kernel.org/patch/8121641/
>>>>
>>>> Some additional background about why the static SW MSI region chosen by
>>>> the kernel was later chosen:
>>>> Summary of LPC guest MSI discussion in Santa Fe (was: Re: [RFC 0/8] KVM
>>>> PCIe/MSI passthrough on ARM/ARM64 (Alt II))
>>>>
>> https://lists.linuxfoundation.org/pipermail/iommu/2016-November/019060.ht
>> ml
>>>>
>>>> Thanks
>>>>
>>>> Eric
>>>>
>>>>
>>>> It would just need a
>>>>> different way of asking the IOMMU driver if a SW_MSI is needed, for
>>>>> example with a domain attribute.
>>>>>
>>>>> Thanks,
>>>>> Jean
>>>>>
>>>>>>>
>>>>>>> That, however, doesn't seem to fit here; iommu-dma maps MSI
>> doorbells
>>>>>>> dynamically, so they aren't affected by reserved regions any more than
>>>>>>> regular DMA pages are. In fact, it explicitly ignores the software MSI
>>>>>>> region, since as the comment says, it *is* the software that manages
>> those.
>>>>>> Yes you are right, we don't see any issues with kernel drivers(PCI EP)
>> because
>>>>>> MSI IOVA allocated dynamically by honouring reserved regions same as
>> DMA pages.
>>>>>>>
>>>>>>> The MSI_IOVA_BASE region exists for VFIO, precisely because in that
>> case
>>>>>>> the kernel *doesn't* control the address space, but still needs some way
>>>>>>> to steal a bit of it for MSIs that the guest doesn't necessarily know
>>>>>>> about, and give userspace a fighting chance of knowing what it's taken.
>>>>>>> I think at the time we discussed the idea of adding something to the
>>>>>>> VFIO uapi such that userspace could move this around if it wanted or
>>>>>>> needed to, but decided we could live without that initially. Perhaps now
>>>>>>> the time has come?
>>>>>> Yes, we see issues only with user-space drivers(DPDK) in which
>> MSI_IOVA_BASE
>>>>>> region is considered to map MSI registers. This patch helps us to fix the
>> issue.
>>>>>>
>>>>>> Thanks,
>>>>>> Srinath.
>>>>>>>
>>>>>>> Robin.
>>>>>>>
>>>>>>>> If any platform has the limitaion to access default MSI IOVA, then it can
>>>>>>>> be changed using "arm-smmu.msi_iova_base=0xa0000000" command
>> line argument.
>>>>>>>>
>>>>>>>> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
>>>>>>>> ---
>>>>>>>> drivers/iommu/arm-smmu.c | 5 ++++-
>>>>>>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
>>>>>>>> index 4f1a350..5e59c9d 100644
>>>>>>>> --- a/drivers/iommu/arm-smmu.c
>>>>>>>> +++ b/drivers/iommu/arm-smmu.c
>>>>>>>> @@ -72,6 +72,9 @@ static bool disable_bypass =
>>>>>>>> module_param(disable_bypass, bool, S_IRUGO);
>>>>>>>> MODULE_PARM_DESC(disable_bypass,
>>>>>>>> "Disable bypass streams such that incoming transactions from
>> devices that are not attached to an iommu domain will report an abort back to
>> the device and will not be allowed to pass through the SMMU.");
>>>>>>>> +static unsigned long msi_iova_base = MSI_IOVA_BASE;
>>>>>>>> +module_param(msi_iova_base, ulong, S_IRUGO);
>>>>>>>> +MODULE_PARM_DESC(msi_iova_base, "msi iova base address.");
>>>>>>>>
>>>>>>>> struct arm_smmu_s2cr {
>>>>>>>> struct iommu_group *group;
>>>>>>>> @@ -1566,7 +1569,7 @@ static void
>> arm_smmu_get_resv_regions(struct device *dev,
>>>>>>>> struct iommu_resv_region *region;
>>>>>>>> int prot = IOMMU_WRITE | IOMMU_NOEXEC |
>> IOMMU_MMIO;
>>>>>>>>
>>>>>>>> - region = iommu_alloc_resv_region(MSI_IOVA_BASE,
>> MSI_IOVA_LENGTH,
>>>>>>>> + region = iommu_alloc_resv_region(msi_iova_base,
>> MSI_IOVA_LENGTH,
>>>>>>>> prot,
>> IOMMU_RESV_SW_MSI);
>>>>>>>> if (!region)
>>>>>>>> return;
>>>>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> linux-arm-kernel mailing list
>>>>> linux-arm-kernel@lists.infradead.org
>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>>
>>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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* Re: [PATCH/RFC] arm64/kernel: Fix return value when cpu_online() fails in __cpu_up()
From: Catalin Marinas @ 2020-05-28 11:53 UTC (permalink / raw)
To: Nobuhiro Iwamatsu, linux-arm-kernel
Cc: Mark Rutland, Gavin Shan, Will Deacon, Yuji Ishikawa
In-Reply-To: <20200527233457.2531118-1-nobuhiro1.iwamatsu@toshiba.co.jp>
On Thu, 28 May 2020 08:34:57 +0900, Nobuhiro Iwamatsu wrote:
> If boot_secondary() was successful, and cpu_online() was an error in
> __cpu_up(), -EIO was returned, but 0 is returned by commit d22b115cbfbb7
> ("arm64/kernel: Simplify __cpu_up() by bailing out early").
> Therefore, bringup_wait_for_ap() causes the primary core to wait for a
> long time, which may cause boot failure.
> This commit sets -EIO to return code under the same conditions.
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64/kernel: Fix return value when cpu_online() fails in __cpu_up()
https://git.kernel.org/arm64/c/ba051f097fc3
--
Catalin
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* [PATCH AUTOSEL 5.6 44/47] net: Fix return value about devm_platform_ioremap_resource()
From: Sasha Levin @ 2020-05-28 11:55 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Sasha Levin, netdev, linux-can, Tiezhu Yang, David S . Miller,
linux-arm-kernel
In-Reply-To: <20200528115600.1405808-1-sashal@kernel.org>
From: Tiezhu Yang <yangtiezhu@loongson.cn>
[ Upstream commit ef24d6c3d6965158dfe23ae961d87e9a343e18a2 ]
When call function devm_platform_ioremap_resource(), we should use IS_ERR()
to check the return value and return PTR_ERR() if failed.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/net/can/ifi_canfd/ifi_canfd.c | 5 ++++-
drivers/net/can/sun4i_can.c | 2 +-
drivers/net/dsa/b53/b53_srab.c | 2 +-
drivers/net/ethernet/marvell/pxa168_eth.c | 2 +-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/can/ifi_canfd/ifi_canfd.c b/drivers/net/can/ifi_canfd/ifi_canfd.c
index 04d59bede5ea..74503cacf594 100644
--- a/drivers/net/can/ifi_canfd/ifi_canfd.c
+++ b/drivers/net/can/ifi_canfd/ifi_canfd.c
@@ -947,8 +947,11 @@ static int ifi_canfd_plat_probe(struct platform_device *pdev)
u32 id, rev;
addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(addr))
+ return PTR_ERR(addr);
+
irq = platform_get_irq(pdev, 0);
- if (IS_ERR(addr) || irq < 0)
+ if (irq < 0)
return -EINVAL;
id = readl(addr + IFI_CANFD_IP_ID);
diff --git a/drivers/net/can/sun4i_can.c b/drivers/net/can/sun4i_can.c
index e3ba8ab0cbf4..e2c6cf4b2228 100644
--- a/drivers/net/can/sun4i_can.c
+++ b/drivers/net/can/sun4i_can.c
@@ -792,7 +792,7 @@ static int sun4ican_probe(struct platform_device *pdev)
addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(addr)) {
- err = -EBUSY;
+ err = PTR_ERR(addr);
goto exit;
}
diff --git a/drivers/net/dsa/b53/b53_srab.c b/drivers/net/dsa/b53/b53_srab.c
index 0a1be5259be0..38cd8285ac67 100644
--- a/drivers/net/dsa/b53/b53_srab.c
+++ b/drivers/net/dsa/b53/b53_srab.c
@@ -609,7 +609,7 @@ static int b53_srab_probe(struct platform_device *pdev)
priv->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->regs))
- return -ENOMEM;
+ return PTR_ERR(priv->regs);
dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, priv);
if (!dev)
diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 7a0d785b826c..17243bb5ba91 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -1418,7 +1418,7 @@ static int pxa168_eth_probe(struct platform_device *pdev)
pep->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pep->base)) {
- err = -ENOMEM;
+ err = PTR_ERR(pep->base);
goto err_netdev;
}
--
2.25.1
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* Re: [PATCH] clk: versatile: Fix kconfig dependency on COMMON_CLK_VERSATILE
From: Arnd Bergmann @ 2020-05-28 11:57 UTC (permalink / raw)
To: Rob Herring
Cc: Anders Roxell, Stephen Boyd, Michael Turquette, linux-clk,
SoC Team, Linus Walleij, Linux ARM
In-Reply-To: <20200527181307.2482167-1-robh@kernel.org>
On Wed, May 27, 2020 at 8:13 PM Rob Herring <robh@kernel.org> wrote:
> diff --git a/drivers/clk/versatile/Kconfig b/drivers/clk/versatile/Kconfig
> index a0ed412e8396..8c1b0e8e8d32 100644
> --- a/drivers/clk/versatile/Kconfig
> +++ b/drivers/clk/versatile/Kconfig
> @@ -1,11 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> -menuconfig COMMON_CLK_VERSATILE
> - bool "Clock driver for ARM Reference designs" if COMPILE_TEST
> - default y if ARCH_INTEGRATOR || ARCH_REALVIEW || \
> - ARCH_VERSATILE || ARCH_VEXPRESS
> -
> -if COMMON_CLK_VERSATILE
> +menu "Clock driver for ARM Reference designs"
> + depends on ARCH_INTEGRATOR || ARCH_REALVIEW || \
> + ARCH_VERSATILE || ARCH_VEXPRESS || COMPILE_TEST
>
I've applied this version now but added ARCH_ZYNQ as an additional
dependency to work around one of the warnings we got earlier.
Arnd
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* Re: [PATCH 1/3] KVM: arm64: Stop writing aarch32's CSSELR into ACTLR
From: James Morse @ 2020-05-28 11:59 UTC (permalink / raw)
To: Marc Zyngier
Cc: stable, Julien Thierry, kvmarm, linux-arm-kernel,
Suzuki K Poulose
In-Reply-To: <4be0c0b654f7d7c1efe9f52efb856bd8@kernel.org>
Hi Marc,
On 28/05/2020 09:57, Marc Zyngier wrote:
> On 2020-05-26 17:18, James Morse wrote:
>> access_csselr() uses the 32bit r->reg value to access the 64bit array,
>> so reads and write the wrong value. sys_regs[4], is ACTLR_EL1, which
>> is subsequently save/restored when we enter the guest.
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 51db934702b6..2eda539f3281 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -2060,7 +2060,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>>
>> { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
>> { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
>> - { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
>> + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr_el1, NULL, CSSELR_EL1 },
>> };
> This is a departure from the way we deal with 32bit CP15 registers.
> We deal with this exact issue in a very different way for other
> CP15 regs, by adjusting the index in the sys_regs array (see the
> way we handle the VM regs).
>
> How about something like this (untested):
[like access_vm_reg() does]
Sure, I'll give that a test and re-post it.
> Ideally, I'd like the core sys_reg code to deal with this sort
> of funnies, but I'm trying to keep the change minimal...
Roll this '/2' and upper/lower bits stuff into a vcpu_write_cp15_reg() that calls
vcpu_write_sys_reg()? (/me hunts out the todo list)
Thanks,
James
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* Re: [PATCH v6 01/18] dt-bindings: mtd: Document nand-ecc-placement
From: Boris Brezillon @ 2020-05-28 12:02 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-2-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:30:56 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> This optional property defines where the ECC bytes are expected to be
> stored. No value defaults to an unknown location, while these
> locations can be explicitly set to OOB or interleaved depending if
> the ECC bytes are entirely stored in the OOB area or mixed with
> regular data in the main area (also sometimes referred as
> "syndrome").
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> .../devicetree/bindings/mtd/nand-controller.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> index d261b7096c69..4a0798247d2d 100644
> --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> @@ -56,6 +56,16 @@ patternProperties:
> (Linux will handle the calculations). soft_bch is deprecated
> and should be replaced by soft and nand-ecc-algo.
>
> + nand-ecc-placement:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/string
> + - enum: [ oob, interleaved ]
> + description:
> + Location of the ECC bytes. This location is unknown by default
> + but can be explicitly set to "oob", if all ECC bytes are
> + known to be stored in the OOB area, or "interleaved" if ECC
> + bytes will be interleaved with regular data in the main area.
> +
> nand-ecc-algo:
> allOf:
> - $ref: /schemas/types.yaml#/definitions/string
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* Re: [PATCH v6 02/18] mtd: rawnand: Create a new enumeration to describe OOB placement
From: Boris Brezillon @ 2020-05-28 12:08 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-3-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:30:57 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
In the subject s/OOB placement/ECC placement/
> There is currently a confusion between the ECC type/mode/provider
> (eg. on-host, software, on-die or none) and the ECC bytes placement.
>
> Create a new enumeration to describe this placement.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/mtd/nand/raw/nand_base.c | 5 +++++
> include/linux/mtd/rawnand.h | 14 ++++++++++++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index bd3f5a875e39..4d2d444f9db9 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -5018,6 +5018,11 @@ static const char * const nand_ecc_modes[] = {
> [NAND_ECC_ON_DIE] = "on-die",
> };
>
> +static const char * const nand_ecc_placement[] = {
> + [NAND_ECC_PLACEMENT_OOB] = "oob",
> + [NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved",
> +};
> +
> static int of_get_nand_ecc_mode(struct device_node *np)
> {
> const char *pm;
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index 65b1c1c18b41..5e014807e050 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -92,6 +92,20 @@ enum nand_ecc_mode {
> NAND_ECC_ON_DIE,
> };
>
> +/**
> + * enum nand_ecc_placement - NAND ECC bytes placement
> + * @NAND_ECC_PLACEMENT_UNKNOWN: The actual position of the ECC bytes is unknown
> + * @NAND_ECC_PLACEMENT_OOB: The ECC bytes are located in the OOB area
> + * @NAND_ECC_PLACEMENT_INTERLEAVED: Syndrome layout, there are ECC bytes
> + * interleaved with regular data in the main
> + * area
> + */
> +enum nand_ecc_placement {
> + NAND_ECC_PLACEMENT_UNKNOWN,
> + NAND_ECC_PLACEMENT_OOB,
> + NAND_ECC_PLACEMENT_INTERLEAVED,
> +};
> +
> enum nand_ecc_algo {
> NAND_ECC_UNKNOWN,
> NAND_ECC_HAMMING,
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* RE: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi iova address
From: Shameerali Kolothum Thodi @ 2020-05-28 12:09 UTC (permalink / raw)
To: Auger Eric, Jean-Philippe Brucker
Cc: Will Deacon, Joerg Roedel, iommu@lists.linux-foundation.org,
Linux Kernel Mailing List, Alex Williamson, Srinath Mannam,
BCM Kernel Feedback, Robin Murphy, Linux ARM
In-Reply-To: <9aeb1cd5-48de-f581-1212-5c7b95fd8338@redhat.com>
> -----Original Message-----
> From: Auger Eric [mailto:eric.auger@redhat.com]
> Sent: 28 May 2020 12:48
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>;
> Jean-Philippe Brucker <jean-philippe@linaro.org>
> Cc: Robin Murphy <robin.murphy@arm.com>; Joerg Roedel
> <joro@8bytes.org>; iommu@lists.linux-foundation.org; Linux Kernel Mailing
> List <linux-kernel@vger.kernel.org>; Alex Williamson
> <alex.williamson@redhat.com>; Srinath Mannam
> <srinath.mannam@broadcom.com>; BCM Kernel Feedback
> <bcm-kernel-feedback-list@broadcom.com>; Will Deacon <will@kernel.org>;
> Linux ARM <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi
> iova address
>
>
>
> On 5/28/20 11:15 AM, Shameerali Kolothum Thodi wrote:
> >
> >
> >> -----Original Message-----
> >> From: Auger Eric [mailto:eric.auger@redhat.com]
> >> Sent: 28 May 2020 09:54
> >> To: Jean-Philippe Brucker <jean-philippe@linaro.org>
> >> Cc: Will Deacon <will@kernel.org>; Joerg Roedel <joro@8bytes.org>;
> >> iommu@lists.linux-foundation.org; Shameerali Kolothum Thodi
> >> <shameerali.kolothum.thodi@huawei.com>; Linux Kernel Mailing List
> >> <linux-kernel@vger.kernel.org>; Alex Williamson
> >> <alex.williamson@redhat.com>; Srinath Mannam
> >> <srinath.mannam@broadcom.com>; BCM Kernel Feedback
> >> <bcm-kernel-feedback-list@broadcom.com>; Robin Murphy
> >> <robin.murphy@arm.com>; Linux ARM
> <linux-arm-kernel@lists.infradead.org>
> >> Subject: Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set
> msi
> >> iova address
> >>
> >> Hi,
> >>
> >> On 5/28/20 10:38 AM, Jean-Philippe Brucker wrote:
> >>> [+ Shameer]
> >>>
> >>> On Thu, May 28, 2020 at 09:43:46AM +0200, Auger Eric wrote:
> >>>> Hi,
> >>>>
> >>>> On 5/28/20 9:23 AM, Jean-Philippe Brucker wrote:
> >>>>> On Thu, May 28, 2020 at 10:45:14AM +0530, Srinath Mannam wrote:
> >>>>>> On Wed, May 27, 2020 at 11:00 PM Robin Murphy
> >> <robin.murphy@arm.com> wrote:
> >>>>>>>
> >>>>>> Thanks Robin for your quick response.
> >>>>>>> On 2020-05-27 17:03, Srinath Mannam wrote:
> >>>>>>>> This patch gives the provision to change default value of MSI IOVA
> base
> >>>>>>>> to platform's suitable IOVA using module parameter. The present
> >>>>>>>> hardcoded MSI IOVA base may not be the accessible IOVA ranges of
> >> platform.
> >>>>>>>
> >>>>>>> That in itself doesn't seem entirely unreasonable; IIRC the current
> >>>>>>> address is just an arbitrary choice to fit nicely into Qemu's memory
> >>>>>>> map, and there was always the possibility that it wouldn't suit
> >> everything.
> >>>>>>>
> >>>>>>>> Since commit aadad097cd46 ("iommu/dma: Reserve IOVA for PCIe
> >> inaccessible
> >>>>>>>> DMA address"), inaccessible IOVA address ranges parsed from
> >> dma-ranges
> >>>>>>>> property are reserved.
> >>>>>
> >>>>> I don't understand why we only reserve the PCIe windows for DMA
> >> domains.
> >>>>> Shouldn't VFIO also prevent userspace from mapping them?
> >>>>
> >>>> VFIO prevents userspace from DMA mapping iovas within reserved
> regions:
> >>>> 9b77e5c79840 vfio/type1: check dma map request is within a valid iova
> >> range
> >>>
> >>> Right but I was asking specifically about the IOVA reservation introduced
> >>> by commit aadad097cd46. They are not registered as reserved regions
> within
> >>> the IOMMU core, they are only taken into account by dma-iommu.c when
> >>> creating a DMA domain. As VFIO uses UNMANAGED domains, it isn't
> aware
> >> of
> >>> those regions and they won't be seen by vfio_iommu_resv_exclude().
> >>>
> >>> It looks like the PCIe regions used to be common until cd2c9fcf5c66
> >>> ("iommu/dma: Move PCI window region reservation back into dma specific
> >>> path.") But I couldn't find the justification for this commit.
> >>
> >> Yes I noticed that as well when debugging the above mentioned case
> >> before and after cd2c9fcf5c66. I do not remember about the rationale of
> >> removing the DMA host brige windows from the resv regions. Did it break
> >> a legacy case?
> >>>
> >
> > I think yes. And going through the ML discussions, this was done so because
> with the
> > " vfio/type1: Add support for valid iova list management" series you reported
> > an issue with Seattle platform. See the full discussion here,
> >
> > https://lore.kernel.org/patchwork/patch/889012/
>
> Hey thank you for reminding me of the Seattle case :-) Now I also recall
> that, if I am not wrong, this also caused some trouble on some x86
> platforms as well, reported by Alex?
True, Alex reported that VT-d RMRR ranges were causing issues[1] as well.
And then you came with IOMMU_RESV_DIRECT_RELAXABLE regions
to exclude those[2]
Maybe we should still report PCI
> host bridge windows in the reserved regions, if possible/feasible tag
> them differently from other reserved regions and not reject any VFIO
> DMA_MAP colliding with them?
I guess that is possible. But current interface is to report the regions that are safe
from a IOMMU transaction point of view and I am not sure PCI window regions
comes under that.
Thanks,
Shameer
1. https://lkml.org/lkml/2018/6/5/760
2. https://lore.kernel.org/patchwork/cover/1083072/
> Thanks
>
> Eric
> >
> > Cheers,
> > Shameer
> >
> >>> The thing is, if VFIO isn't aware of the reserved PCIe windows, then
> >>> allowing VFIO or userspace to choose MSI_IOVA_BASE won't solve the
> >> problem
> >>> reported by Srinath, because they could well choose an IOVA within the
> >>> PCIe window...
> >> I agree with you
> >>
> >> Thanks
> >>
> >> Eric
> >>>
> >>> Thanks,
> >>> Jean
> >>>
> >>>> but it does not prevent the SW MSI region chosen by the kernel from
> >>>> colliding with other reserved regions (esp. PCIe host bridge windows).
> >>>>
> >>>> If they were
> >>>>> part of the common reserved regions then we could have VFIO choose a
> >>>>> SW_MSI region among the remaining free space.
> >>>> As Robin said this was the initial chosen approach
> >>>> [PATCH 10/10] vfio: allow the user to register reserved iova range for
> >>>> MSI mapping
> >>>> https://patchwork.kernel.org/patch/8121641/
> >>>>
> >>>> Some additional background about why the static SW MSI region chosen
> by
> >>>> the kernel was later chosen:
> >>>> Summary of LPC guest MSI discussion in Santa Fe (was: Re: [RFC 0/8] KVM
> >>>> PCIe/MSI passthrough on ARM/ARM64 (Alt II))
> >>>>
> >>
> https://lists.linuxfoundation.org/pipermail/iommu/2016-November/019060.ht
> >> ml
> >>>>
> >>>> Thanks
> >>>>
> >>>> Eric
> >>>>
> >>>>
> >>>> It would just need a
> >>>>> different way of asking the IOMMU driver if a SW_MSI is needed, for
> >>>>> example with a domain attribute.
> >>>>>
> >>>>> Thanks,
> >>>>> Jean
> >>>>>
> >>>>>>>
> >>>>>>> That, however, doesn't seem to fit here; iommu-dma maps MSI
> >> doorbells
> >>>>>>> dynamically, so they aren't affected by reserved regions any more
> than
> >>>>>>> regular DMA pages are. In fact, it explicitly ignores the software MSI
> >>>>>>> region, since as the comment says, it *is* the software that manages
> >> those.
> >>>>>> Yes you are right, we don't see any issues with kernel drivers(PCI EP)
> >> because
> >>>>>> MSI IOVA allocated dynamically by honouring reserved regions same as
> >> DMA pages.
> >>>>>>>
> >>>>>>> The MSI_IOVA_BASE region exists for VFIO, precisely because in that
> >> case
> >>>>>>> the kernel *doesn't* control the address space, but still needs some
> way
> >>>>>>> to steal a bit of it for MSIs that the guest doesn't necessarily know
> >>>>>>> about, and give userspace a fighting chance of knowing what it's
> taken.
> >>>>>>> I think at the time we discussed the idea of adding something to the
> >>>>>>> VFIO uapi such that userspace could move this around if it wanted or
> >>>>>>> needed to, but decided we could live without that initially. Perhaps
> now
> >>>>>>> the time has come?
> >>>>>> Yes, we see issues only with user-space drivers(DPDK) in which
> >> MSI_IOVA_BASE
> >>>>>> region is considered to map MSI registers. This patch helps us to fix the
> >> issue.
> >>>>>>
> >>>>>> Thanks,
> >>>>>> Srinath.
> >>>>>>>
> >>>>>>> Robin.
> >>>>>>>
> >>>>>>>> If any platform has the limitaion to access default MSI IOVA, then it
> can
> >>>>>>>> be changed using "arm-smmu.msi_iova_base=0xa0000000"
> command
> >> line argument.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
> >>>>>>>> ---
> >>>>>>>> drivers/iommu/arm-smmu.c | 5 ++++-
> >>>>>>>> 1 file changed, 4 insertions(+), 1 deletion(-)
> >>>>>>>>
> >>>>>>>> diff --git a/drivers/iommu/arm-smmu.c
> b/drivers/iommu/arm-smmu.c
> >>>>>>>> index 4f1a350..5e59c9d 100644
> >>>>>>>> --- a/drivers/iommu/arm-smmu.c
> >>>>>>>> +++ b/drivers/iommu/arm-smmu.c
> >>>>>>>> @@ -72,6 +72,9 @@ static bool disable_bypass =
> >>>>>>>> module_param(disable_bypass, bool, S_IRUGO);
> >>>>>>>> MODULE_PARM_DESC(disable_bypass,
> >>>>>>>> "Disable bypass streams such that incoming transactions
> from
> >> devices that are not attached to an iommu domain will report an abort back
> to
> >> the device and will not be allowed to pass through the SMMU.");
> >>>>>>>> +static unsigned long msi_iova_base = MSI_IOVA_BASE;
> >>>>>>>> +module_param(msi_iova_base, ulong, S_IRUGO);
> >>>>>>>> +MODULE_PARM_DESC(msi_iova_base, "msi iova base address.");
> >>>>>>>>
> >>>>>>>> struct arm_smmu_s2cr {
> >>>>>>>> struct iommu_group *group;
> >>>>>>>> @@ -1566,7 +1569,7 @@ static void
> >> arm_smmu_get_resv_regions(struct device *dev,
> >>>>>>>> struct iommu_resv_region *region;
> >>>>>>>> int prot = IOMMU_WRITE | IOMMU_NOEXEC |
> >> IOMMU_MMIO;
> >>>>>>>>
> >>>>>>>> - region = iommu_alloc_resv_region(MSI_IOVA_BASE,
> >> MSI_IOVA_LENGTH,
> >>>>>>>> + region = iommu_alloc_resv_region(msi_iova_base,
> >> MSI_IOVA_LENGTH,
> >>>>>>>> prot,
> >> IOMMU_RESV_SW_MSI);
> >>>>>>>> if (!region)
> >>>>>>>> return;
> >>>>>>>>
> >>>>>
> >>>>> _______________________________________________
> >>>>> linux-arm-kernel mailing list
> >>>>> linux-arm-kernel@lists.infradead.org
> >>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>>>>
> >>>>
> >>>
> >>> _______________________________________________
> >>> linux-arm-kernel mailing list
> >>> linux-arm-kernel@lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>>
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
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* Re: [PATCH 1/3] KVM: arm64: Stop writing aarch32's CSSELR into ACTLR
From: Marc Zyngier @ 2020-05-28 12:10 UTC (permalink / raw)
To: James Morse
Cc: stable, Julien Thierry, kvmarm, linux-arm-kernel,
Suzuki K Poulose
In-Reply-To: <09dca8e9-c548-43fd-a95b-747a77f19e02@arm.com>
On 2020-05-28 12:59, James Morse wrote:
> Hi Marc,
>
> On 28/05/2020 09:57, Marc Zyngier wrote:
>> On 2020-05-26 17:18, James Morse wrote:
>>> access_csselr() uses the 32bit r->reg value to access the 64bit
>>> array,
>>> so reads and write the wrong value. sys_regs[4], is ACTLR_EL1, which
>>> is subsequently save/restored when we enter the guest.
>
>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>> index 51db934702b6..2eda539f3281 100644
>>> --- a/arch/arm64/kvm/sys_regs.c
>>> +++ b/arch/arm64/kvm/sys_regs.c
>>> @@ -2060,7 +2060,7 @@ static const struct sys_reg_desc cp15_regs[] =
>>> {
>>>
>>> { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
>>> { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
>>> - { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL,
>>> c0_CSSELR },
>>> + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr_el1, NULL,
>>> CSSELR_EL1 },
>>> };
>
>> This is a departure from the way we deal with 32bit CP15 registers.
>> We deal with this exact issue in a very different way for other
>> CP15 regs, by adjusting the index in the sys_regs array (see the
>> way we handle the VM regs).
>>
>> How about something like this (untested):
>
> [like access_vm_reg() does]
>
> Sure, I'll give that a test and re-post it.
Thanks!
>
>
>> Ideally, I'd like the core sys_reg code to deal with this sort
>> of funnies, but I'm trying to keep the change minimal...
>
> Roll this '/2' and upper/lower bits stuff into a vcpu_write_cp15_reg()
> that calls
> vcpu_write_sys_reg()? (/me hunts out the todo list)
I was thinking of hiding it differently: in emulate_cp, substitute the
sys_reg_desc structure for a temporary one that represents the 64bit
version, and make it completely transparent.
I'm sure there is a couple of nits around that though...
M.
--
Jazz is not dead. It just smells funny...
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* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Andy Shevchenko @ 2020-05-28 12:22 UTC (permalink / raw)
To: Marco Felsch
Cc: Dmitry Torokhov, linux-mediatek, linux-input, Yingjoe Chen,
Fengping Yu, linux-arm-kernel
In-Reply-To: <20200528114558.5decxsun2o65k2fr@pengutronix.de>
On Thu, May 28, 2020 at 01:45:58PM +0200, Marco Felsch wrote:
> On 20-05-28 13:27, Andy Shevchenko wrote:
> > On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
...
> > > + select CONFIG_REGMAP_MMIO
> >
> > This is wrong.
>
> Why is this wrong? The driver uses the rmap-mmio functions.
In Kconfig CONFIG_ prefix is implied.
There is no CONFIG_CONFIG_REGMAP_MMIO.
> Thanks for the explanation =)
Sorry, I think it's obvious...
> > > + select INPUT_MATRIXKMAP
--
With Best Regards,
Andy Shevchenko
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* Re: [RESEND PATCH v11 2/3] drivers: input: keyboard: Add mtk keypad driver
From: Marco Felsch @ 2020-05-28 12:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Dmitry Torokhov, linux-mediatek, linux-input, Yingjoe Chen,
Fengping Yu, linux-arm-kernel
In-Reply-To: <20200528122248.GL1634618@smile.fi.intel.com>
On 20-05-28 15:22, Andy Shevchenko wrote:
> On Thu, May 28, 2020 at 01:45:58PM +0200, Marco Felsch wrote:
> > On 20-05-28 13:27, Andy Shevchenko wrote:
> > > On Thu, May 28, 2020 at 05:01:47PM +0800, Fengping Yu wrote:
>
> ...
>
> > > > + select CONFIG_REGMAP_MMIO
> > >
> > > This is wrong.
> >
> > Why is this wrong? The driver uses the rmap-mmio functions.
>
> In Kconfig CONFIG_ prefix is implied.
>
> There is no CONFIG_CONFIG_REGMAP_MMIO.
>
> > Thanks for the explanation =)
>
> Sorry, I think it's obvious...
Damn, you right it is. Bloody automatism mismatch in my brain.
Regards,
Marco
>
> > > > + select INPUT_MATRIXKMAP
>
> --
> With Best Regards,
> Andy Shevchenko
>
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* [PATCH 0/2] regmap: provide simple bitops and use them in a driver
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Hi Mark,
I noticed that oftentimes I use regmap_update_bits() for simple bit
setting or clearing. In this case the fourth argument is superfluous as
it's always 0 or equal to the mask argument.
This series proposes to add simple bit operations for setting, clearing
and testing specific bits with regmap.
The second patch uses all three in a driver that got recently picked into
the net-next tree.
The patches obviously target different trees so - if you're ok with
the change itself - I propose you pick the first one into your regmap
tree for v5.8 and then I'll resend the second patch to add the first
user for these macros for v5.9.
Bartosz Golaszewski (2):
regmap: provide helpers for simple bit operations
net: ethernet: mtk-star-emac: use regmap bitops
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
include/linux/regmap.h | 18 +++++
2 files changed, 53 insertions(+), 45 deletions(-)
--
2.25.0
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* [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528123459.21168-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a macro.
This adds three new macros for simple bit operations: set_bits,
clear_bits and test_bits.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
include/linux/regmap.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 40b07168fd8e..6ef829169f36 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -71,6 +71,24 @@ struct reg_sequence {
unsigned int delay_us;
};
+#define regmap_set_bits(map, reg, bits) \
+ regmap_update_bits_base(map, reg, bits, bits, NULL, false, false)
+#define regmap_clear_bits(map, reg, bits) \
+ regmap_update_bits_base(map, reg, bits, 0, NULL, false, false)
+/*
+ * Returns -1 if the underlying regmap_read() fails, 0 if at least one of the
+ * tested bits is not set and 1 if all tested bits are set.
+ */
+#define regmap_test_bits(map, reg, bits) \
+({ \
+ unsigned int __val, __ret, __bits; \
+ __bits = (bits); \
+ __ret = regmap_read(map, reg, &__val); \
+ if (__ret == 0) \
+ __ret = (__val & __bits) == __bits ? 1 : 0; \
+ __ret; \
+})
+
#define regmap_update_bits(map, reg, mask, val) \
regmap_update_bits_base(map, reg, mask, val, NULL, false, false)
#define regmap_update_bits_async(map, reg, mask, val)\
--
2.25.0
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* [PATCH 2/2] net: ethernet: mtk-star-emac: use regmap bitops
From: Bartosz Golaszewski @ 2020-05-28 12:34 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528123459.21168-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Shrink the code visually by replacing regmap_update_bits() with
appropriate regmap bit operations where applicable.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
1 file changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index 8596ca0e60eb..326ac792a4a0 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -413,8 +413,8 @@ static void mtk_star_dma_unmap_tx(struct mtk_star_priv *priv,
static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_NIC_PD, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_NIC_PD);
}
/* Unmask the three interrupts we care about, mask all others. */
@@ -434,41 +434,38 @@ static void mtk_star_intr_disable(struct mtk_star_priv *priv)
static void mtk_star_intr_enable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_enable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_enable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static void mtk_star_intr_disable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC,
- MTK_STAR_BIT_INT_STS_TNTC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_disable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC,
- MTK_STAR_BIT_INT_STS_FNRC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_disable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv)
@@ -524,12 +521,10 @@ static void mtk_star_dma_init(struct mtk_star_priv *priv)
static void mtk_star_dma_start(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_START,
- MTK_STAR_BIT_TX_DMA_CTRL_START);
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_START,
- MTK_STAR_BIT_RX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_START);
}
static void mtk_star_dma_stop(struct mtk_star_priv *priv)
@@ -553,16 +548,14 @@ static void mtk_star_dma_disable(struct mtk_star_priv *priv)
static void mtk_star_dma_resume_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
}
static void mtk_star_dma_resume_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
}
static void mtk_star_set_mac_addr(struct net_device *ndev)
@@ -845,8 +838,8 @@ static int mtk_star_hash_wait_ok(struct mtk_star_priv *priv)
return ret;
/* Check the BIST_OK bit. */
- regmap_read(priv->regs, MTK_STAR_REG_HASH_CTRL, &val);
- if (!(val & MTK_STAR_BIT_HASH_CTRL_BIST_OK))
+ if (!regmap_test_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_OK))
return -EIO;
return 0;
@@ -880,12 +873,10 @@ static int mtk_star_reset_hash_table(struct mtk_star_priv *priv)
if (ret)
return ret;
- regmap_update_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN);
- regmap_update_bits(priv->regs, MTK_STAR_REG_TEST1,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_EN);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1,
+ MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
return mtk_star_hash_wait_ok(priv);
}
@@ -1016,13 +1007,13 @@ static int mtk_star_enable(struct net_device *ndev)
return ret;
/* Setup the hashing algorithm */
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_HASH_ALG |
- MTK_STAR_BIT_ARL_CFG_MISC_MODE, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_HASH_ALG |
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
/* Don't strip VLAN tags */
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_VLAN_STRIP, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_VLAN_STRIP);
/* Setup DMA */
mtk_star_dma_init(priv);
@@ -1204,9 +1195,8 @@ static void mtk_star_set_rx_mode(struct net_device *ndev)
int ret;
if (ndev->flags & IFF_PROMISC) {
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
} else if (netdev_mc_count(ndev) > MTK_STAR_HASHTABLE_MC_LIMIT ||
ndev->flags & IFF_ALLMULTI) {
for (i = 0; i < MTK_STAR_HASHTABLE_SIZE_MAX; i++) {
--
2.25.0
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^ permalink raw reply related
* Re: [PATCH 2/3] KVM: arm64: Stop save/restoring ACTLR_EL1
From: Marc Zyngier @ 2020-05-28 12:36 UTC (permalink / raw)
To: James Morse; +Cc: Julien Thierry, kvmarm, linux-arm-kernel, Suzuki K Poulose
In-Reply-To: <20200526161834.29165-3-james.morse@arm.com>
On 2020-05-26 17:18, James Morse wrote:
> KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
TAC is a leftover from 32bit.
> This means ACTLR* accesses from the guest are always trapped, and
> always return the value in the sys_regs array.
>
> The guest can't change the value of these registers, so we are
> save restoring the reset value, which came from the host.
>
> Stop save/restoring this register.
>
> This also stops this register being affected by sysregs_loaded_on_cpu,
> so we can provide 32 bit accessors that always use the in-memory copy.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> arch/arm64/kvm/hyp/sysreg-sr.c | 2 --
> arch/arm64/kvm/sys_regs.c | 2 --
> 2 files changed, 4 deletions(-)
>
> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c
> b/arch/arm64/kvm/hyp/sysreg-sr.c
> index 75b1925763f1..57116cf3a1a5 100644
> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> @@ -44,7 +44,6 @@ static void __hyp_text
> __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
> {
> ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
> ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(SYS_SCTLR);
> - ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
> ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(SYS_CPACR);
> ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(SYS_TTBR0);
> ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(SYS_TTBR1);
> @@ -133,7 +132,6 @@ static void __hyp_text
> __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> isb();
> }
>
> - write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
If we don't need to save/restore it, we can also drop its presence
in the sys_regs array.
> write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], SYS_CPACR);
> write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], SYS_TTBR0);
> write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], SYS_TTBR1);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2eda539f3281..aae58513025c 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -81,7 +81,6 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu,
> int reg)
> switch (reg) {
> case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1);
> case SCTLR_EL1: return read_sysreg_s(SYS_SCTLR_EL12);
> - case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1);
> case CPACR_EL1: return read_sysreg_s(SYS_CPACR_EL12);
> case TTBR0_EL1: return read_sysreg_s(SYS_TTBR0_EL12);
> case TTBR1_EL1: return read_sysreg_s(SYS_TTBR1_EL12);
> @@ -124,7 +123,6 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64
> val, int reg)
> switch (reg) {
> case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return;
> case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return;
> - case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return;
> case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return;
> case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return;
> case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return;
It strikes me that we don't even have a trap handler for this sysreg,
whether it is 32 or 64bit... That's a bit unfortunate, to say the
least...
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: [PATCH 2/3] KVM: arm64: Stop save/restoring ACTLR_EL1
From: Marc Zyngier @ 2020-05-28 12:38 UTC (permalink / raw)
To: James Morse; +Cc: Julien Thierry, kvmarm, linux-arm-kernel, Suzuki K Poulose
In-Reply-To: <4d42a5db0b573c7a184aea654829a06c@kernel.org>
On 2020-05-28 13:36, Marc Zyngier wrote:
> On 2020-05-26 17:18, James Morse wrote:
>> KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
>
> TAC is a leftover from 32bit.
>
>> This means ACTLR* accesses from the guest are always trapped, and
>> always return the value in the sys_regs array.
>>
>> The guest can't change the value of these registers, so we are
>> save restoring the reset value, which came from the host.
>>
>> Stop save/restoring this register.
>>
>> This also stops this register being affected by sysregs_loaded_on_cpu,
>> so we can provide 32 bit accessors that always use the in-memory copy.
>>
>> Signed-off-by: James Morse <james.morse@arm.com>
>> ---
>> arch/arm64/kvm/hyp/sysreg-sr.c | 2 --
>> arch/arm64/kvm/sys_regs.c | 2 --
>> 2 files changed, 4 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c
>> b/arch/arm64/kvm/hyp/sysreg-sr.c
>> index 75b1925763f1..57116cf3a1a5 100644
>> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
>> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
>> @@ -44,7 +44,6 @@ static void __hyp_text
>> __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
>> {
>> ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
>> ctxt->sys_regs[SCTLR_EL1] = read_sysreg_el1(SYS_SCTLR);
>> - ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
>> ctxt->sys_regs[CPACR_EL1] = read_sysreg_el1(SYS_CPACR);
>> ctxt->sys_regs[TTBR0_EL1] = read_sysreg_el1(SYS_TTBR0);
>> ctxt->sys_regs[TTBR1_EL1] = read_sysreg_el1(SYS_TTBR1);
>> @@ -133,7 +132,6 @@ static void __hyp_text
>> __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
>> isb();
>> }
>>
>> - write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
>
> If we don't need to save/restore it, we can also drop its presence
> in the sys_regs array.
>
>> write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], SYS_CPACR);
>> write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], SYS_TTBR0);
>> write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], SYS_TTBR1);
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 2eda539f3281..aae58513025c 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -81,7 +81,6 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu,
>> int reg)
>> switch (reg) {
>> case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1);
>> case SCTLR_EL1: return read_sysreg_s(SYS_SCTLR_EL12);
>> - case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1);
>> case CPACR_EL1: return read_sysreg_s(SYS_CPACR_EL12);
>> case TTBR0_EL1: return read_sysreg_s(SYS_TTBR0_EL12);
>> case TTBR1_EL1: return read_sysreg_s(SYS_TTBR1_EL12);
>> @@ -124,7 +123,6 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64
>> val, int reg)
>> switch (reg) {
>> case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return;
>> case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return;
>> - case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return;
>> case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return;
>> case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return;
>> case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return;
>
> It strikes me that we don't even have a trap handler for this sysreg,
> whether it is 32 or 64bit... That's a bit unfortunate, to say the
> least...
Ah, no. the sucker is hidden away in "generic_v8"...
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: [PATCH 3/3] KVM: arm64: Add emulation for 32bit guests accessing ACTLR2
From: Marc Zyngier @ 2020-05-28 12:51 UTC (permalink / raw)
To: James Morse; +Cc: Julien Thierry, kvmarm, linux-arm-kernel, Suzuki K Poulose
In-Reply-To: <20200526161834.29165-4-james.morse@arm.com>
Hi James,
On 2020-05-26 17:18, James Morse wrote:
> ACTLR_EL1 is a 64bit register while the 32bit ACTLR is obviously 32bit.
> For 32bit software, the extra bits are accessible via ACTLR2... which
> KVM doesn't emulate.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> I'm not convinced this is endian safe, but it does match what
> kvm_inject_undef32() do.
>
> The alternative would be to always read the 64bit value, and generate
> the 32bit offets like access_vm_reg() does.
>
> arch/arm64/include/asm/kvm_host.h | 1 +
> arch/arm64/kvm/sys_regs_generic_v8.c | 16 +++++++++++++++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/kvm_host.h
> b/arch/arm64/include/asm/kvm_host.h
> index 32c8a675e5a4..5b7538663a8e 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -185,6 +185,7 @@ enum vcpu_sysreg {
> #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
> #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
> #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
> +#define c1_ACTLR2 (c1_ACTLR + 1) /* ACTLR top 32 bits */
> #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
> #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0
> */
> #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
> diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c
> b/arch/arm64/kvm/sys_regs_generic_v8.c
> index 9cb6b4c8355a..ed77bbb48e64 100644
> --- a/arch/arm64/kvm/sys_regs_generic_v8.c
> +++ b/arch/arm64/kvm/sys_regs_generic_v8.c
> @@ -30,6 +30,18 @@ static bool access_actlr(struct kvm_vcpu *vcpu,
> return true;
> }
>
> +static bool access_cp15_actlr(struct kvm_vcpu *vcpu,
> + struct sys_reg_params *p,
> + const struct sys_reg_desc *r)
> +{
> + if (p->is_write)
> + return ignore_write(vcpu, p);
> +
> + p->regval = vcpu_cp15(vcpu, r->reg);
> + return true;
> +
> +}
> +
> static void reset_actlr(struct kvm_vcpu *vcpu, const struct
> sys_reg_desc *r)
> {
> __vcpu_sys_reg(vcpu, ACTLR_EL1) = read_sysreg(actlr_el1);
> @@ -46,7 +58,9 @@ static const struct sys_reg_desc genericv8_sys_regs[]
> = {
> static const struct sys_reg_desc genericv8_cp15_regs[] = {
> /* ACTLR */
> { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
> - access_actlr },
> + access_cp15_actlr, NULL, c1_ACTLR },
> + { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b011),
> + access_cp15_actlr, NULL, c1_ACTLR2 },
> };
>
> static struct kvm_sys_reg_target_table genericv8_target_table = {
I'd get rid of any form of storage, and go with something like
(untested, again):
diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c
b/arch/arm64/kvm/sys_regs_generic_v8.c
index 9cb6b4c8355a..1b2bf2d37612 100644
--- a/arch/arm64/kvm/sys_regs_generic_v8.c
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -26,13 +26,16 @@ static bool access_actlr(struct kvm_vcpu *vcpu,
if (p->is_write)
return ignore_write(vcpu, p);
- p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
- return true;
-}
+ p->regval = read_sysreg(actlr_el1);
-static void reset_actlr(struct kvm_vcpu *vcpu, const struct
sys_reg_desc *r)
-{
- __vcpu_sys_reg(vcpu, ACTLR_EL1) = read_sysreg(actlr_el1);
+ if (p->aarch32) {
+ if (r->Op2 & 2)
+ p->regval = upper_32_bit(p->regval);
+ else
+ p->regval = lower_32_bit(p->regval);
+ }
+
+ return true;
}
/*
@@ -40,13 +43,13 @@ static void reset_actlr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
*/
static const struct sys_reg_desc genericv8_sys_regs[] = {
- { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
+ { SYS_DESC(SYS_ACTLR_EL1), access_actlr, },
};
static const struct sys_reg_desc genericv8_cp15_regs[] = {
/* ACTLR */
- { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
- access_actlr },
+ { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001), access_actlr },
+ { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b011), access_actlr },
};
static struct kvm_sys_reg_target_table genericv8_target_table = {
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply related
* Re: [PATCH 2/3] KVM: arm64: Stop save/restoring ACTLR_EL1
From: James Morse @ 2020-05-28 12:55 UTC (permalink / raw)
To: Marc Zyngier; +Cc: Julien Thierry, kvmarm, linux-arm-kernel, Suzuki K Poulose
In-Reply-To: <07d09551c456c6be326473e003def3ab@kernel.org>
Hi Marc,
On 28/05/2020 13:38, Marc Zyngier wrote:
> On 2020-05-28 13:36, Marc Zyngier wrote:
>> On 2020-05-26 17:18, James Morse wrote:
>>> KVM sets HCR_EL2.TACR (which it calls HCR_TAC) via HCR_GUEST_FLAGS.
>>> This means ACTLR* accesses from the guest are always trapped, and
>>> always return the value in the sys_regs array.
>>>
>>> The guest can't change the value of these registers, so we are
>>> save restoring the reset value, which came from the host.
>>>
>>> Stop save/restoring this register.
>>>
>>> This also stops this register being affected by sysregs_loaded_on_cpu,
>>> so we can provide 32 bit accessors that always use the in-memory copy.
>>> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
>>> index 75b1925763f1..57116cf3a1a5 100644
>>> --- a/arch/arm64/kvm/hyp/sysreg-sr.c
>>> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
>>> @@ -133,7 +132,6 @@ static void __hyp_text
>>> __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
>>> isb();
>>> }
>>>
>>> - write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
>>
>> If we don't need to save/restore it, we can also drop its presence
>> in the sys_regs array.
So even user-space accesses read from the hardware register? Fine by me.
>> It strikes me that we don't even have a trap handler for this sysreg,
>> whether it is 32 or 64bit... That's a bit unfortunate, to say the
>> least...
>
> Ah, no. the sucker is hidden away in "generic_v8"...
That thing is A7/A15 (and then user-ABI) legacy right?
I was looking at ripping all that out when I ran over these. RFC grade, known not to bisect:
http://www.linux-arm.org/git?p=linux-jm.git;a=shortlog;h=refs/heads/kvm_kill_target_table/v0
Thanks,
James
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^ permalink raw reply
* RE: [PATCH 2/2] firmware: smccc: Add ARCH_SOC_ID support
From: Jose Marinho @ 2020-05-28 13:05 UTC (permalink / raw)
To: Arnd Bergmann, Sudeep Holla
Cc: Mark Rutland, Francois Ozog, Lorenzo Pieralisi,
Greg Kroah-Hartman, linux-kernel@vger.kernel.org,
Harb Abdulhamid (harb@amperecomputing.com), nd, Will Deacon,
Linux ARM
In-Reply-To: <CAK8P3a1+jjgOyJcRQm60RULjwtvWzvYK1QwrjOX_aRAbDGKuJg@mail.gmail.com>
> On Sat, May 23, 2020 at 7:27 PM Sudeep Holla <sudeep.holla@arm.com>
> wrote:
> > On Fri, May 22, 2020 at 08:41:59PM +0200, Arnd Bergmann wrote:
> > > On Fri, May 22, 2020 at 6:54 PM Sudeep Holla <sudeep.holla@arm.com>
> wrote:
> >
> > > jep106:5678 (the IMP_DEF_SOC_ID field in my example) would probably
> > > be sufficient to not conflict with a another soc_device driver, but
> > > is quite likely to clash with an ID used by another manufacturer.
> > >
> >
> > IIUC, you are fine with "jep106:1234:5678" where 1234 is jep106
> manufacture
> > id code and 5678 is soc_id as it may avoid all the conflicts across
> > the manufacture namespaces.
>
> I think either jep106:5678 or jep106:1234:5678 (or some variation with
> different field separators if you prefer) would be fine here.
>
> > > jep106:1234 (the manufacturer ID) in turn seems too broad from
> > > the soc_id field, as that would include every chip made by one
> > > company.
> > >
> >
> > I understand, and IIUC you prefer this to be embedded with soc_id
> > especially to avoid namespace conflicts which makes sense.
> >
> > Thanks for all the discussion and valuable inputs. I am now bit nervous
> > to add SoC info from SMCCC ARCH_SOC_ID to sysfs yet as we need more
> info
> > especially "machine" and "serial_number" for elsewhere(OEM firmware
> mostly
> > from DT or ACPI).
>
> I probably wouldn't mix those in with the same driver. If machine and
> serial_number have no smccc interface, then they should be left out,
> but there could be a separate soc_device that gets that information
> by other means, usually using one of the existing hardware id register
> drivers.
>
> > TBH, the mix might be bit of a mess as there are soc drivers that rely
> > on DT completely today. Anyways, this SOC_ID can be added as library that
> > can be used by a *generic* soc driver once we define a standard way to
> > fetch other information("machine" and "serial_number"). I am happy to
> > get suggestions on that front especially from you and Francois as you
> > have got some context already.
>
> Well, I suppose we could have the entire data from the smccc interface
> in a central place somewhere, such as (to stay with my example)
> "1234:5678:9abcdef0" in an attribute of any soc_device driver that
> adds a call to a library function for the jep106 ID, or possibly in
> /sys/firmware or even a field added to /proc/cpuinfo.
I think this is a great way to expose the SoC ID info. It's important to have the SoC ID as a whole in a sysfs (or somewhere where it's easy to obtain and parse from user-space).
The information provided by SoC ID should be listed in this form jep106:1234:5678, that is jep106:<manufacturer ID>:<SoC ID> .
Regards,
Jose
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^ permalink raw reply
* Re: [PATCH v8 00/13] add ecspi ERR009165 for i.mx6/7 soc family
From: Mark Brown @ 2020-05-28 13:07 UTC (permalink / raw)
To: catalin.marinas, vkoul, mark.rutland, will.deacon, s.hauer,
festevam, dan.j.williams, Robin Gong, shawnguo, u.kleine-koenig,
martin.fuzzey, robh+dt
Cc: devicetree, linux-kernel, linux-spi, linux-imx, kernel,
linux-arm-kernel
In-Reply-To: <1590006865-20900-1-git-send-email-yibin.gong@nxp.com>
On Thu, 21 May 2020 04:34:12 +0800, Robin Gong wrote:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/1] spi: imx: fallback to PIO if dma setup failure
commit: bcd8e7761ec9c128b9102b0833d9c7052ae2dbcf
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
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^ permalink raw reply
* Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi iova address
From: Auger Eric @ 2020-05-28 13:11 UTC (permalink / raw)
To: Shameerali Kolothum Thodi, Jean-Philippe Brucker
Cc: Robin Murphy, Joerg Roedel, iommu@lists.linux-foundation.org,
Linux Kernel Mailing List, Alex Williamson, Srinath Mannam,
BCM Kernel Feedback, Will Deacon, Linux ARM
In-Reply-To: <f62731300adc4def97418f0bc2f5010e@huawei.com>
Hi Shameer,
On 5/28/20 2:09 PM, Shameerali Kolothum Thodi wrote:
>
>
>> -----Original Message-----
>> From: Auger Eric [mailto:eric.auger@redhat.com]
>> Sent: 28 May 2020 12:48
>> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>;
>> Jean-Philippe Brucker <jean-philippe@linaro.org>
>> Cc: Robin Murphy <robin.murphy@arm.com>; Joerg Roedel
>> <joro@8bytes.org>; iommu@lists.linux-foundation.org; Linux Kernel Mailing
>> List <linux-kernel@vger.kernel.org>; Alex Williamson
>> <alex.williamson@redhat.com>; Srinath Mannam
>> <srinath.mannam@broadcom.com>; BCM Kernel Feedback
>> <bcm-kernel-feedback-list@broadcom.com>; Will Deacon <will@kernel.org>;
>> Linux ARM <linux-arm-kernel@lists.infradead.org>
>> Subject: Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set msi
>> iova address
>>
>>
>>
>> On 5/28/20 11:15 AM, Shameerali Kolothum Thodi wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Auger Eric [mailto:eric.auger@redhat.com]
>>>> Sent: 28 May 2020 09:54
>>>> To: Jean-Philippe Brucker <jean-philippe@linaro.org>
>>>> Cc: Will Deacon <will@kernel.org>; Joerg Roedel <joro@8bytes.org>;
>>>> iommu@lists.linux-foundation.org; Shameerali Kolothum Thodi
>>>> <shameerali.kolothum.thodi@huawei.com>; Linux Kernel Mailing List
>>>> <linux-kernel@vger.kernel.org>; Alex Williamson
>>>> <alex.williamson@redhat.com>; Srinath Mannam
>>>> <srinath.mannam@broadcom.com>; BCM Kernel Feedback
>>>> <bcm-kernel-feedback-list@broadcom.com>; Robin Murphy
>>>> <robin.murphy@arm.com>; Linux ARM
>> <linux-arm-kernel@lists.infradead.org>
>>>> Subject: Re: [RFC PATCH] iommu/arm-smmu: Add module parameter to set
>> msi
>>>> iova address
>>>>
>>>> Hi,
>>>>
>>>> On 5/28/20 10:38 AM, Jean-Philippe Brucker wrote:
>>>>> [+ Shameer]
>>>>>
>>>>> On Thu, May 28, 2020 at 09:43:46AM +0200, Auger Eric wrote:
>>>>>> Hi,
>>>>>>
>>>>>> On 5/28/20 9:23 AM, Jean-Philippe Brucker wrote:
>>>>>>> On Thu, May 28, 2020 at 10:45:14AM +0530, Srinath Mannam wrote:
>>>>>>>> On Wed, May 27, 2020 at 11:00 PM Robin Murphy
>>>> <robin.murphy@arm.com> wrote:
>>>>>>>>>
>>>>>>>> Thanks Robin for your quick response.
>>>>>>>>> On 2020-05-27 17:03, Srinath Mannam wrote:
>>>>>>>>>> This patch gives the provision to change default value of MSI IOVA
>> base
>>>>>>>>>> to platform's suitable IOVA using module parameter. The present
>>>>>>>>>> hardcoded MSI IOVA base may not be the accessible IOVA ranges of
>>>> platform.
>>>>>>>>>
>>>>>>>>> That in itself doesn't seem entirely unreasonable; IIRC the current
>>>>>>>>> address is just an arbitrary choice to fit nicely into Qemu's memory
>>>>>>>>> map, and there was always the possibility that it wouldn't suit
>>>> everything.
>>>>>>>>>
>>>>>>>>>> Since commit aadad097cd46 ("iommu/dma: Reserve IOVA for PCIe
>>>> inaccessible
>>>>>>>>>> DMA address"), inaccessible IOVA address ranges parsed from
>>>> dma-ranges
>>>>>>>>>> property are reserved.
>>>>>>>
>>>>>>> I don't understand why we only reserve the PCIe windows for DMA
>>>> domains.
>>>>>>> Shouldn't VFIO also prevent userspace from mapping them?
>>>>>>
>>>>>> VFIO prevents userspace from DMA mapping iovas within reserved
>> regions:
>>>>>> 9b77e5c79840 vfio/type1: check dma map request is within a valid iova
>>>> range
>>>>>
>>>>> Right but I was asking specifically about the IOVA reservation introduced
>>>>> by commit aadad097cd46. They are not registered as reserved regions
>> within
>>>>> the IOMMU core, they are only taken into account by dma-iommu.c when
>>>>> creating a DMA domain. As VFIO uses UNMANAGED domains, it isn't
>> aware
>>>> of
>>>>> those regions and they won't be seen by vfio_iommu_resv_exclude().
>>>>>
>>>>> It looks like the PCIe regions used to be common until cd2c9fcf5c66
>>>>> ("iommu/dma: Move PCI window region reservation back into dma specific
>>>>> path.") But I couldn't find the justification for this commit.
>>>>
>>>> Yes I noticed that as well when debugging the above mentioned case
>>>> before and after cd2c9fcf5c66. I do not remember about the rationale of
>>>> removing the DMA host brige windows from the resv regions. Did it break
>>>> a legacy case?
>>>>>
>>>
>>> I think yes. And going through the ML discussions, this was done so because
>> with the
>>> " vfio/type1: Add support for valid iova list management" series you reported
>>> an issue with Seattle platform. See the full discussion here,
>>>
>>> https://lore.kernel.org/patchwork/patch/889012/
>>
>> Hey thank you for reminding me of the Seattle case :-) Now I also recall
>> that, if I am not wrong, this also caused some trouble on some x86
>> platforms as well, reported by Alex?
>
> True, Alex reported that VT-d RMRR ranges were causing issues[1] as well.
> And then you came with IOMMU_RESV_DIRECT_RELAXABLE regions
> to exclude those[2]
I thought we also had the case of RESERVED regions but anyway.
>
> Maybe we should still report PCI
>> host bridge windows in the reserved regions, if possible/feasible tag
>> them differently from other reserved regions and not reject any VFIO
>> DMA_MAP colliding with them?
>
> I guess that is possible. But current interface is to report the regions that are safe
> from a IOMMU transaction point of view and I am not sure PCI window regions
> comes under that.
yes only the sysfs interface could expose them at the moment.
Thanks
Eric
>
> Thanks,
> Shameer
>
> 1. https://lkml.org/lkml/2018/6/5/760
> 2. https://lore.kernel.org/patchwork/cover/1083072/
>
>> Thanks
>>
>> Eric
>>>
>>> Cheers,
>>> Shameer
>>>
>>>>> The thing is, if VFIO isn't aware of the reserved PCIe windows, then
>>>>> allowing VFIO or userspace to choose MSI_IOVA_BASE won't solve the
>>>> problem
>>>>> reported by Srinath, because they could well choose an IOVA within the
>>>>> PCIe window...
>>>> I agree with you
>>>>
>>>> Thanks
>>>>
>>>> Eric
>>>>>
>>>>> Thanks,
>>>>> Jean
>>>>>
>>>>>> but it does not prevent the SW MSI region chosen by the kernel from
>>>>>> colliding with other reserved regions (esp. PCIe host bridge windows).
>>>>>>
>>>>>> If they were
>>>>>>> part of the common reserved regions then we could have VFIO choose a
>>>>>>> SW_MSI region among the remaining free space.
>>>>>> As Robin said this was the initial chosen approach
>>>>>> [PATCH 10/10] vfio: allow the user to register reserved iova range for
>>>>>> MSI mapping
>>>>>> https://patchwork.kernel.org/patch/8121641/
>>>>>>
>>>>>> Some additional background about why the static SW MSI region chosen
>> by
>>>>>> the kernel was later chosen:
>>>>>> Summary of LPC guest MSI discussion in Santa Fe (was: Re: [RFC 0/8] KVM
>>>>>> PCIe/MSI passthrough on ARM/ARM64 (Alt II))
>>>>>>
>>>>
>> https://lists.linuxfoundation.org/pipermail/iommu/2016-November/019060.ht
>>>> ml
>>>>>>
>>>>>> Thanks
>>>>>>
>>>>>> Eric
>>>>>>
>>>>>>
>>>>>> It would just need a
>>>>>>> different way of asking the IOMMU driver if a SW_MSI is needed, for
>>>>>>> example with a domain attribute.
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Jean
>>>>>>>
>>>>>>>>>
>>>>>>>>> That, however, doesn't seem to fit here; iommu-dma maps MSI
>>>> doorbells
>>>>>>>>> dynamically, so they aren't affected by reserved regions any more
>> than
>>>>>>>>> regular DMA pages are. In fact, it explicitly ignores the software MSI
>>>>>>>>> region, since as the comment says, it *is* the software that manages
>>>> those.
>>>>>>>> Yes you are right, we don't see any issues with kernel drivers(PCI EP)
>>>> because
>>>>>>>> MSI IOVA allocated dynamically by honouring reserved regions same as
>>>> DMA pages.
>>>>>>>>>
>>>>>>>>> The MSI_IOVA_BASE region exists for VFIO, precisely because in that
>>>> case
>>>>>>>>> the kernel *doesn't* control the address space, but still needs some
>> way
>>>>>>>>> to steal a bit of it for MSIs that the guest doesn't necessarily know
>>>>>>>>> about, and give userspace a fighting chance of knowing what it's
>> taken.
>>>>>>>>> I think at the time we discussed the idea of adding something to the
>>>>>>>>> VFIO uapi such that userspace could move this around if it wanted or
>>>>>>>>> needed to, but decided we could live without that initially. Perhaps
>> now
>>>>>>>>> the time has come?
>>>>>>>> Yes, we see issues only with user-space drivers(DPDK) in which
>>>> MSI_IOVA_BASE
>>>>>>>> region is considered to map MSI registers. This patch helps us to fix the
>>>> issue.
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Srinath.
>>>>>>>>>
>>>>>>>>> Robin.
>>>>>>>>>
>>>>>>>>>> If any platform has the limitaion to access default MSI IOVA, then it
>> can
>>>>>>>>>> be changed using "arm-smmu.msi_iova_base=0xa0000000"
>> command
>>>> line argument.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
>>>>>>>>>> ---
>>>>>>>>>> drivers/iommu/arm-smmu.c | 5 ++++-
>>>>>>>>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/iommu/arm-smmu.c
>> b/drivers/iommu/arm-smmu.c
>>>>>>>>>> index 4f1a350..5e59c9d 100644
>>>>>>>>>> --- a/drivers/iommu/arm-smmu.c
>>>>>>>>>> +++ b/drivers/iommu/arm-smmu.c
>>>>>>>>>> @@ -72,6 +72,9 @@ static bool disable_bypass =
>>>>>>>>>> module_param(disable_bypass, bool, S_IRUGO);
>>>>>>>>>> MODULE_PARM_DESC(disable_bypass,
>>>>>>>>>> "Disable bypass streams such that incoming transactions
>> from
>>>> devices that are not attached to an iommu domain will report an abort back
>> to
>>>> the device and will not be allowed to pass through the SMMU.");
>>>>>>>>>> +static unsigned long msi_iova_base = MSI_IOVA_BASE;
>>>>>>>>>> +module_param(msi_iova_base, ulong, S_IRUGO);
>>>>>>>>>> +MODULE_PARM_DESC(msi_iova_base, "msi iova base address.");
>>>>>>>>>>
>>>>>>>>>> struct arm_smmu_s2cr {
>>>>>>>>>> struct iommu_group *group;
>>>>>>>>>> @@ -1566,7 +1569,7 @@ static void
>>>> arm_smmu_get_resv_regions(struct device *dev,
>>>>>>>>>> struct iommu_resv_region *region;
>>>>>>>>>> int prot = IOMMU_WRITE | IOMMU_NOEXEC |
>>>> IOMMU_MMIO;
>>>>>>>>>>
>>>>>>>>>> - region = iommu_alloc_resv_region(MSI_IOVA_BASE,
>>>> MSI_IOVA_LENGTH,
>>>>>>>>>> + region = iommu_alloc_resv_region(msi_iova_base,
>>>> MSI_IOVA_LENGTH,
>>>>>>>>>> prot,
>>>> IOMMU_RESV_SW_MSI);
>>>>>>>>>> if (!region)
>>>>>>>>>> return;
>>>>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> linux-arm-kernel mailing list
>>>>>>> linux-arm-kernel@lists.infradead.org
>>>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>>>>
>>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> linux-arm-kernel mailing list
>>>>> linux-arm-kernel@lists.infradead.org
>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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^ permalink raw reply
* [PATCH] KVM: arm64: Check advertised Stage-2 page size capability
From: Marc Zyngier @ 2020-05-28 13:12 UTC (permalink / raw)
To: Will Deacon
Cc: kernel-team, kvm, Suzuki K Poulose, Catalin Marinas, James Morse,
linux-arm-kernel, alexandru.elisei, kvmarm, Julien Thierry
With ARMv8.5-GTG, the hardware (or more likely a hypervisor) can
advertise the supported Stage-2 page sizes.
Let's check this at boot time.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
Hi Will,
Can you please take this patch via the arm64 tree, and apply it
to the for-next/cpufeature branch?
Thanks,
M.
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/sysreg.h | 3 +++
arch/arm64/kernel/cpufeature.c | 18 +++++++++++++++
arch/arm64/kvm/reset.c | 37 +++++++++++++++++++++++++++++--
virt/kvm/arm/arm.c | 4 +---
5 files changed, 58 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 32c8a675e5a4..7dd8fefa6aec 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -670,7 +670,7 @@ static inline int kvm_arm_have_ssbd(void)
void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
-void kvm_set_ipa_limit(void);
+int kvm_set_ipa_limit(void);
#define __KVM_HAVE_ARCH_VM_ALLOC
struct kvm *kvm_arch_alloc_vm(void);
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index fa9d02ca4b25..efe368ee4996 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -703,6 +703,9 @@
#define ID_AA64ZFR0_SVEVER_SVE2 0x1
/* id_aa64mmfr0 */
+#define ID_AA64MMFR0_TGRAN4_2_SHIFT 40
+#define ID_AA64MMFR0_TGRAN64_2_SHIFT 36
+#define ID_AA64MMFR0_TGRAN16_2_SHIFT 32
#define ID_AA64MMFR0_TGRAN4_SHIFT 28
#define ID_AA64MMFR0_TGRAN64_SHIFT 24
#define ID_AA64MMFR0_TGRAN16_SHIFT 20
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7437b8c19528..b3202a99e559 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -267,6 +267,24 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
};
static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
+ /*
+ * Page size not being supported at Stage-2 is not fatal. You
+ * just give up KVM if PAGE_SIZE isn't supported there. Go fix
+ * your favourite nesting hypervisor.
+ *
+ * There is a small corner case where the hypervisor explicitly
+ * advertises a given granule size at Stage-2 (value 2) on some
+ * vCPUs, and uses the fallback to Stage-1 (value 0) for other
+ * vCPUs. Although this is not forbidden by the architecture, it
+ * indicates that the hypervisor is being silly (or buggy).
+ *
+ * We make no effort to cope with this and pretend that if these
+ * fields are inconsistent across vCPUs, then it isn't worth
+ * trying to bring KVM up.
+ */
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
/*
* We already refuse to boot CPUs that don't support our configured
* page size, so we can only detect mismatches for a page size other
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index d8800ef4f42d..70cd7bcca433 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -337,14 +337,45 @@ u32 get_kvm_ipa_limit(void)
return kvm_ipa_limit;
}
-void kvm_set_ipa_limit(void)
+int kvm_set_ipa_limit(void)
{
- unsigned int ipa_max, pa_max, va_max, parange;
+ unsigned int ipa_max, pa_max, va_max, parange, tgran_2;
u64 mmfr0;
mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
parange = cpuid_feature_extract_unsigned_field(mmfr0,
ID_AA64MMFR0_PARANGE_SHIFT);
+
+ /*
+ * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
+ * Stage-2. If not, things will stop very quickly.
+ */
+ switch (PAGE_SIZE) {
+ default:
+ case SZ_4K:
+ tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT;
+ break;
+ case SZ_16K:
+ tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT;
+ break;
+ case SZ_64K:
+ tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT;
+ break;
+ }
+
+ switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {
+ default:
+ case 1:
+ kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
+ return -EINVAL;
+ case 0:
+ kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
+ break;
+ case 2:
+ kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
+ break;
+ }
+
pa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
/* Clamp the IPA limit to the PA size supported by the kernel */
@@ -378,6 +409,8 @@ void kvm_set_ipa_limit(void)
"KVM IPA limit (%d bit) is smaller than default size\n", ipa_max);
kvm_ipa_limit = ipa_max;
kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit);
+
+ return 0;
}
/*
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
index 48d0ec44ad77..53b3ba9173ba 100644
--- a/virt/kvm/arm/arm.c
+++ b/virt/kvm/arm/arm.c
@@ -1387,9 +1387,7 @@ static inline void hyp_cpu_pm_exit(void)
static int init_common_resources(void)
{
- kvm_set_ipa_limit();
-
- return 0;
+ return kvm_set_ipa_limit();
}
static int init_subsystems(void)
--
2.26.2
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* [PATCH] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
From: Marc Zyngier @ 2020-05-28 13:12 UTC (permalink / raw)
To: Will Deacon
Cc: kernel-team, kvm, Suzuki K Poulose, Catalin Marinas, James Morse,
linux-arm-kernel, alexandru.elisei, kvmarm, Julien Thierry
In-Reply-To: <20200528131259.860459-1-maz@kernel.org>
Having __load_guest_stage2 in kvm_hyp.h is quickly going to trigger
a circular include problem. In order to avoid this, let's move
it to kvm_mmu.h, where it will be a better fit anyway.
In the process, drop the __hyp_text annotation, which doesn't help
as the function is marked as __always_inline.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
Hi Will,
Can you please take this patch via the arm64 tree, and apply it
to the for-next/kvm/errata branch?
Thanks,
M.
arch/arm64/include/asm/kvm_hyp.h | 18 ------------------
arch/arm64/include/asm/kvm_mmu.h | 17 +++++++++++++++++
2 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
index 238d2e049694..dcb63bf94105 100644
--- a/arch/arm64/include/asm/kvm_hyp.h
+++ b/arch/arm64/include/asm/kvm_hyp.h
@@ -10,7 +10,6 @@
#include <linux/compiler.h>
#include <linux/kvm_host.h>
#include <asm/alternative.h>
-#include <asm/kvm_mmu.h>
#include <asm/sysreg.h>
#define __hyp_text __section(.hyp.text) notrace
@@ -88,22 +87,5 @@ void deactivate_traps_vhe_put(void);
u64 __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host_ctxt);
void __noreturn __hyp_do_panic(unsigned long, ...);
-/*
- * Must be called from hyp code running at EL2 with an updated VTTBR
- * and interrupts disabled.
- */
-static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm)
-{
- write_sysreg(kvm->arch.vtcr, vtcr_el2);
- write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);
-
- /*
- * ARM errata 1165522 and 1530923 require the actual execution of the
- * above before we can switch to the EL1/EL0 translation regime used by
- * the guest.
- */
- asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
-}
-
#endif /* __ARM64_KVM_HYP_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 30b0e8d6b895..1abe58bbbf13 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -604,5 +604,22 @@ static __always_inline u64 kvm_get_vttbr(struct kvm *kvm)
return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
}
+/*
+ * Must be called from hyp code running at EL2 with an updated VTTBR
+ * and interrupts disabled.
+ */
+static __always_inline void __load_guest_stage2(struct kvm *kvm)
+{
+ write_sysreg(kvm->arch.vtcr, vtcr_el2);
+ write_sysreg(kvm_get_vttbr(kvm), vttbr_el2);
+
+ /*
+ * ARM errata 1165522 and 1530923 require the actual execution of the
+ * above before we can switch to the EL1/EL0 translation regime used by
+ * the guest.
+ */
+ asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
+}
+
#endif /* __ASSEMBLY__ */
#endif /* __ARM64_KVM_MMU_H__ */
--
2.26.2
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* [PATCH net-next] dt-bindings: net: rename the bindings document for MediaTek STAR MAC
From: Bartosz Golaszewski @ 2020-05-28 13:27 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Matthias Brugger
Cc: devicetree, Stephane Le Provost, Bartosz Golaszewski, netdev,
linux-kernel, Fabien Parent, linux-mediatek, Andrew Perepech,
Pedro Tsai, linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The driver itself was renamed before getting merged into mainline, but
the binding document kept the old name. This makes both names consistent.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
.../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (100%)
diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
similarity index 100%
rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
--
2.26.1
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:29 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
linux-kernel, Mark Lee, Fabien Parent, Pedro Tsai, linux-mediatek,
Andrew Perepech, John Crispin, Matthias Brugger, Jakub Kicinski,
David S . Miller, linux-arm-kernel
In-Reply-To: <20200528123459.21168-2-brgl@bgdev.pl>
[-- Attachment #1.1: Type: text/plain, Size: 200 bytes --]
On Thu, May 28, 2020 at 02:34:58PM +0200, Bartosz Golaszewski wrote:
> This adds three new macros for simple bit operations: set_bits,
> clear_bits and test_bits.
Why macros and not static inlines?
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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