* [PATCH 7/9] KVM: mmu: Move mmu lock/unlock to arch code for clear dirty log
From: Vipin Sharma @ 2023-04-21 16:53 UTC (permalink / raw)
To: maz, oliver.upton, james.morse, suzuki.poulose, yuzenghui,
catalin.marinas, will, chenhuacai, aleksandar.qemu.devel,
tsbogend, anup, atishp, paul.walmsley, palmer, aou, seanjc,
pbonzini, dmatlack, ricarkol
Cc: linux-arm-kernel, kvmarm, linux-mips, kvm-riscv, linux-riscv,
linux-kselftest, kvm, linux-kernel, Vipin Sharma
In-Reply-To: <20230421165305.804301-1-vipinsh@google.com>
Move mmu_lock lock and unlock calls from common code in
kvm_clear_dirty_log_protect() to arch specific code in
kvm_arch_mmu_enable_log_dirty_pt_masked(). None of the other code inside
the for loop of kvm_arch_mmu_enable_log_dirty_pt_masked() needs mmu_lock
exclusivity apart from the arch specific API call.
Future commits will change clear dirty log operations under mmu read
lock instead of write lock for ARM and, potentially, x86 architectures.
No functional changes intended.
Signed-off-by: Vipin Sharma <vipinsh@google.com>
---
arch/arm64/kvm/mmu.c | 2 ++
arch/mips/kvm/mmu.c | 2 ++
arch/riscv/kvm/mmu.c | 2 ++
arch/x86/kvm/mmu/mmu.c | 3 +++
virt/kvm/dirty_ring.c | 2 --
virt/kvm/kvm_main.c | 4 ----
6 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 7113587222ff..dc1c9059604e 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1002,7 +1002,9 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
struct kvm_memory_slot *slot,
gfn_t gfn_offset, unsigned long mask)
{
+ write_lock(&kvm->mmu_lock);
kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
+ write_unlock(&kvm->mmu_lock);
}
static void kvm_send_hwpoison_signal(unsigned long address, short lsb)
diff --git a/arch/mips/kvm/mmu.c b/arch/mips/kvm/mmu.c
index e8c08988ed37..b8d4723d197e 100644
--- a/arch/mips/kvm/mmu.c
+++ b/arch/mips/kvm/mmu.c
@@ -415,11 +415,13 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
struct kvm_memory_slot *slot,
gfn_t gfn_offset, unsigned long mask)
{
+ spin_lock(&kvm->mmu_lock);
gfn_t base_gfn = slot->base_gfn + gfn_offset;
gfn_t start = base_gfn + __ffs(mask);
gfn_t end = base_gfn + __fls(mask);
kvm_mips_mkclean_gpa_pt(kvm, start, end);
+ spin_unlock(&kvm->mmu_lock);
}
/*
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index 78211aed36fa..425fa11dcf9c 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -395,11 +395,13 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
gfn_t gfn_offset,
unsigned long mask)
{
+ spin_lock(&kvm->mmu_lock);
phys_addr_t base_gfn = slot->base_gfn + gfn_offset;
phys_addr_t start = (base_gfn + __ffs(mask)) << PAGE_SHIFT;
phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
gstage_wp_range(kvm, start, end);
+ spin_unlock(&kvm->mmu_lock);
}
void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 144c5a01cd77..f1dc549b01cb 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -1367,6 +1367,7 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
struct kvm_memory_slot *slot,
gfn_t gfn_offset, unsigned long mask)
{
+ write_lock(&kvm->mmu_lock);
/*
* Huge pages are NOT write protected when we start dirty logging in
* initially-all-set mode; must write protect them here so that they
@@ -1397,6 +1398,8 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
else
kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
+
+ write_unlock(&kvm->mmu_lock);
}
int kvm_cpu_dirty_log_size(void)
diff --git a/virt/kvm/dirty_ring.c b/virt/kvm/dirty_ring.c
index c1cd7dfe4a90..d894c58d2152 100644
--- a/virt/kvm/dirty_ring.c
+++ b/virt/kvm/dirty_ring.c
@@ -66,9 +66,7 @@ static void kvm_reset_dirty_gfn(struct kvm *kvm, u32 slot, u64 offset, u64 mask)
if (!memslot || (offset + __fls(mask)) >= memslot->npages)
return;
- KVM_MMU_LOCK(kvm);
kvm_arch_mmu_enable_log_dirty_pt_masked(kvm, memslot, offset, mask);
- KVM_MMU_UNLOCK(kvm);
}
int kvm_dirty_ring_alloc(struct kvm_dirty_ring *ring, int index, u32 size)
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index f40b72eb0e7b..378c40e958b6 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -2157,7 +2157,6 @@ static int kvm_get_dirty_log_protect(struct kvm *kvm, struct kvm_dirty_log *log)
dirty_bitmap_buffer = kvm_second_dirty_bitmap(memslot);
memset(dirty_bitmap_buffer, 0, n);
- KVM_MMU_LOCK(kvm);
for (i = 0; i < n / sizeof(long); i++) {
unsigned long mask;
gfn_t offset;
@@ -2173,7 +2172,6 @@ static int kvm_get_dirty_log_protect(struct kvm *kvm, struct kvm_dirty_log *log)
kvm_arch_mmu_enable_log_dirty_pt_masked(kvm, memslot,
offset, mask);
}
- KVM_MMU_UNLOCK(kvm);
}
if (flush)
@@ -2268,7 +2266,6 @@ static int kvm_clear_dirty_log_protect(struct kvm *kvm,
if (copy_from_user(dirty_bitmap_buffer, log->dirty_bitmap, n))
return -EFAULT;
- KVM_MMU_LOCK(kvm);
for (offset = log->first_page, i = offset / BITS_PER_LONG,
n = DIV_ROUND_UP(log->num_pages, BITS_PER_LONG); n--;
i++, offset += BITS_PER_LONG) {
@@ -2291,7 +2288,6 @@ static int kvm_clear_dirty_log_protect(struct kvm *kvm,
offset, mask);
}
}
- KVM_MMU_UNLOCK(kvm);
if (flush)
kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
--
2.40.0.634.g4ca3ef3211-goog
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* [PATCH 6/9] KVM: arm64: Correct the kvm_pgtable_stage2_flush() documentation
From: Vipin Sharma @ 2023-04-21 16:53 UTC (permalink / raw)
To: maz, oliver.upton, james.morse, suzuki.poulose, yuzenghui,
catalin.marinas, will, chenhuacai, aleksandar.qemu.devel,
tsbogend, anup, atishp, paul.walmsley, palmer, aou, seanjc,
pbonzini, dmatlack, ricarkol
Cc: linux-arm-kernel, kvmarm, linux-mips, kvm-riscv, linux-riscv,
linux-kselftest, kvm, linux-kernel, Vipin Sharma
In-Reply-To: <20230421165305.804301-1-vipinsh@google.com>
Remove _range suffix from kvm_pgtable_stage2_flush_range which is used
in documentation of kvm_pgtable_stage2_flush(). There is no function
named kvm_pgtable_stage2_flush_range().
Fixes: 93c66b40d728 ("KVM: arm64: Add support for stage-2 cache flushing in generic page-table")
Signed-off-by: Vipin Sharma <vipinsh@google.com>
---
arch/arm64/include/asm/kvm_pgtable.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h
index 4cd6762bda80..4cd62506c198 100644
--- a/arch/arm64/include/asm/kvm_pgtable.h
+++ b/arch/arm64/include/asm/kvm_pgtable.h
@@ -605,9 +605,8 @@ int kvm_pgtable_stage2_relax_perms(struct kvm_pgtable *pgt, u64 addr,
bool kvm_pgtable_stage2_is_young(struct kvm_pgtable *pgt, u64 addr);
/**
- * kvm_pgtable_stage2_flush_range() - Clean and invalidate data cache to Point
- * of Coherency for guest stage-2 address
- * range.
+ * kvm_pgtable_stage2_flush() - Clean and invalidate data cache to Point of
+ * Coherency for guest stage-2 address range.
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
* @addr: Intermediate physical address from which to flush.
* @size: Size of the range.
--
2.40.0.634.g4ca3ef3211-goog
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* Re: [RFC PATCH net-next 08/22] net: dsa: mt7530: change p{5,6}_interface to p{5,6}_configured
From: Daniel Golle @ 2023-04-21 17:28 UTC (permalink / raw)
To: arinc9.unal
Cc: Sean Wang, Landen Chao, DENG Qingfang, Andrew Lunn,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King,
Arınç ÜNAL, Richard van Schagen,
Richard van Schagen, Frank Wunderlich, erkin.bozoglu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20230421143648.87889-9-arinc.unal@arinc9.com>
On Fri, Apr 21, 2023 at 05:36:34PM +0300, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> The idea of p5_interface and p6_interface pointers is to prevent
> mt753x_mac_config() from running twice for MT7531, as it's already run with
> mt753x_cpu_port_enable() from mt7531_setup_common(), if the port is used as
> a CPU port.
>
> Change p5_interface and p6_interface to p5_configured and p6_configured.
> Make them boolean.
>
> Do not set them for any other reason.
>
> The priv->p5_intf_sel check is useless as in this code path, it will always
> be P5_INTF_SEL_GMAC5.
>
> There was also no need to set priv->p5_interface and priv->p6_interface to
> PHY_INTERFACE_MODE_NA on mt7530_setup() and mt7531_setup() as they would
> already be set to that when "priv" is allocated. The pointers were of the
> phy_interface_t enumeration type, and the first element of the enum is
> PHY_INTERFACE_MODE_NA. There was nothing in between that would change this
> beforehand.
>
> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
NACK. This assumes that a user port is configured exactly once.
However, interface mode may change because of mode-changing PHYs (e.g.
often using Cisco SGMII for 10M/100M/1000M but using 2500Base-X for
2500M, ie. depending on actual link speed).
Also when using SFP modules (which can be hotplugged) the interface
mode may change after initially setting up the driver, e.g. when SFP
driver is loaded or a module is plugged or replaced.
> ---
> drivers/net/dsa/mt7530.c | 19 ++++---------------
> drivers/net/dsa/mt7530.h | 10 ++++++----
> 2 files changed, 10 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index bac2388319a3..2f670e512415 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -2237,8 +2237,6 @@ mt7530_setup(struct dsa_switch *ds)
> val |= MHWTRAP_MANUAL;
> mt7530_write(priv, MT7530_MHWTRAP, val);
>
> - priv->p6_interface = PHY_INTERFACE_MODE_NA;
> -
> /* Enable and reset MIB counters */
> mt7530_mib_reset(ds);
>
> @@ -2460,10 +2458,6 @@ mt7531_setup(struct dsa_switch *ds)
> mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
> MT7531_GPIO0_INTERRUPT);
>
> - /* Let phylink decide the interface later. */
> - priv->p5_interface = PHY_INTERFACE_MODE_NA;
> - priv->p6_interface = PHY_INTERFACE_MODE_NA;
> -
> /* Enable PHY core PLL, since phy_device has not yet been created
> * provided for phy_[read,write]_mmd_indirect is called, we provide
> * our own mt7531_ind_mmd_phy_[read,write] to complete this
> @@ -2733,25 +2727,20 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> goto unsupported;
> break;
> case 5: /* Port 5, can be used as a CPU port. */
> - if (priv->p5_interface == state->interface)
> + if (priv->p5_configured)
> break;
>
> if (mt753x_mac_config(ds, port, mode, state) < 0)
> goto unsupported;
> -
> - if (priv->p5_intf_sel != P5_DISABLED)
> - priv->p5_interface = state->interface;
> break;
> case 6: /* Port 6, can be used as a CPU port. */
> - if (priv->p6_interface == state->interface)
> + if (priv->p6_configured)
> break;
>
> mt753x_pad_setup(ds, state);
>
> if (mt753x_mac_config(ds, port, mode, state) < 0)
> goto unsupported;
> -
> - priv->p6_interface = state->interface;
> break;
> default:
> unsupported:
> @@ -2859,12 +2848,12 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
> else
> interface = PHY_INTERFACE_MODE_2500BASEX;
>
> - priv->p5_interface = interface;
> + priv->p5_configured = true;
> break;
> case 6:
> interface = PHY_INTERFACE_MODE_2500BASEX;
>
> - priv->p6_interface = interface;
> + priv->p6_configured = true;
> break;
> default:
> return -EINVAL;
> diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
> index f58828577520..c3a37a0f4843 100644
> --- a/drivers/net/dsa/mt7530.h
> +++ b/drivers/net/dsa/mt7530.h
> @@ -745,8 +745,10 @@ struct mt753x_info {
> * @ports: Holding the state among ports
> * @reg_mutex: The lock for protecting among process accessing
> * registers
> - * @p6_interface: Holding the current port 6 interface
> - * @p5_interface: Holding the current port 5 interface
> + * @p6_configured: Flag for distinguishing if port 6 of the MT7531 switch
> + * is already configured
> + * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch
> + * is already configured
> * @p5_intf_sel: Holding the current port 5 interface select
> * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
> * has got SGMII
> @@ -767,8 +769,8 @@ struct mt7530_priv {
> const struct mt753x_info *info;
> unsigned int id;
> bool mcm;
> - phy_interface_t p6_interface;
> - phy_interface_t p5_interface;
> + bool p6_configured;
> + bool p5_configured;
> p5_interface_select p5_intf_sel;
> bool p5_sgmii;
> u8 mirror_rx;
> --
> 2.37.2
>
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* Re: [PATCH 1/1] ufs: core: fix &hwq->cq_lock deadlock issue
From: Bart Van Assche @ 2023-04-21 17:25 UTC (permalink / raw)
To: Alice Chao, alim.akhtar, avri.altman, jejb, martin.petersen,
matthias.bgg, angelogioacchino.delregno, quic_asutoshd, quic_cang,
mani, linux-scsi, linux-kernel, linux-arm-kernel, linux-mediatek
Cc: stanley.chu, peter.wang, chun-hung.wu, powen.kao, naomi.chu,
cc.chou, chaotian.jing, jiajie.hao, tun-yu.yu, eddie.huang,
wsd_upstream
In-Reply-To: <20230421075636.24946-1-alice.chao@mediatek.com>
On 4/21/23 00:56, Alice Chao wrote:
> When ufshcd_err_handler() is executed, CQ event interrupt can enter
> waiting for the same lock. It could happened in upstream code path
> ufshcd_handle_mcq_cq_events() and also in ufs_mtk_mcq_intr(). This
> warning message will be generated when &hwq->cq_lock is used in IRQ
> context with IRQ enabled. Use ufshcd_mcq_poll_cqe_lock() with
> spin_lock_irqsave instead of spin_lock to resolve the deadlock issue.
Please add a Fixes: tag.
Thanks,
Bart.
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* Re: [PATCH] arm64: Also reset KASAN tag if page is not PG_mte_tagged
From: Peter Collingbourne @ 2023-04-21 17:20 UTC (permalink / raw)
To: Catalin Marinas
Cc: andreyknvl, Qun-wei Lin (林群崴),
Guangye Yang (杨光业), linux-mm,
Chinwen Chang (張錦文), kasan-dev, ryabinin.a.a,
linux-arm-kernel, vincenzo.frascino, will, eugenis, stable
In-Reply-To: <ZEKAZZLeqY/Vvu+z@arm.com>
On Fri, Apr 21, 2023 at 5:24 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Thu, Apr 20, 2023 at 02:09:45PM -0700, Peter Collingbourne wrote:
> > Consider the following sequence of events:
> >
> > 1) A page in a PROT_READ|PROT_WRITE VMA is faulted.
> > 2) Page migration allocates a page with the KASAN allocator,
> > causing it to receive a non-match-all tag, and uses it
> > to replace the page faulted in 1.
> > 3) The program uses mprotect() to enable PROT_MTE on the page faulted in 1.
>
> Ah, so there is no race here, it's simply because the page allocation
> for migration has a non-match-all kasan tag in page->flags.
>
> How do we handle the non-migration case with mprotect()? IIRC
> post_alloc_hook() always resets the page->flags since
> GFP_HIGHUSER_MOVABLE has the __GFP_SKIP_KASAN_UNPOISON flag.
Yes, that's how it normally works.
> > As a result of step 3, we are left with a non-match-all tag for a page
> > with tags accessible to userspace, which can lead to the same kind of
> > tag check faults that commit e74a68468062 ("arm64: Reset KASAN tag in
> > copy_highpage with HW tags only") intended to fix.
> >
> > The general invariant that we have for pages in a VMA with VM_MTE_ALLOWED
> > is that they cannot have a non-match-all tag. As a result of step 2, the
> > invariant is broken. This means that the fix in the referenced commit
> > was incomplete and we also need to reset the tag for pages without
> > PG_mte_tagged.
> >
> > Fixes: e5b8d9218951 ("arm64: mte: reset the page tag in page->flags")
>
> This commit was reverted in 20794545c146 (arm64: kasan: Revert "arm64:
> mte: reset the page tag in page->flags"). It looks a bit strange to fix
> it up.
It does seem strange but I think it is correct because that is when
the bug (resetting tag only if PG_mte_tagged) was introduced. The
revert preserved the bug because it did not account for the migration
case, which means that it didn't account for migration+mprotect
either.
> > diff --git a/arch/arm64/mm/copypage.c b/arch/arm64/mm/copypage.c
> > index 4aadcfb01754..a7bb20055ce0 100644
> > --- a/arch/arm64/mm/copypage.c
> > +++ b/arch/arm64/mm/copypage.c
> > @@ -21,9 +21,10 @@ void copy_highpage(struct page *to, struct page *from)
> >
> > copy_page(kto, kfrom);
> >
> > + if (kasan_hw_tags_enabled())
> > + page_kasan_tag_reset(to);
> > +
> > if (system_supports_mte() && page_mte_tagged(from)) {
> > - if (kasan_hw_tags_enabled())
> > - page_kasan_tag_reset(to);
>
> This should work but can we not do this at allocation time like we do
> for the source page and remove any page_kasan_tag_reset() here
> altogether?
That would be difficult because of the number of different ways that
the page can be allocated. That's why we also decided to reset it here
in commit e74a68468062.
Peter
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* Re: [PATCH] spi: bcm63xx: remove PM_SLEEP based conditional compilation
From: Florian Fainelli @ 2023-04-21 17:13 UTC (permalink / raw)
To: Dhruva Gole, Mark Brown
Cc: Vaishnav Achath, Vignesh, Apurva Nandan, linux-arm-kernel,
linux-spi, linux-kernel, Grant Likely, Tanguy Bouzeloc
In-Reply-To: <20230420121615.967487-1-d-gole@ti.com>
On 4/20/23 05:16, Dhruva Gole wrote:
> Get rid of conditional compilation based on CONFIG_PM_SLEEP because
> it may introduce build issues with certain configs where it maybe disabled
> This is because if above config is not enabled the suspend-resume
> functions are never part of the code but the bcm63xx_spi_pm_ops struct
> still inits them to non-existent suspend-resume functions.
>
> Fixes: b42dfed83d95 ("spi: add Broadcom BCM63xx SPI controller driver")
>
> Signed-off-by: Dhruva Gole <d-gole@ti.com>
> ---
> drivers/spi/spi-bcm63xx.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
> index 96633a0051b1..99395932074c 100644
> --- a/drivers/spi/spi-bcm63xx.c
> +++ b/drivers/spi/spi-bcm63xx.c
> @@ -617,7 +617,6 @@ static void bcm63xx_spi_remove(struct platform_device *pdev)
> clk_disable_unprepare(bs->clk);
> }
>
> -#ifdef CONFIG_PM_SLEEP
> static int bcm63xx_spi_suspend(struct device *dev)
Don't we need a __maybe_unused here?
--
Florian
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* Re: [PATCH 9/9] KVM: arm64: Run clear-dirty-log under MMU read lock
From: Marc Zyngier @ 2023-04-21 17:10 UTC (permalink / raw)
To: Vipin Sharma
Cc: oliver.upton, james.morse, suzuki.poulose, yuzenghui,
catalin.marinas, will, chenhuacai, aleksandar.qemu.devel,
tsbogend, anup, atishp, paul.walmsley, palmer, aou, seanjc,
pbonzini, dmatlack, ricarkol, linux-arm-kernel, kvmarm,
linux-mips, kvm-riscv, linux-riscv, linux-kselftest, kvm,
linux-kernel
In-Reply-To: <20230421165305.804301-10-vipinsh@google.com>
On Fri, 21 Apr 2023 17:53:05 +0100,
Vipin Sharma <vipinsh@google.com> wrote:
>
> Take MMU read lock for write protecting PTEs and use shared page table
> walker for clearing dirty logs.
>
> Clearing dirty logs are currently performed under MMU write locks. This
> means vCPUs write protection fault, which also take MMU read lock, will
> be blocked during this operation. This causes guest degradation and
> especially noticeable on VMs with lot of vCPUs.
>
> Taking MMU read lock will allow vCPUs to execute parallelly and reduces
> the impact on vCPUs performance.
Sure. Taking no lock whatsoever would be even better.
What I don't see is the detailed explanation that gives me the warm
feeling that this is safe and correct. Such an explanation is the
minimum condition for me to even read the patch.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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^ permalink raw reply
* [PATCH 2/9] KVM: selftests: Add optional delay between consecutive Clear-Dirty-Log calls
From: Vipin Sharma @ 2023-04-21 16:52 UTC (permalink / raw)
To: maz, oliver.upton, james.morse, suzuki.poulose, yuzenghui,
catalin.marinas, will, chenhuacai, aleksandar.qemu.devel,
tsbogend, anup, atishp, paul.walmsley, palmer, aou, seanjc,
pbonzini, dmatlack, ricarkol
Cc: linux-arm-kernel, kvmarm, linux-mips, kvm-riscv, linux-riscv,
linux-kselftest, kvm, linux-kernel, Vipin Sharma
In-Reply-To: <20230421165305.804301-1-vipinsh@google.com>
In dirty_log_perf_test, add option "-l" to wait between consecutive
Clear-Dirty-Log calls. Accept delay in milliseconds.
This allows dirty_log_perf_test to mimic real world use where after
clearing dirty memory, some time is spent in transferring memory before
making a subsequeunt Clear-Dirty-Log call.
Signed-off-by: Vipin Sharma <vipinsh@google.com>
---
.../testing/selftests/kvm/dirty_log_perf_test.c | 17 +++++++++++++++--
tools/testing/selftests/kvm/include/memstress.h | 5 +++--
tools/testing/selftests/kvm/lib/memstress.c | 10 +++++++++-
3 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/tools/testing/selftests/kvm/dirty_log_perf_test.c b/tools/testing/selftests/kvm/dirty_log_perf_test.c
index 0852a7ba42e1..338f03a4a550 100644
--- a/tools/testing/selftests/kvm/dirty_log_perf_test.c
+++ b/tools/testing/selftests/kvm/dirty_log_perf_test.c
@@ -135,6 +135,7 @@ struct test_params {
uint32_t random_seed;
bool random_access;
uint64_t clear_chunk_size;
+ int clear_chunk_wait_time_ms
};
static void run_test(enum vm_guest_mode mode, void *arg)
@@ -249,7 +250,8 @@ static void run_test(enum vm_guest_mode mode, void *arg)
clock_gettime(CLOCK_MONOTONIC, &start);
memstress_clear_dirty_log_in_chunks(vm, bitmaps, p->slots,
pages_per_slot,
- pages_per_clear);
+ pages_per_clear,
+ p->clear_chunk_wait_time_ms);
ts_diff = timespec_elapsed(start);
clear_dirty_log_total = timespec_add(clear_dirty_log_total,
ts_diff);
@@ -352,6 +354,11 @@ static void help(char *name)
" the memslot size then whole memslot is cleared in one call.\n"
" Size must be aligned to the host page size. e.g. 10M or 3G\n"
" (default: UINT64_MAX, clears whole memslot in one call)\n");
+ printf(" -l: Specify time in milliseconds to wait after Clear-Dirty-Log\n"
+ " call. This allows to mimic use cases where flow is to get\n"
+ " dirty log followed by multiple clear dirty log calls and\n"
+ " sending corresponding memory to destination (in this test\n"
+ " sending will be just idle waiting)\n");
puts("");
exit(0);
}
@@ -368,6 +375,7 @@ int main(int argc, char *argv[])
.random_seed = 1,
.write_percent = 100,
.clear_chunk_size = UINT64_MAX,
+ .clear_chunk_wait_time_ms = 0,
};
int opt;
@@ -378,7 +386,7 @@ int main(int argc, char *argv[])
guest_modes_append_default();
- while ((opt = getopt(argc, argv, "ab:c:eghi:k:m:nop:r:s:v:x:w:")) != -1) {
+ while ((opt = getopt(argc, argv, "ab:c:eghi:k:l:m:nop:r:s:v:x:w:")) != -1) {
switch (opt) {
case 'a':
p.random_access = true;
@@ -405,6 +413,11 @@ int main(int argc, char *argv[])
case 'k':
p.clear_chunk_size = parse_size(optarg);
break;
+ case 'l':
+ p.clear_chunk_wait_time_ms =
+ atoi_non_negative("Clear dirty log chunks wait time",
+ optarg);
+ break;
case 'm':
guest_modes_cmdline(optarg);
break;
diff --git a/tools/testing/selftests/kvm/include/memstress.h b/tools/testing/selftests/kvm/include/memstress.h
index 2acc93f76fc3..01fdcea80360 100644
--- a/tools/testing/selftests/kvm/include/memstress.h
+++ b/tools/testing/selftests/kvm/include/memstress.h
@@ -78,12 +78,13 @@ void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int sl
void memstress_clear_dirty_log_in_chunks(struct kvm_vm *vm,
unsigned long *bitmaps[], int slots,
uint64_t pages_per_slot,
- uint64_t pages_per_clear);
+ uint64_t pages_per_clear,
+ int wait_ms);
static inline void memstress_clear_dirty_log(struct kvm_vm *vm,
unsigned long *bitmaps[], int slots,
uint64_t pages_per_slot) {
memstress_clear_dirty_log_in_chunks(vm, bitmaps, slots, pages_per_slot,
- pages_per_slot);
+ pages_per_slot, 0);
}
unsigned long **memstress_alloc_bitmaps(int slots, uint64_t pages_per_slot);
void memstress_free_bitmaps(unsigned long *bitmaps[], int slots);
diff --git a/tools/testing/selftests/kvm/lib/memstress.c b/tools/testing/selftests/kvm/lib/memstress.c
index e0c701ab4e9a..483ecbc53a5b 100644
--- a/tools/testing/selftests/kvm/lib/memstress.c
+++ b/tools/testing/selftests/kvm/lib/memstress.c
@@ -358,10 +358,15 @@ void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int sl
void memstress_clear_dirty_log_in_chunks(struct kvm_vm *vm,
unsigned long *bitmaps[], int slots,
uint64_t pages_per_slot,
- uint64_t pages_per_clear)
+ uint64_t pages_per_clear,
+ int wait_ms)
{
int i, slot;
uint64_t from, clear_pages_count;
+ struct timespec wait = {
+ .tv_sec = wait_ms / 1000,
+ .tv_nsec = (wait_ms % 1000) * 1000000ull,
+ };
for (i = 0; i < slots; i++) {
slot = MEMSTRESS_MEM_SLOT_INDEX + i;
@@ -374,6 +379,9 @@ void memstress_clear_dirty_log_in_chunks(struct kvm_vm *vm,
kvm_vm_clear_dirty_log(vm, slot, bitmaps[i], from,
clear_pages_count);
from += clear_pages_count;
+ if (wait_ms)
+ nanosleep(&wait, NULL);
+
}
}
--
2.40.0.634.g4ca3ef3211-goog
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^ permalink raw reply related
* [PATCH 0/9] KVM: arm64: Use MMU read lock for clearing dirty logs
From: Vipin Sharma @ 2023-04-21 16:52 UTC (permalink / raw)
To: maz, oliver.upton, james.morse, suzuki.poulose, yuzenghui,
catalin.marinas, will, chenhuacai, aleksandar.qemu.devel,
tsbogend, anup, atishp, paul.walmsley, palmer, aou, seanjc,
pbonzini, dmatlack, ricarkol
Cc: linux-arm-kernel, kvmarm, linux-mips, kvm-riscv, linux-riscv,
linux-kselftest, kvm, linux-kernel, Vipin Sharma
This patch series improves guest vCPUs performances on Arm during clearing
dirty log operations by taking MMU read lock instead of MMU write lock.
vCPUs write protection faults are fixed in Arm using MMU read locks.
However, when userspace is clearing dirty logs via KVM_CLEAR_DIRTY_LOG
ioctl, then kernel code takes MMU write lock. This will block vCPUs
write protection faults and degrade guest performance. This
degradation gets worse as guest VM size increases in terms of memory and
vCPU count.
In this series, MMU read lock adoption is made possible by using
KVM_PGTABLE_WALK_SHARED flag in page walker.
Patches 1 to 5:
These patches are modifying dirty_log_perf_test. Intent is to mimic
production scenarios where guest keeps on executing while userspace
threads collect and clear dirty logs independently.
Three new command line options are added:
1. j: Allows to run guest vCPUs and main thread collecting dirty logs
independently of each other after initialization is complete.
2. k: Allows to clear dirty logs in smaller chunks compared to existing
whole memslot clear in one call.
3. l: Allows to add customizable wait time between consecutive clear
dirty log calls to mimic sending dirty memory to destination.
Patch 7-8:
These patches refactor code to move MMU lock operations to arch specific
code, refactor Arm's page table walker APIs, and change MMU write lock
for clearing dirty logs to read lock. Patch 8 has results showing
improvements based on dirty_log_perf_test.
Vipin Sharma (9):
KVM: selftests: Allow dirty_log_perf_test to clear dirty memory in
chunks
KVM: selftests: Add optional delay between consecutive Clear-Dirty-Log
calls
KVM: selftests: Pass count of read and write accesses from guest to
host
KVM: selftests: Print read and write accesses of pages by vCPUs in
dirty_log_perf_test
KVM: selftests: Allow independent execution of vCPUs in
dirty_log_perf_test
KVM: arm64: Correct the kvm_pgtable_stage2_flush() documentation
KVM: mmu: Move mmu lock/unlock to arch code for clear dirty log
KMV: arm64: Allow stage2_apply_range_sched() to pass page table walker
flags
KVM: arm64: Run clear-dirty-log under MMU read lock
arch/arm64/include/asm/kvm_pgtable.h | 17 ++-
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 4 +-
arch/arm64/kvm/hyp/pgtable.c | 16 ++-
arch/arm64/kvm/mmu.c | 36 ++++--
arch/mips/kvm/mmu.c | 2 +
arch/riscv/kvm/mmu.c | 2 +
arch/x86/kvm/mmu/mmu.c | 3 +
.../selftests/kvm/dirty_log_perf_test.c | 108 ++++++++++++++----
.../testing/selftests/kvm/include/memstress.h | 13 ++-
tools/testing/selftests/kvm/lib/memstress.c | 43 +++++--
virt/kvm/dirty_ring.c | 2 -
virt/kvm/kvm_main.c | 4 -
12 files changed, 185 insertions(+), 65 deletions(-)
base-commit: 95b9779c1758f03cf494e8550d6249a40089ed1c
--
2.40.0.634.g4ca3ef3211-goog
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^ permalink raw reply
* Re: [PATCH v2 7/7] ASoC: dt-bindings: mediatek,mt8188-afe: add audio properties
From: Krzysztof Kozlowski @ 2023-04-21 16:43 UTC (permalink / raw)
To: Trevor Wu, broonie, lgirdwood, tiwai, perex, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg, angelogioacchino.delregno
Cc: alsa-devel, linux-mediatek, linux-arm-kernel, linux-kernel,
devicetree
In-Reply-To: <20230421100905.28045-8-trevor.wu@mediatek.com>
On 21/04/2023 12:09, Trevor Wu wrote:
> Assign top_a1sys_hp clock to 26M, and add apll1_d4 to clocks for switching
> the parent of top_a1sys_hp dynamically
> On the other hand, "mediatek,infracfg" is included for bus protection.
>
> Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
> ---
> .../bindings/sound/mediatek,mt8188-afe.yaml | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
> index 82ccb32f08f2..812e0702ca36 100644
> --- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
> +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml
> @@ -29,6 +29,10 @@ properties:
> $ref: /schemas/types.yaml#/definitions/phandle
> description: The phandle of the mediatek topckgen controller
>
> + mediatek,infracfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle of the mediatek infracfg controller
> +
> power-domains:
> maxItems: 1
>
> @@ -52,6 +56,7 @@ properties:
> - description: mux for i2si1_mck
> - description: mux for i2si2_mck
> - description: audio 26m clock
> + - description: audio pll1 divide 4
>
> clock-names:
> items:
> @@ -73,6 +78,7 @@ properties:
> - const: i2si1_m_sel
> - const: i2si2_m_sel
> - const: adsp_audio_26m
> + - const: apll1_d4
>
> mediatek,etdm-in1-cowork-source:
> $ref: /schemas/types.yaml#/definitions/uint32
> @@ -147,6 +153,8 @@ required:
> - power-domains
> - clocks
> - clock-names
> + - assigned-clocks
> + - assigned-clock-parents
You were explaining it last time, but it did not solve my concerns.
Requiring these properties means that your hardware boots with incorrect
clock parents, including result of any firmware, and there is no way it
can correctly work without reparenting. What's more, this means that
your clock hierarchy does not include these clocks for some reason, e.g.
you need to reparent parents of some parent of your clock input,
otherwise device cannot work. Cannot work never ever.
Is this the case?
Have in mind that bindings are used also by other OS and projects, like
bootloaders, firmware etc.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup
From: Thomas Gleixner @ 2023-04-21 16:36 UTC (permalink / raw)
To: Paul Menzel
Cc: Sean Christopherson, Andrew Cooper, linux-kernel, x86,
David Woodhouse, Brian Gerst, Arjan van de Veen, Paolo Bonzini,
Paul McKenney, Tom Lendacky, Oleksandr Natalenko,
Guilherme G. Piccoli, Piotr Gorski, David Woodhouse, Usama Arif,
Jürgen Groß, Boris Ostrovsky, xen-devel, Russell King,
Arnd Bergmann, linux-arm-kernel, Catalin Marinas, Will Deacon,
Guo Ren, linux-csky, Thomas Bogendoerfer, linux-mips,
James E. J. Bottomley, Helge Deller, linux-parisc, Paul Walmsley,
Palmer Dabbelt, linux-riscv, Mark Rutland, Sabin Rapan
In-Reply-To: <87sfcu2wup.ffs@tglx>
On Thu, Apr 20 2023 at 21:10, Thomas Gleixner wrote:
> On Thu, Apr 20 2023 at 18:47, Paul Menzel wrote:
>> Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
>> I quickly applied it on top of your branch, but I am getting:
>
> As I said it was untested. I was traveling and did not have access to a
> machine to even build it completely. Fixed up and tested version below.
I've updated
git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git hotplug
for your conveniance.
Thanks,
tglx
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^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: net: mediatek: add WED RX binding for MT7981 eth driver
From: Krzysztof Kozlowski @ 2023-04-21 16:35 UTC (permalink / raw)
To: Daniel Golle, devicetree, netdev, linux-mediatek,
linux-arm-kernel, linux-kernel, Rob Herring, Krzysztof Kozlowski,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno
In-Reply-To: <b355493ed3d56396af91492b86f77f613485272a.1681994362.git.daniel@makrotopia.org>
On 20/04/2023 18:04, Daniel Golle wrote:
> Add compatible string for mediatek,mt7981-wed as MT7981 also supports
> RX WED just like MT7986, but needs a different firmware file.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH] arm64: defconfig: Enable PRUSS as module
From: Christian Gmeiner @ 2023-04-21 16:31 UTC (permalink / raw)
To: MD Danish Anwar
Cc: rafal, Mark Brown, nfraprado, Thierry Reding, Krzysztof Kozlowski,
Geert Uytterhoeven, Arnd Bergmann, Bjorn Andersson, Will Deacon,
Catalin Marinas, nm, linux-kernel, linux-arm-kernel, linux-omap,
vigneshr
In-Reply-To: <20230419095051.3269777-1-danishanwar@ti.com>
>
> Enables PRUSS as kernel module for TI SoCs.
>
> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index a24609e14d50..2a362a902526 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1277,6 +1277,7 @@ CONFIG_ARCH_TEGRA_186_SOC=y
> CONFIG_ARCH_TEGRA_194_SOC=y
> CONFIG_ARCH_TEGRA_234_SOC=y
> CONFIG_TI_SCI_PM_DOMAINS=y
> +CONFIG_TI_PRUSS=m
> CONFIG_ARM_IMX_BUS_DEVFREQ=y
> CONFIG_ARM_IMX8M_DDRC_DEVFREQ=m
> CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
> --
> 2.34.1
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
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^ permalink raw reply
* Re: [PATCH v5 06/11] dt-bindings: PCI: Update the RK3399 example to a valid one
From: Krzysztof Kozlowski @ 2023-04-21 16:30 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Rick Wertenbroek, alberto.dassatti, xxm, dlemoal, Shawn Lin,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Heiko Stuebner, Caleb Connolly,
Corentin Labbe, Brian Norris, Johan Jonker, Judy Hsiao,
Sascha Hauer, Hugh Cole-Baker, Arnaud Ferraris, linux-pci,
linux-rockchip, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <ZEJW0giyXAlNMYTz@lpieralisi>
On 21/04/2023 11:26, Lorenzo Pieralisi wrote:
> On Wed, Apr 19, 2023 at 10:01:25PM +0200, Krzysztof Kozlowski wrote:
>> On 18/04/2023 09:46, Rick Wertenbroek wrote:
>>> Update the example in the documentation to a valid example.
>>> Address for mem-base was invalid, it pointed to address
>>> 0x8000'0000 which is the upper region of the DDR which
>>> is not necessarily populated depending on the board.
>>> This address should point to the base of the memory
>>> window region of the controller which is 0xfa00'0000.
>>> Add missing pinctrl.
>>>
>>> Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
>>> ---
>>> .../devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> index 88386a6d7011..6b62f6f58efe 100644
>>> --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>>> @@ -47,7 +47,7 @@ examples:
>>>
>>> pcie-ep@f8000000 {
>>> compatible = "rockchip,rk3399-pcie-ep";
>>> - reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
>>> + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
>>> reg-names = "apb-base", "mem-base";
>>> clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
>>> <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
>>> @@ -63,6 +63,8 @@ examples:
>>> phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
>>> phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
>>> rockchip,max-outbound-regions = <16>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pcie_clkreqnb_cpm>;
>>
>> This is just example of the binding, you do not need to fill all
>> unrelated (generic) properties like pinctrl.
>
> Should I merge it as-is ?
Yeah, go ahead. That was the note for the future that generic properties
are not always needed or even helpful in the example.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [RFC PATCH net-next 04/22] net: dsa: mt7530: improve comments regarding port 5 and 6
From: Daniel Golle @ 2023-04-21 16:24 UTC (permalink / raw)
To: arinc9.unal
Cc: Sean Wang, Landen Chao, DENG Qingfang, Andrew Lunn,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King,
Arınç ÜNAL, Richard van Schagen,
Richard van Schagen, Frank Wunderlich, erkin.bozoglu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20230421143648.87889-5-arinc.unal@arinc9.com>
On Fri, Apr 21, 2023 at 05:36:30PM +0300, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> There's no logic to numerically order the CPU ports. State the port number
> and its capability of being used as a CPU port instead.
>
> Remove the irrelevant PHY muxing information from
> mt7530_mac_port_get_caps(). Explain the supported MII modes instead.
>
> Remove the out of place PHY muxing information from
> mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531
> switches but there's no PHY muxing on MT7531.
>
> These comments were gradually introduced with the commits below.
> ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
> 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
> 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new
> hardware")
> c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Daniel Golle <daniel@makrotopia.org>
> ---
> drivers/net/dsa/mt7530.c | 19 +++++++++++++------
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index edc34be745b2..e956ffa1eea8 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -2504,7 +2504,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
> config->supported_interfaces);
> break;
>
> - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
> + case 5: /* Port 5 which can be used as a CPU port supports rgmii with
> + * delays, mii, and gmii.
> + */
> phy_interface_set_rgmii(config->supported_interfaces);
> __set_bit(PHY_INTERFACE_MODE_MII,
> config->supported_interfaces);
> @@ -2512,7 +2514,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
> config->supported_interfaces);
> break;
>
> - case 6: /* 1st cpu port */
> + case 6: /* Port 6 which can be used as a CPU port supports rgmii and
> + * trgmii.
> + */
> __set_bit(PHY_INTERFACE_MODE_RGMII,
> config->supported_interfaces);
> __set_bit(PHY_INTERFACE_MODE_TRGMII,
> @@ -2532,14 +2536,17 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
> config->supported_interfaces);
> break;
>
> - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
> + case 5: /* Port 5 which can be used as a CPU port supports rgmii with
> + * delays on MT7531BE, sgmii/802.3z on MT7531AE.
> + */
> if (!priv->p5_sgmii) {
> phy_interface_set_rgmii(config->supported_interfaces);
> break;
> }
> fallthrough;
>
> - case 6: /* 1st cpu port supports sgmii/8023z only */
> + case 6: /* Port 6 which can be used as a CPU port supports sgmii/802.3z.
> + */
> __set_bit(PHY_INTERFACE_MODE_SGMII,
> config->supported_interfaces);
> __set_bit(PHY_INTERFACE_MODE_1000BASEX,
> @@ -2731,7 +2738,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> state->interface != PHY_INTERFACE_MODE_INTERNAL)
> goto unsupported;
> break;
> - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
> + case 5: /* Port 5, can be used as a CPU port. */
> if (priv->p5_interface == state->interface)
> break;
>
> @@ -2741,7 +2748,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> if (priv->p5_intf_sel != P5_DISABLED)
> priv->p5_interface = state->interface;
> break;
> - case 6: /* 1st cpu port */
> + case 6: /* Port 6, can be used as a CPU port. */
> if (priv->p6_interface == state->interface)
> break;
>
> --
> 2.37.2
>
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^ permalink raw reply
* Re: [RFC PATCH net-next 02/22] net: dsa: mt7530: use p5_interface_select as data type for p5_intf_sel
From: Daniel Golle @ 2023-04-21 16:23 UTC (permalink / raw)
To: arinc9.unal
Cc: Sean Wang, Landen Chao, DENG Qingfang, Andrew Lunn,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King,
Arınç ÜNAL, Richard van Schagen,
Richard van Schagen, Frank Wunderlich, erkin.bozoglu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20230421143648.87889-3-arinc.unal@arinc9.com>
On Fri, Apr 21, 2023 at 05:36:28PM +0300, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> Use the p5_interface_select enumeration as the data type for the
> p5_intf_sel field. This ensures p5_intf_sel can only take the values
> defined in the p5_interface_select enumeration.
>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> ---
> drivers/net/dsa/mt7530.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
> index 845f5dd16d83..703f8a528317 100644
> --- a/drivers/net/dsa/mt7530.h
> +++ b/drivers/net/dsa/mt7530.h
> @@ -674,13 +674,13 @@ struct mt7530_port {
> };
>
> /* Port 5 interface select definitions */
> -enum p5_interface_select {
> - P5_DISABLED = 0,
> +typedef enum {
We usually avoid adding typedef in kernel code. If the purpose is
just to be more verbose in the struct definition, you can as well
also just use 'enum p5_interface_select as type in the struct.
> + P5_DISABLED,
> P5_INTF_SEL_PHY_P0,
> P5_INTF_SEL_PHY_P4,
> P5_INTF_SEL_GMAC5,
> P5_INTF_SEL_GMAC5_SGMII,
> -};
> +} p5_interface_select;
>
> struct mt7530_priv;
>
> @@ -768,7 +768,7 @@ struct mt7530_priv {
> bool mcm;
> phy_interface_t p6_interface;
> phy_interface_t p5_interface;
> - unsigned int p5_intf_sel;
> + p5_interface_select p5_intf_sel;
enum p5_interface_select p5_intf_sel;
> u8 mirror_rx;
> u8 mirror_tx;
> struct mt7530_port ports[MT7530_NUM_PORTS];
> --
> 2.37.2
>
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^ permalink raw reply
* Re: [RFC PATCH net-next 01/22] net: dsa: mt7530: add missing @p5_interface to mt7530_priv description
From: Daniel Golle @ 2023-04-21 16:21 UTC (permalink / raw)
To: arinc9.unal
Cc: Sean Wang, Landen Chao, DENG Qingfang, Andrew Lunn,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King,
Arınç ÜNAL, Richard van Schagen,
Richard van Schagen, Frank Wunderlich, erkin.bozoglu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20230421143648.87889-2-arinc.unal@arinc9.com>
On Fri, Apr 21, 2023 at 05:36:27PM +0300, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> Add the missing p5_interface field to the mt7530_priv description. Sort out
> the description in the process.
>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Acked-by: Daniel Golle <daniel@makrotopia.org>
> ---
> drivers/net/dsa/mt7530.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
> index 5084f48a8869..845f5dd16d83 100644
> --- a/drivers/net/dsa/mt7530.h
> +++ b/drivers/net/dsa/mt7530.h
> @@ -746,7 +746,8 @@ struct mt753x_info {
> * @ports: Holding the state among ports
> * @reg_mutex: The lock for protecting among process accessing
> * registers
> - * @p6_interface Holding the current port 6 interface
> + * @p6_interface: Holding the current port 6 interface
> + * @p5_interface: Holding the current port 5 interface
> * @p5_intf_sel: Holding the current port 5 interface select
> * @irq: IRQ number of the switch
> * @irq_domain: IRQ domain of the switch irq_chip
> --
> 2.37.2
>
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^ permalink raw reply
* Re: [PATCH] spi: bcm63xx: remove PM_SLEEP based conditional compilation
From: Mark Brown @ 2023-04-21 16:06 UTC (permalink / raw)
To: Dhruva Gole
Cc: Vaishnav Achath, Vignesh, Apurva Nandan, linux-arm-kernel,
linux-spi, linux-kernel, Grant Likely, Tanguy Bouzeloc
In-Reply-To: <20230420121615.967487-1-d-gole@ti.com>
On Thu, 20 Apr 2023 17:46:15 +0530, Dhruva Gole wrote:
> Get rid of conditional compilation based on CONFIG_PM_SLEEP because
> it may introduce build issues with certain configs where it maybe disabled
> This is because if above config is not enabled the suspend-resume
> functions are never part of the code but the bcm63xx_spi_pm_ops struct
> still inits them to non-existent suspend-resume functions.
>
> Fixes: b42dfed83d95 ("spi: add Broadcom BCM63xx SPI controller driver")
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
Thanks!
[1/1] spi: bcm63xx: remove PM_SLEEP based conditional compilation
commit: 25f0617109496e1aff49594fbae5644286447a0f
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
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^ permalink raw reply
* linux-next: build failure after merge of the tip tree
From: broonie @ 2023-04-21 16:03 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H . Peter Anvin, Peter Zijlstra
Cc: stable, Marco Elver, Sebastian Andrzej Siewior, linux-arm-kernel,
Linux Kernel Mailing List, Linux Next Mailing List
Hi all,
After merging the tip tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:
/tmp/next/build/kernel/time/posix-cpu-timers.c: In function 'posix_cpu_timer_wait_running_nsleep':
/tmp/next/build/kernel/time/posix-cpu-timers.c:1310:30: error: 'timr' is a pointer; did you mean to use '->'?
1310 | spin_unlock_irq(&timr.it_lock);
| ^
| ->
/tmp/next/build/kernel/time/posix-cpu-timers.c:1312:28: error: 'timr' is a pointer; did you mean to use '->'?
1312 | spin_lock_irq(&timr.it_lock);
| ^
| ->
Caused by commit
2aaae4bf41b101f7e ("posix-cpu-timers: Implement the missing timer_wait_running callback")
The !POSIX_CPU_TIMERS_TASK_WORK case wasn't fully updated. I've used
the version of the tip tree from next-20230420 instead.
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^ permalink raw reply
* [PATCH 0/7] add displays support for bsh-smm-s2/pro boards
From: Dario Binacchi @ 2023-04-21 15:43 UTC (permalink / raw)
To: linux-kernel
Cc: michael, Amarula patchwork, Dario Binacchi, Adam Ford,
Daniel Vetter, David Airlie, Fabio Estevam, Jagan Teki,
Krzysztof Kozlowski, Marek Szyprowski, Marek Vasut,
NXP Linux Team, Pengutronix Kernel Team, Rob Herring,
Sam Ravnborg, Sascha Hauer, Shawn Guo, Thierry Reding, devicetree,
dri-devel, linux-arm-kernel
The series adds drivers for the displays used by bsh-smm-s2/pro boards.
It has been tested applying it on top of these patches:
Adam Ford <aford173@gmail.com> (6)
arm64: dts: imx8mn: Add display peripherals
drm: bridge: samsung-dsim: Dynamically configure DPHY timing
drm: bridge: samsung-dsim: Fetch pll-clock-frequency automatically
drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
drm: bridge: samsung-dsim: Support non-burst mode
drm: bridge: samsung-dsim: Support multi-lane calculations
Series "drm: Add Samsung MIPI DSIM bridge" (https://lwn.net/Articles/925754/)
Marek Vasut <marex@denx.de> (1):
0adce1be8dc0 drm: bridge: samsung-dsim: Add i.MX8M Plus support
Jagan Teki <jagan@amarulasolutions.com> (9):
0a98655a08cc dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support
b25b5384e27d drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support
ee83295c036d dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support
f18605b9b682 drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge
8ab12dbce060 drm: exynos: dsi: Add host helper for te_irq_handler
c37c8e89af38 drm: exynos: dsi: Consolidate component and bridge
11276ea9964a drm: exynos: dsi: Add atomic_get_input_bus_fmts
2fe8a5f92c08 drm: exynos: dsi: Add input_bus_flags
5d79cf173994 drm: exynos: dsi: Add atomic check
Marek Szyprowski <m.szyprowski@samsung.com> (1):
b9ad1112014d drm: exynos: dsi: Handle proper host initialization
Jagan Teki <jagan@amarulasolutions.com> (5):
93b2ce0c329d drm: exynos: dsi: Introduce hw_type platform data
83d704dc0cf6 drm: exynos: dsi: Add platform PLL_P (PMS_P) offset
f25b304ea948 drm: exynos: dsi: Mark PHY as optional
6c59da2ae519 drm: exynos: dsi: Lookup OF-graph or Child node devices
2186e15100de drm: exynos: dsi: Drop explicit call to bridge detach
Michael Trimarchi (7):
dt-bindings: display: panel: Add synaptics r63353 panel controller
drm/panel: Add Synaptics R63353 panel driver
arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup
dt-bindings: display: panel: Add Ilitek ili9805 panel controller
drm/panel: Add Ilitek ILI9805 panel driver
dt-bindings: ili9805: add compatible string for Tianma TM041XDHG01
drm/panel: ilitek-ili9805: add support for Tianma TM041XDHG01 panel
.../display/panel/ilitek,ili9805.yaml | 61 +++
.../display/panel/synaptics,r63353.yaml | 58 +++
MAINTAINERS | 12 +
.../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 +
.../freescale/imx8mn-bsh-smm-s2-display.dtsi | 111 +++++
drivers/gpu/drm/panel/Kconfig | 16 +
drivers/gpu/drm/panel/Makefile | 2 +
drivers/gpu/drm/panel/panel-ilitek-ili9805.c | 418 ++++++++++++++++++
.../gpu/drm/panel/panel-synaptics-r63353.c | 376 ++++++++++++++++
9 files changed, 1055 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9805.yaml
create mode 100644 Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi
create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9805.c
create mode 100644 drivers/gpu/drm/panel/panel-synaptics-r63353.c
--
2.32.0
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^ permalink raw reply
* [PATCH 3/7] arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup
From: Dario Binacchi @ 2023-04-21 15:43 UTC (permalink / raw)
To: linux-kernel
Cc: michael, Amarula patchwork, Dario Binacchi, Fabio Estevam,
Krzysztof Kozlowski, NXP Linux Team, Pengutronix Kernel Team,
Rob Herring, Sascha Hauer, Shawn Guo, devicetree,
linux-arm-kernel
In-Reply-To: <20230421154308.527128-1-dario.binacchi@amarulasolutions.com>
From: Michael Trimarchi <michael@amarulasolutions.com>
Add the display and nodes required for its operation.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
.../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 +
.../freescale/imx8mn-bsh-smm-s2-display.dtsi | 111 ++++++++++++++++++
2 files changed, 112 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
index c11895d9d582..5f9c0df0ec7d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
@@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8mn.dtsi"
+#include "imx8mn-bsh-smm-s2-display.dtsi"
/ {
chosen {
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi
new file mode 100644
index 000000000000..bac987d76f1e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 BSH
+ */
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <50>;
+ status = "okay";
+ };
+
+ reg_3v3_dvdd: regulator-3v3-O3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvdd>;
+ regulator-name = "3v3-dvdd-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_v3v3_avdd: regulator-3v3-O2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_avdd>;
+ regulator-name = "3v3-avdd-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pwm1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bl>;
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "sharp,ls068b3sx02", "synaptics,r63353";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel>;
+ reg = <0>;
+
+ backlight = <&backlight>;
+ dvdd-supply = <®_3v3_dvdd>;
+ avdd-supply = <®_v3v3_avdd>;
+ reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+};
+
+&iomuxc {
+
+ /* This is for both PWM and voltage regulators for display */
+ pinctrl_bl: pwm1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16
+ >;
+ };
+
+ pinctrl_panel: panelgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */
+ >;
+ };
+
+ pinctrl_dvdd: dvddgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */
+ >;
+ };
+
+ pinctrl_avdd: avddgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */
+ >;
+ };
+};
--
2.32.0
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^ permalink raw reply related
* Re: [PATCH] pwm: meson: simplify calculation in meson_pwm_get_state
From: Heiner Kallweit @ 2023-04-21 15:33 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: Jerome Brunet, Martin Blumenstingl, Neil Armstrong, Kevin Hilman,
Uwe Kleine-König, thierry.reding@gmail.com,
linux-arm-kernel@lists.infradead.org,
open list:ARM/Amlogic Meson..., linux-pwm, kernel
In-Reply-To: <20230421145723.oq7zqbhhz4fhkmyj@CAB-WSD-L081021>
On 21.04.2023 16:57, Dmitry Rokosov wrote:
> Hello Heiner,
>
> Thank you for the patch! Please find my comments below.
>
> On Wed, Apr 19, 2023 at 11:30:55PM +0200, Heiner Kallweit wrote:
>> I don't see a reason why we should treat the case lo < hi that
>> different and return 0 as period and duty_cycle. Let's handle it as
>> normal use case and also remove the optimization for lo == 0.
>> I think the improved readability is worth it.
>>
>> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
>
> Inside this patch, in my opinion, you have not only simplified and
> optimized but have also modified the logic. It is important to provide
> more details on this modification. Previously, in cases where
> (channel->lo != 0) && (channel->lo < channel->hi), period and duty_cycle
> were not calculated. However, in your patchset, duty_cycle and polarity
> are calculated and returned to the caller in such cases.
> Can you please share the details of why this is the right solution?
It's the obvious solution. I see no reason to return all zero's for
lo < hi, and also the commit that added this calculation doesn't provide
an explanation. It just references the calculation in meson_pwm_calc(),
however I fail to see that lo < hi is treated differently there.
c375bcbaabdb ("pwm: meson: Read the full hardware state in meson_pwm_get_state()")
> Also, please rephrase the commit message using 'modify' instead of
> 'simplify'.
>
>> ---
>> drivers/pwm/pwm-meson.c | 14 ++------------
>> 1 file changed, 2 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
>> index 5732300eb..3865538dd 100644
>> --- a/drivers/pwm/pwm-meson.c
>> +++ b/drivers/pwm/pwm-meson.c
>> @@ -351,18 +351,8 @@ static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
>> channel->lo = FIELD_GET(PWM_LOW_MASK, value);
>> channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
>>
>> - if (channel->lo == 0) {
>> - state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
>> - state->duty_cycle = state->period;
>> - } else if (channel->lo >= channel->hi) {
>> - state->period = meson_pwm_cnt_to_ns(chip, pwm,
>> - channel->lo + channel->hi);
>> - state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
>> - channel->hi);
>> - } else {
>> - state->period = 0;
>> - state->duty_cycle = 0;
>> - }
>> + state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
>> + state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
>>
>> state->polarity = PWM_POLARITY_NORMAL;
>>
>> --
>> 2.40.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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^ permalink raw reply
* [PATCH v2] arm64: dts: rockchip: fix nEXTRST on SOQuartz
From: Nicolas Frattaroli @ 2023-04-21 15:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, Peter Geis
Cc: Nicolas Frattaroli, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In pre-production prototypes (of which I only know one person
having one, Peter Geis), GPIO0 pin A5 was tied to the SDMMC
power enable pin on the CM4 connector. On all production models,
this is not the case; instead, this pin is used for the nEXTRST
signal, and the SDMMC power enable pin is always pulled high.
Since everyone currently using the SOQuartz device trees will
want this change, it is made to the tree without splitting the
trees into two separate ones of which users will then inevitably
choose the wrong one.
This fixes USB and PCIe on a wide variety of CM4IO-compatible
boards which use the nEXTRST signal.
Fixes: 5859b5a9c3ac ("arm64: dts: rockchip: add SoQuartz CM4IO dts")
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
Changes in v2:
- use GPIO hog instead of a fake regulator
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 18 +++++++-----
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 29 +++++++++----------
2 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
index 263ce40770dd..cddf6cd2fecb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -28,6 +28,16 @@ vcc_5v: vcc-5v-regulator {
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
+
+ vcc_sd_pwr: vcc-sd-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sd_pwr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
};
/* phy for pcie */
@@ -130,13 +140,7 @@ &saradc {
};
&sdmmc0 {
- vmmc-supply = <&sdmmc_pwr>;
- status = "okay";
-};
-
-&sdmmc_pwr {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ vmmc-supply = <&vcc_sd_pwr>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
index ce7165d7f1a1..3036985e2567 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -104,16 +104,6 @@ vcc3v3_sys: vcc3v3-sys-regulator {
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
-
- sdmmc_pwr: sdmmc-pwr-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwr_h>;
- regulator-name = "sdmmc_pwr";
- status = "disabled";
- };
};
&cpu0 {
@@ -155,6 +145,19 @@ &gmac1m0_clkinout
status = "disabled";
};
+&gpio0 {
+ nextrst-hog {
+ gpio-hog;
+ /*
+ * GPIO_ACTIVE_LOW + output-low here means that the pin is set
+ * to high, because output-low decides the value pre-inversion.
+ */
+ gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "nEXTRST";
+ };
+};
+
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -538,12 +541,6 @@ wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- sdmmc-pwr {
- sdmmc_pwr_h: sdmmc-pwr-h {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
};
&pmu_io_domains {
--
2.40.0
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^ permalink raw reply related
* [PATCH] net: ethernet: mediatek: remove return value check of `mtk_wed_hw_add_debugfs`
From: Wang Zhang @ 2023-04-21 15:10 UTC (permalink / raw)
To: Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno
Cc: hust-os-kernel-patches, Wang Zhang, Dongliang Mu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
Smatch complains that:
mtk_wed_hw_add_debugfs() warn: 'dir' is an error pointer or valid
Debugfs checks are generally not supposed to be checked
for errors and it is not necessary here.
fix it by just deleting the dead code.
Signed-off-by: Wang Zhang <silver_code@hust.edu.cn>
Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
---
This issue is found by static analyzer. The patched code has passed
Smatch checker, but remains untested on mediatek soc.
---
drivers/net/ethernet/mediatek/mtk_wed_debugfs.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
index 56f663439721..b244c02c5b51 100644
--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
@@ -252,8 +252,6 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
snprintf(hw->dirname, sizeof(hw->dirname), "wed%d", hw->index);
dir = debugfs_create_dir(hw->dirname, NULL);
- if (!dir)
- return;
hw->debugfs_dir = dir;
debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
--
2.34.1
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^ permalink raw reply related
* Re: [RFC PATCH net-next 03/22] net: dsa: mt7530: properly support MT7531AE and MT7531BE
From: Daniel Golle @ 2023-04-21 15:22 UTC (permalink / raw)
To: arinc9.unal
Cc: Sean Wang, Landen Chao, DENG Qingfang, Andrew Lunn,
Florian Fainelli, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King,
Arınç ÜNAL, Richard van Schagen,
Richard van Schagen, Frank Wunderlich, erkin.bozoglu, netdev,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20230421143648.87889-4-arinc.unal@arinc9.com>
On Fri, Apr 21, 2023 at 05:36:29PM +0300, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> Introduce the p5_sgmii pointer to store the information for whether port 5
> has got SGMII or not. Print "found MT7531AE" if it's got it, print "found
> MT7531BE" if it hasn't.
>
> Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the
> switch is identified.
>
> Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the
> information. Address the code where mt7531_dual_sgmii_supported() is used.
>
> Get rid of mt7531_is_rgmii_port() which just prints the opposite of
> priv->p5_sgmii.
>
> Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to
> represent the mode that port 5 is used in, not the hardware information of
> port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if port 5 is not
> dsa_is_unused_port().
>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> ---
> drivers/net/dsa/mt7530-mdio.c | 7 ++---
> drivers/net/dsa/mt7530.c | 49 +++++++++++++++--------------------
> drivers/net/dsa/mt7530.h | 6 +++--
> 3 files changed, 27 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
> index 088533663b83..fa3ee85a99c1 100644
> --- a/drivers/net/dsa/mt7530-mdio.c
> +++ b/drivers/net/dsa/mt7530-mdio.c
> @@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus = {
> };
>
> static int
> -mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
> +mt7531_create_sgmii(struct mt7530_priv *priv)
> {
> struct regmap_config *mt7531_pcs_config[2] = {};
> struct phylink_pcs *pcs;
> struct regmap *regmap;
> int i, ret = 0;
>
> - /* MT7531AE has two SGMII units for port 5 and port 6
> - * MT7531BE has only one SGMII unit for port 6
> - */
> - for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
> + for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) {
> mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
> sizeof(struct regmap_config),
> GFP_KERNEL);
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index c680873819b0..edc34be745b2 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -473,15 +473,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
> return 0;
> }
>
> -static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
> -{
> - u32 val;
> -
> - val = mt7530_read(priv, MT7531_TOP_SIG_SR);
> -
> - return (val & PAD_DUAL_SGMII_EN) != 0;
> -}
> -
> static int
> mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
> {
> @@ -496,7 +487,7 @@ mt7531_pll_setup(struct mt7530_priv *priv)
> u32 xtal;
> u32 val;
>
> - if (mt7531_dual_sgmii_supported(priv))
> + if (priv->p5_sgmii)
> return;
>
> val = mt7530_read(priv, MT7531_CREV);
> @@ -907,8 +898,6 @@ static const char *p5_intf_modes(unsigned int p5_interface)
> return "PHY P4";
> case P5_INTF_SEL_GMAC5:
> return "GMAC5";
> - case P5_INTF_SEL_GMAC5_SGMII:
> - return "GMAC5_SGMII";
> default:
> return "unknown";
> }
> @@ -2440,6 +2429,18 @@ mt7531_setup(struct dsa_switch *ds)
> return -ENODEV;
> }
>
> + /* MT7531AE has got two SGMII units. One for port 5, one for port 6.
> + * MT7531BE has got only one SGMII unit which is for port 6.
> + */
> + val = mt7530_read(priv, MT7531_TOP_SIG_SR);
> +
> + if ((val & PAD_DUAL_SGMII_EN) != 0) {
> + priv->p5_sgmii = true;
> + dev_info(priv->dev, "found MT7531AE\n");
> + } else {
> + dev_info(priv->dev, "found MT7531BE\n");
I don't think dev_info is useful here for regular users.
If you really want this output, use dev_dbg to reduce log pollution.
Imho completely removing the else branch and only silently
setting priv->p5_sgmii is sufficient, as users can also turn on
dyndbg for drivers/net/pcs/pcs-mtk-lynxi.c and will then be informed
about the created SGMII/1000Base-X/2500Base-X PCS instances.
> + }
> +
> /* all MACs must be forced link-down before sw reset */
> for (i = 0; i < MT7530_NUM_PORTS; i++)
> mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
> @@ -2451,19 +2452,16 @@ mt7531_setup(struct dsa_switch *ds)
>
> mt7531_pll_setup(priv);
>
> - if (mt7531_dual_sgmii_supported(priv)) {
> - priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
> -
> + if (priv->p5_sgmii) {
> /* Let ds->slave_mii_bus be able to access external phy. */
> mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
> MT7531_EXT_P_MDC_11);
> mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
> MT7531_EXT_P_MDIO_12);
> - } else {
> - priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
> }
> - dev_dbg(ds->dev, "P5 support %s interface\n",
> - p5_intf_modes(priv->p5_intf_sel));
> +
> + if (!dsa_is_unused_port(ds, 5))
> + priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
>
> mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
> MT7531_GPIO0_INTERRUPT);
> @@ -2523,11 +2521,6 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
> }
> }
>
> -static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
> -{
> - return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
> -}
> -
> static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
> struct phylink_config *config)
> {
> @@ -2540,7 +2533,7 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
> break;
>
> case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
> - if (mt7531_is_rgmii_port(priv, port)) {
> + if (!priv->p5_sgmii) {
> phy_interface_set_rgmii(config->supported_interfaces);
> break;
> }
> @@ -2607,7 +2600,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
> {
> u32 val;
>
> - if (!mt7531_is_rgmii_port(priv, port)) {
> + if (priv->p5_sgmii) {
> dev_err(priv->dev, "RGMII mode is not available for port %d\n",
> port);
> return -EINVAL;
> @@ -2860,7 +2853,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
>
> switch (port) {
> case 5:
> - if (mt7531_is_rgmii_port(priv, port))
> + if (!priv->p5_sgmii)
> interface = PHY_INTERFACE_MODE_RGMII;
> else
> interface = PHY_INTERFACE_MODE_2500BASEX;
> @@ -3019,7 +3012,7 @@ mt753x_setup(struct dsa_switch *ds)
> mt7530_free_irq_common(priv);
>
> if (priv->create_sgmii) {
> - ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
> + ret = priv->create_sgmii(priv);
> if (ret && priv->irq)
> mt7530_free_irq(priv);
> }
> diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
> index 703f8a528317..f58828577520 100644
> --- a/drivers/net/dsa/mt7530.h
> +++ b/drivers/net/dsa/mt7530.h
> @@ -679,7 +679,6 @@ typedef enum {
> P5_INTF_SEL_PHY_P0,
> P5_INTF_SEL_PHY_P4,
> P5_INTF_SEL_GMAC5,
> - P5_INTF_SEL_GMAC5_SGMII,
> } p5_interface_select;
>
> struct mt7530_priv;
> @@ -749,6 +748,8 @@ struct mt753x_info {
> * @p6_interface: Holding the current port 6 interface
> * @p5_interface: Holding the current port 5 interface
> * @p5_intf_sel: Holding the current port 5 interface select
> + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
> + * has got SGMII
> * @irq: IRQ number of the switch
> * @irq_domain: IRQ domain of the switch irq_chip
> * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
> @@ -769,6 +770,7 @@ struct mt7530_priv {
> phy_interface_t p6_interface;
> phy_interface_t p5_interface;
> p5_interface_select p5_intf_sel;
> + bool p5_sgmii;
> u8 mirror_rx;
> u8 mirror_tx;
> struct mt7530_port ports[MT7530_NUM_PORTS];
> @@ -778,7 +780,7 @@ struct mt7530_priv {
> int irq;
> struct irq_domain *irq_domain;
> u32 irq_enable;
> - int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
> + int (*create_sgmii)(struct mt7530_priv *priv);
> };
>
> struct mt7530_hw_vlan_entry {
> --
> 2.37.2
>
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