* [PATCH v2 2/2] trace, ras: add ARM RAS extension trace event
From: Ruidong Tian @ 2024-03-21 2:53 UTC (permalink / raw)
To: catalin.marinas, will, lpieralisi, guohanjun, sudeep.holla,
xueshuai, baolin.wang, linux-kernel, linux-acpi, linux-arm-kernel,
rafael, lenb, tony.luck, bp, linux-edac
Cc: tianruidond, Tyler Baicar, Ruidong Tian
In-Reply-To: <20240321025317.114621-1-tianruidong@linux.alibaba.com>
From: Tyler Baicar <baicar@os.amperecomputing.com>
Add a trace event for hardware errors reported by the ARMv8
RAS extension registers.
Signed-off-by: Tyler Baicar <baicar@os.amperecomputing.com>
Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
---
drivers/acpi/arm64/aest.c | 5 ++++
include/ras/ras_event.h | 55 +++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/drivers/acpi/arm64/aest.c b/drivers/acpi/arm64/aest.c
index ab17aa5f5997..0cfe7fb9d4b9 100644
--- a/drivers/acpi/arm64/aest.c
+++ b/drivers/acpi/arm64/aest.c
@@ -15,6 +15,8 @@
#include <acpi/actbl.h>
#include <asm/ras.h>
+#include <ras/ras_event.h>
+
#undef pr_fmt
#define pr_fmt(fmt) "ACPI AEST: " fmt
@@ -153,6 +155,9 @@ static void aest_print(struct aest_node_llist *lnode)
pr_err("%s ERR%uMISC2: 0x%llx\n", pfx_seq, index, regs->err_misc[2]);
pr_err("%s ERR%uMISC3: 0x%llx\n", pfx_seq, index, regs->err_misc[3]);
}
+
+ trace_arm_ras_ext_event(lnode->type, lnode->id0, lnode->id1, index,
+ lnode->regs);
}
static void aest_handle_memory_failure(struct aest_node_llist *lnode)
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index cbd3ddd7c33d..6003cab65ae4 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -338,6 +338,61 @@ TRACE_EVENT(aer_event,
"Not available")
);
+/*
+ * ARM RAS Extension Events Report
+ *
+ * This event is generated when an error reported by the ARM RAS extension
+ * hardware is detected.
+ */
+
+#ifdef CONFIG_ARM64_RAS_EXTN
+#include <asm/ras.h>
+TRACE_EVENT(arm_ras_ext_event,
+
+ TP_PROTO(u8 type, u32 id0, u32 id1, u32 index, struct ras_ext_regs *regs),
+
+ TP_ARGS(type, id0, id1, index, regs),
+
+ TP_STRUCT__entry(
+ __field(u8, type)
+ __field(u32, id0)
+ __field(u32, id1)
+ __field(u32, index)
+ __field(u64, err_fr)
+ __field(u64, err_ctlr)
+ __field(u64, err_status)
+ __field(u64, err_addr)
+ __field(u64, err_misc0)
+ __field(u64, err_misc1)
+ __field(u64, err_misc2)
+ __field(u64, err_misc3)
+ ),
+
+ TP_fast_assign(
+ __entry->type = type;
+ __entry->id0 = id0;
+ __entry->id1 = id1;
+ __entry->index = index;
+ __entry->err_fr = regs->err_fr;
+ __entry->err_ctlr = regs->err_ctlr;
+ __entry->err_status = regs->err_status;
+ __entry->err_addr = regs->err_addr;
+ __entry->err_misc0 = regs->err_misc[0];
+ __entry->err_misc1 = regs->err_misc[1];
+ __entry->err_misc2 = regs->err_misc[2];
+ __entry->err_misc3 = regs->err_misc[3];
+ ),
+
+ TP_printk("type: %d; id0: %d; id1: %d; index: %d; ERR_FR: %llx; ERR_CTLR: %llx; "
+ "ERR_STATUS: %llx; ERR_ADDR: %llx; ERR_MISC0: %llx; ERR_MISC1: %llx; "
+ "ERR_MISC2: %llx; ERR_MISC3: %llx",
+ __entry->type, __entry->id0, __entry->id1, __entry->index, __entry->err_fr,
+ __entry->err_ctlr, __entry->err_status, __entry->err_addr,
+ __entry->err_misc0, __entry->err_misc1, __entry->err_misc2,
+ __entry->err_misc3)
+);
+#endif
+
/*
* memory-failure recovery action result event
*
--
2.33.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 1/2] ACPI/AEST: Initial AEST driver
From: Ruidong Tian @ 2024-03-21 2:53 UTC (permalink / raw)
To: catalin.marinas, will, lpieralisi, guohanjun, sudeep.holla,
xueshuai, baolin.wang, linux-kernel, linux-acpi, linux-arm-kernel,
rafael, lenb, tony.luck, bp, linux-edac
Cc: tianruidond, Tyler Baicar, Ruidong Tian
In-Reply-To: <20240321025317.114621-1-tianruidong@linux.alibaba.com>
From: Tyler Baicar <baicar@os.amperecomputing.com>
Add support for parsing the ARM Error Source Table and basic handling of
errors reported through both memory mapped and system register interfaces.
Assume system register interfaces are only registered with private
peripheral interrupts (PPIs); otherwise there is no guarantee the
core handling the error is the core which took the error and has the
syndrome info in its system registers.
In kernel-first mode, all configuration is controlled by kernel, include
CE ce_threshold and interrupt enable/disable.
All detected errors will be processed as follow:
- CE, DE: use a workqueue to log this hardware errors.
- UER, UEO: log it and call memory_failure in workquee.
- UC, UEU: panic in irq context.
Signed-off-by: Tyler Baicar <baicar@os.amperecomputing.com>
Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com>
---
MAINTAINERS | 11 +
arch/arm64/include/asm/ras.h | 71 +++
drivers/acpi/arm64/Kconfig | 10 +
drivers/acpi/arm64/Makefile | 1 +
drivers/acpi/arm64/aest.c | 834 +++++++++++++++++++++++++++++++++++
include/linux/acpi_aest.h | 92 ++++
include/linux/cpuhotplug.h | 1 +
7 files changed, 1020 insertions(+)
create mode 100644 arch/arm64/include/asm/ras.h
create mode 100644 drivers/acpi/arm64/aest.c
create mode 100644 include/linux/acpi_aest.h
diff --git a/MAINTAINERS b/MAINTAINERS
index dd5de540ec0b..34900d4bb677 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -330,6 +330,17 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: drivers/acpi/arm64
+ACPI AEST
+M: Tyler Baicar <baicar@os.amperecomputing.com>
+M: Ruidong Tian <tianruidond@linux.alibaba.com>
+L: linux-acpi@vger.kernel.org
+L: linux-arm-kernel@lists.infradead.org
+S: Supported
+F: arch/arm64/include/asm/ras.h
+F: drivers/acpi/arm64/aest.c
+F: include/linux/acpi_aest.h
+
+
ACPI FOR RISC-V (ACPI/riscv)
M: Sunil V L <sunilvl@ventanamicro.com>
L: linux-acpi@vger.kernel.org
diff --git a/arch/arm64/include/asm/ras.h b/arch/arm64/include/asm/ras.h
new file mode 100644
index 000000000000..04667f0de30f
--- /dev/null
+++ b/arch/arm64/include/asm/ras.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_RAS_H
+#define __ASM_RAS_H
+
+#include <linux/types.h>
+#include <linux/bits.h>
+
+/* ERR<n>FR */
+#define ERR_FR_RP BIT(15)
+#define ERR_FR_CEC GENMASK_ULL(14, 12)
+
+#define ERR_FR_RP_SINGLE_COUNTER 0
+#define ERR_FR_RP_DOUBLE_COUNTER 1
+
+#define ERR_FR_CEC_0B_COUNTER 0
+#define ERR_FR_CEC_8B_COUNTER BIT(1)
+#define ERR_FR_CEC_16B_COUNTER BIT(2)
+
+/* ERR<n>STATUS */
+#define ERR_STATUS_AV BIT(31)
+#define ERR_STATUS_V BIT(30)
+#define ERR_STATUS_UE BIT(29)
+#define ERR_STATUS_ER BIT(28)
+#define ERR_STATUS_OF BIT(27)
+#define ERR_STATUS_MV BIT(26)
+#define ERR_STATUS_CE (BIT(25) | BIT(24))
+#define ERR_STATUS_DE BIT(23)
+#define ERR_STATUS_PN BIT(22)
+#define ERR_STATUS_UET (BIT(21) | BIT(20))
+#define ERR_STATUS_CI BIT(19)
+#define ERR_STATUS_IERR GENMASK_ULL(15, 8)
+#define ERR_STATUS_SERR GENMASK_ULL(7, 0)
+
+/* These bit is write-one-to-clear */
+#define ERR_STATUS_W1TC (ERR_STATUS_AV | ERR_STATUS_V | ERR_STATUS_UE | \
+ ERR_STATUS_ER | ERR_STATUS_OF | ERR_STATUS_MV | \
+ ERR_STATUS_CE | ERR_STATUS_DE | ERR_STATUS_PN | \
+ ERR_STATUS_UET | ERR_STATUS_CI)
+
+#define ERR_STATUS_UET_UC 0
+#define ERR_STATUS_UET_UEU 1
+#define ERR_STATUS_UET_UER 2
+#define ERR_STATUS_UET_UEO 3
+
+/* ERR<n>CTLR */
+#define ERR_CTLR_FI BIT(3)
+#define ERR_CTLR_UI BIT(2)
+
+/* ERR<n>ADDR */
+#define ERR_ADDR_AI BIT(61)
+#define ERR_ADDR_PADDR GENMASK_ULL(55, 0)
+
+/* ERR<n>MISC0 */
+
+/* ERR<n>FR.CEC == 0b010, ERR<n>FR.RP == 0 */
+#define ERR_MISC0_8B_OF BIT(39)
+#define ERR_MISC0_8B_CEC GENMASK_ULL(38, 32)
+
+/* ERR<n>FR.CEC == 0b100, ERR<n>FR.RP == 0 */
+#define ERR_MISC0_16B_OF BIT(47)
+#define ERR_MISC0_16B_CEC GENMASK_ULL(46, 32)
+
+struct ras_ext_regs {
+ u64 err_fr;
+ u64 err_ctlr;
+ u64 err_status;
+ u64 err_addr;
+ u64 err_misc[4];
+};
+
+#endif /* __ASM_RAS_H */
diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig
index b3ed6212244c..639db671c5cf 100644
--- a/drivers/acpi/arm64/Kconfig
+++ b/drivers/acpi/arm64/Kconfig
@@ -21,3 +21,13 @@ config ACPI_AGDI
config ACPI_APMT
bool
+
+config ACPI_AEST
+ bool "ARM Error Source Table Support"
+
+ help
+ The Arm Error Source Table (AEST) provides details on ACPI
+ extensions that enable kernel-first handling of errors in a
+ system that supports the Armv8 RAS extensions.
+
+ If set, the kernel will report and log hardware errors.
diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile
index 143debc1ba4a..b5b740058c46 100644
--- a/drivers/acpi/arm64/Makefile
+++ b/drivers/acpi/arm64/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ACPI_GTDT) += gtdt.o
obj-$(CONFIG_ACPI_APMT) += apmt.o
obj-$(CONFIG_ARM_AMBA) += amba.o
obj-y += dma.o init.o
+obj-$(CONFIG_ACPI_AEST) += aest.o
diff --git a/drivers/acpi/arm64/aest.c b/drivers/acpi/arm64/aest.c
new file mode 100644
index 000000000000..ab17aa5f5997
--- /dev/null
+++ b/drivers/acpi/arm64/aest.c
@@ -0,0 +1,834 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM Error Source Table Support
+ *
+ * Copyright (c) 2021, Ampere Computing LLC
+ * Copyright (c) 2021-2024, Alibaba Group.
+ */
+
+#include <linux/acpi.h>
+#include <linux/acpi_aest.h>
+#include <linux/cpuhotplug.h>
+#include <linux/kernel.h>
+#include <linux/genalloc.h>
+#include <linux/llist.h>
+#include <acpi/actbl.h>
+#include <asm/ras.h>
+
+#undef pr_fmt
+#define pr_fmt(fmt) "ACPI AEST: " fmt
+
+#define CASE_READ(res, x) \
+ case (x): { \
+ res = read_sysreg_s(SYS_##x##_EL1); \
+ break; \
+ }
+
+#define CASE_WRITE(val, x) \
+ case (x): { \
+ write_sysreg_s((val), SYS_##x##_EL1); \
+ break; \
+ }
+
+#define for_each_implemented_record(index, node) \
+ for ((index) = node->interface.record_start; \
+ (index) < node->interface.record_end; \
+ (index)++)
+
+#define AEST_LOG_PREFIX_BUFFER 64
+
+/*
+ * This memory pool is only to be used to save AEST node in AEST irq context.
+ * There can be 500 AEST node at most.
+ */
+#define AEST_NODE_ALLOCED_MAX 500
+
+static struct acpi_table_header *aest_table;
+
+static struct aest_node __percpu **aest_ppi_data;
+
+static int *ppi_irqs;
+static u8 num_ppi;
+static u8 ppi_idx;
+
+static struct work_struct aest_work;
+
+static struct gen_pool *aest_node_pool;
+static struct llist_head aest_node_llist;
+
+static u64 aest_sysreg_read(u64 __unused, u32 offset)
+{
+ u64 res;
+
+ switch (offset) {
+ CASE_READ(res, ERXFR)
+ CASE_READ(res, ERXCTLR)
+ CASE_READ(res, ERXSTATUS)
+ CASE_READ(res, ERXADDR)
+ CASE_READ(res, ERXMISC0)
+ CASE_READ(res, ERXMISC1)
+ CASE_READ(res, ERXMISC2)
+ CASE_READ(res, ERXMISC3)
+ default :
+ res = 0;
+ }
+ return res;
+}
+
+static void aest_sysreg_write(u64 base, u32 offset, u64 val)
+{
+ switch (offset) {
+ CASE_WRITE(val, ERXFR)
+ CASE_WRITE(val, ERXCTLR)
+ CASE_WRITE(val, ERXSTATUS)
+ CASE_WRITE(val, ERXADDR)
+ CASE_WRITE(val, ERXMISC0)
+ CASE_WRITE(val, ERXMISC1)
+ CASE_WRITE(val, ERXMISC2)
+ CASE_WRITE(val, ERXMISC3)
+ default :
+ return;
+ }
+}
+
+static u64 aest_iomem_read(u64 base, u32 offset)
+{
+ return readq_relaxed((void *)(base + offset));
+}
+
+static void aest_iomem_write(u64 base, u32 offset, u64 val)
+{
+ writeq_relaxed(val, (void *)(base + offset));
+}
+
+static void aest_print(struct aest_node_llist *lnode)
+{
+ static atomic_t seqno = { 0 };
+ unsigned int curr_seqno;
+ char pfx_seq[AEST_LOG_PREFIX_BUFFER];
+ int index;
+ struct ras_ext_regs *regs;
+
+ curr_seqno = atomic_inc_return(&seqno);
+ snprintf(pfx_seq, sizeof(pfx_seq), "{%u}" HW_ERR, curr_seqno);
+ pr_info("%sHardware error from %s\n", pfx_seq, lnode->node_name);
+
+ switch (lnode->type) {
+ case ACPI_AEST_PROCESSOR_ERROR_NODE:
+ pr_err("%s Error from CPU%d\n", pfx_seq, lnode->id0);
+ break;
+ case ACPI_AEST_MEMORY_ERROR_NODE:
+ pr_err("%s Error from memory at SRAT proximity domain 0x%x\n",
+ pfx_seq, lnode->id0);
+ break;
+ case ACPI_AEST_SMMU_ERROR_NODE:
+ pr_err("%s Error from SMMU IORT node 0x%x subcomponent 0x%x\n",
+ pfx_seq, lnode->id0, lnode->id1);
+ break;
+ case ACPI_AEST_VENDOR_ERROR_NODE:
+ pr_err("%s Error from vendor hid 0x%x uid 0x%x\n",
+ pfx_seq, lnode->id0, lnode->id1);
+ break;
+ case ACPI_AEST_GIC_ERROR_NODE:
+ pr_err("%s Error from GIC type 0x%x instance 0x%x\n",
+ pfx_seq, lnode->id0, lnode->id1);
+ break;
+ default:
+ pr_err("%s Unknown AEST node type\n", pfx_seq);
+ return;
+ }
+
+ index = lnode->index;
+ regs = lnode->regs;
+
+ pr_err("%s ERR%uFR: 0x%llx\n", pfx_seq, index, regs->err_fr);
+ pr_err("%s ERR%uCTRL: 0x%llx\n", pfx_seq, index, regs->err_ctlr);
+ pr_err("%s ERR%uSTATUS: 0x%llx\n", pfx_seq, index, regs->err_status);
+ if (regs->err_status & ERR_STATUS_AV)
+ pr_err("%s ERR%uADDR: 0x%llx\n", pfx_seq, index, regs->err_addr);
+
+ if (regs->err_status & ERR_STATUS_MV) {
+ pr_err("%s ERR%uMISC0: 0x%llx\n", pfx_seq, index, regs->err_misc[0]);
+ pr_err("%s ERR%uMISC1: 0x%llx\n", pfx_seq, index, regs->err_misc[1]);
+ pr_err("%s ERR%uMISC2: 0x%llx\n", pfx_seq, index, regs->err_misc[2]);
+ pr_err("%s ERR%uMISC3: 0x%llx\n", pfx_seq, index, regs->err_misc[3]);
+ }
+}
+
+static void aest_handle_memory_failure(struct aest_node_llist *lnode)
+{
+ unsigned long pfn;
+ u64 addr;
+
+ if (test_bit(lnode->index, &lnode->addressing_mode) ||
+ (lnode->regs->err_addr & ERR_ADDR_AI))
+ return;
+
+ addr = lnode->regs->err_addr & (1UL << CONFIG_ARM64_PA_BITS);
+ pfn = PHYS_PFN(addr);
+
+ if (!pfn_valid(pfn)) {
+ pr_warn(HW_ERR "Invalid physical address: %#llx\n", addr);
+ return;
+ }
+
+ memory_failure(pfn, 0);
+}
+
+static void aest_node_pool_process(struct work_struct *__unused)
+{
+ struct llist_node *head;
+ struct aest_node_llist *lnode, *tmp;
+ u64 status;
+
+ head = llist_del_all(&aest_node_llist);
+ if (!head)
+ return;
+
+ head = llist_reverse_order(head);
+ llist_for_each_entry_safe(lnode, tmp, head, llnode) {
+ aest_print(lnode);
+
+ status = lnode->regs->err_status;
+ if ((status & ERR_STATUS_UE) &&
+ (status & ERR_STATUS_UET) > ERR_STATUS_UET_UEU)
+ aest_handle_memory_failure(lnode);
+ gen_pool_free(aest_node_pool, (unsigned long)lnode,
+ sizeof(*lnode));
+ }
+}
+
+static int aest_node_gen_pool_add(struct aest_node *node, int index,
+ struct ras_ext_regs *regs)
+{
+ struct aest_node_llist *list;
+
+ if (!aest_node_pool)
+ return -EINVAL;
+
+ list = (void *)gen_pool_alloc(aest_node_pool, sizeof(*list));
+ if (!list)
+ return -ENOMEM;
+
+ list->type = node->type;
+ list->node_name = node->name;
+ switch (node->type) {
+ case ACPI_AEST_PROCESSOR_ERROR_NODE:
+ list->id0 = node->spec.processor.processor_id;
+ if (node->spec.processor.flags & (ACPI_AEST_PROC_FLAG_SHARED |
+ ACPI_AEST_PROC_FLAG_GLOBAL))
+ list->id0 = smp_processor_id();
+
+ list->id1 = node->spec.processor.resource_type;
+ break;
+ case ACPI_AEST_MEMORY_ERROR_NODE:
+ list->id0 = node->spec.memory.srat_proximity_domain;
+ break;
+ case ACPI_AEST_SMMU_ERROR_NODE:
+ list->id0 = node->spec.smmu.iort_node_reference;
+ list->id1 = node->spec.smmu.subcomponent_reference;
+ break;
+ case ACPI_AEST_VENDOR_ERROR_NODE:
+ list->id0 = node->spec.vendor.acpi_hid;
+ list->id1 = node->spec.vendor.acpi_uid;
+ break;
+ case ACPI_AEST_GIC_ERROR_NODE:
+ list->id0 = node->spec.gic.interface_type;
+ list->id1 = node->spec.gic.instance_id;
+ break;
+ default:
+ list->id0 = 0;
+ list->id1 = 0;
+ }
+
+ list->regs = regs;
+ list->index = index;
+ list->addressing_mode = node->interface.addressing_mode;
+ llist_add(&list->llnode, &aest_node_llist);
+
+ return 0;
+}
+
+static int aest_node_pool_init(void)
+{
+ unsigned long addr, size;
+ int rc;
+
+ if (aest_node_pool)
+ return 0;
+
+ size = ilog2(sizeof(struct aest_node_llist));
+ aest_node_pool = gen_pool_create(size, -1);
+ if (!aest_node_pool)
+ return -ENOMEM;
+
+ addr = (unsigned long)vmalloc(PAGE_ALIGN(size * AEST_NODE_ALLOCED_MAX));
+ if (!addr)
+ goto err_pool_alloc;
+
+ rc = gen_pool_add(aest_node_pool, addr, size, -1);
+ if (rc)
+ goto err_pool_add;
+
+ return 0;
+
+err_pool_add:
+ vfree((void *)addr);
+
+err_pool_alloc:
+ gen_pool_destroy(aest_node_pool);
+
+ return -ENOMEM;
+}
+
+static void aest_log(struct aest_node *node, int index, struct ras_ext_regs *regs)
+{
+ if (!aest_node_gen_pool_add(node, index, regs))
+ schedule_work(&aest_work);
+}
+
+/*
+ * Each PE may has multi error record, you must selects an error record to
+ * be accessed through the Error Record System registers.
+ */
+static inline void aest_select_record(struct aest_node *node, int i)
+{
+ if (node->interface.type == ACPI_AEST_NODE_SYSTEM_REGISTER) {
+ write_sysreg_s(i, SYS_ERRSELR_EL1);
+ isb();
+ }
+}
+
+/* Ensure all writes has taken effect. */
+static inline void aest_sync(struct aest_node *node)
+{
+ if (node->interface.type == ACPI_AEST_NODE_SYSTEM_REGISTER)
+ isb();
+}
+
+static int aest_proc(struct aest_node *node)
+{
+ struct ras_ext_regs regs = {0};
+ struct aest_access *access;
+ int i, count = 0;
+ u64 regs_p;
+
+ for_each_implemented_record(i, node) {
+
+ /* 1b: Error record at i index is not implemented */
+ if (test_bit(i, &node->interface.record_implemented))
+ continue;
+
+ aest_select_record(node, i);
+
+ access = node->access;
+ regs_p = (u64)&node->interface.regs[i];
+
+ regs.err_status = access->read(regs_p, ERXSTATUS);
+ if (!(regs.err_status & ERR_STATUS_V))
+ continue;
+
+ count++;
+
+ if (regs.err_status & ERR_STATUS_AV)
+ regs.err_addr = access->read(regs_p, ERXADDR);
+
+ regs.err_fr = access->read(regs_p, ERXFR);
+ regs.err_ctlr = access->read(regs_p, ERXCTLR);
+
+ if (regs.err_status & ERR_STATUS_MV) {
+ regs.err_misc[0] = access->read(regs_p, ERXMISC0);
+ regs.err_misc[1] = access->read(regs_p, ERXMISC1);
+ regs.err_misc[2] = access->read(regs_p, ERXMISC2);
+ regs.err_misc[3] = access->read(regs_p, ERXMISC3);
+ }
+
+ if (node->interface.flags & ACPI_AEST_INTERFACE_CLEAR_MISC) {
+ access->write(regs_p, ERXMISC0, 0);
+ access->write(regs_p, ERXMISC1, 0);
+ access->write(regs_p, ERXMISC2, 0);
+ access->write(regs_p, ERXMISC3, 0);
+ } else
+ access->write(regs_p, ERXMISC0,
+ node->interface.ce_threshold[i]);
+
+ aest_log(node, i, ®s);
+
+ /* panic if unrecoverable and uncontainable error encountered */
+ if ((regs.err_status & ERR_STATUS_UE) &&
+ (regs.err_status & ERR_STATUS_UET) < ERR_STATUS_UET_UER)
+ panic("AEST: unrecoverable error encountered");
+
+ /* Write-one-to-clear the bits we've seen */
+ regs.err_status &= ERR_STATUS_W1TC;
+
+ /* Multi bit filed need to write all-ones to clear. */
+ if (regs.err_status & ERR_STATUS_CE)
+ regs.err_status |= ERR_STATUS_CE;
+
+ /* Multi bit filed need to write all-ones to clear. */
+ if (regs.err_status & ERR_STATUS_UET)
+ regs.err_status |= ERR_STATUS_UET;
+
+ access->write(regs_p, ERXSTATUS, regs.err_status);
+
+ aest_sync(node);
+ }
+
+ return count;
+}
+
+static irqreturn_t aest_irq_func(int irq, void *input)
+{
+ struct aest_node *node = input;
+
+ if (aest_proc(node))
+ return IRQ_HANDLED;
+
+ return IRQ_NONE;
+}
+
+static int __init aest_register_gsi(u32 gsi, int trigger, void *data,
+ irq_handler_t aest_irq_func)
+{
+ int cpu, irq;
+
+ irq = acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
+
+ if (irq == -EINVAL) {
+ pr_err("failed to map AEST GSI %d\n", gsi);
+ return -EINVAL;
+ }
+
+ if (irq_is_percpu_devid(irq)) {
+ ppi_irqs[ppi_idx] = irq;
+ for_each_possible_cpu(cpu) {
+ memcpy(per_cpu_ptr(aest_ppi_data[ppi_idx], cpu), data,
+ sizeof(struct aest_node));
+ }
+ if (request_percpu_irq(irq, aest_irq_func, "AEST",
+ aest_ppi_data[ppi_idx++])) {
+ pr_err("failed to register AEST IRQ %d\n", irq);
+ return -EINVAL;
+ }
+ } else {
+ if (request_irq(irq, aest_irq_func, IRQF_SHARED, "AEST",
+ data)) {
+ pr_err("failed to register AEST IRQ %d\n", irq);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int __init aest_init_interrupts(struct acpi_aest_hdr *hdr,
+ struct aest_node *node)
+{
+ struct acpi_aest_node_interrupt *interrupt;
+ int i, trigger, ret = 0, err_ctlr, regs_p;
+
+ interrupt = ACPI_ADD_PTR(struct acpi_aest_node_interrupt, hdr,
+ hdr->node_interrupt_offset);
+
+ for (i = 0; i < hdr->node_interrupt_count; i++, interrupt++) {
+ trigger = (interrupt->flags & AEST_INTERRUPT_MODE) ?
+ ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
+ if (aest_register_gsi(interrupt->gsiv, trigger, node,
+ aest_irq_func))
+ ret = -EINVAL;
+ }
+
+ /* Ensure RAS interrupt is enabled */
+ for_each_implemented_record(i, node) {
+ /* 1b: Error record at i index is not implemented */
+ if (test_bit(i, &node->interface.record_implemented))
+ continue;
+
+ aest_select_record(node, i);
+
+ regs_p = (u64)&node->interface.regs[i];
+
+ err_ctlr = node->access->read(regs_p, ERXCTLR);
+
+ if (interrupt->type == ACPI_AEST_NODE_FAULT_HANDLING)
+ err_ctlr |= ERR_CTLR_FI;
+ if (interrupt->type == ACPI_AEST_NODE_ERROR_RECOVERY)
+ err_ctlr |= ERR_CTLR_UI;
+
+ node->access->write(regs_p, ERXCTLR, err_ctlr);
+
+ aest_sync(node);
+ }
+
+ return ret;
+}
+
+static void __init set_aest_node_name(struct aest_node *node)
+{
+ switch (node->type) {
+ case ACPI_AEST_PROCESSOR_ERROR_NODE:
+ node->name = kasprintf(GFP_KERNEL, "AEST-CPU%d",
+ node->spec.processor.processor_id);
+ break;
+ case ACPI_AEST_MEMORY_ERROR_NODE:
+ case ACPI_AEST_SMMU_ERROR_NODE:
+ case ACPI_AEST_VENDOR_ERROR_NODE:
+ case ACPI_AEST_GIC_ERROR_NODE:
+ node->name = kasprintf(GFP_KERNEL, "AEST-%llx",
+ node->interface.phy_addr);
+ break;
+ default:
+ node->name = kasprintf(GFP_KERNEL, "AEST-Unkown-Node");
+ }
+}
+
+/* access type is decided by AEST interface type. */
+static struct aest_access aest_access[] = {
+ [ACPI_AEST_NODE_SYSTEM_REGISTER] = {
+ .read = aest_sysreg_read,
+ .write = aest_sysreg_write,
+ },
+
+ [ACPI_AEST_NODE_MEMORY_MAPPED] = {
+ .read = aest_iomem_read,
+ .write = aest_iomem_write,
+ },
+ { }
+};
+
+/* In kernel-first mode, kernel will report every CE by default. */
+static void __init aest_set_ce_threshold(struct aest_node *node)
+{
+ u64 regs_p, err_fr, err_fr_cec, err_fr_rp, err_misc0, ce_threshold;
+ int i;
+
+ for_each_implemented_record(i, node) {
+ /* 1b: Error record at i index is not implemented */
+ if (test_bit(i, &node->interface.record_implemented))
+ continue;
+
+ aest_select_record(node, i);
+ regs_p = (u64)&node->interface.regs[i];
+
+ err_fr = node->access->read(regs_p, ERXFR);
+ err_fr_cec = FIELD_GET(ERR_FR_CEC, err_fr);
+ err_fr_rp = FIELD_GET(ERR_FR_RP, err_fr);
+ err_misc0 = node->access->read(regs_p, ERXMISC0);
+
+ if (err_fr_cec == ERR_FR_CEC_0B_COUNTER)
+ pr_debug("%s-%d do not support CE threshold!\n",
+ node->name, i);
+ else if (err_fr_cec == ERR_FR_CEC_8B_COUNTER &&
+ err_fr_rp == ERR_FR_RP_SINGLE_COUNTER) {
+ pr_debug("%s-%d support 8 bit CE threshold!\n",
+ node->name, i);
+ ce_threshold = err_misc0 | ERR_MISC0_8B_CEC;
+ } else if (err_fr_cec == ERR_FR_CEC_16B_COUNTER &&
+ err_fr_rp == ERR_FR_RP_SINGLE_COUNTER) {
+ pr_debug("%s-%d support 16 bit CE threshold!\n",
+ node->name, i);
+ ce_threshold = err_misc0 | ERR_MISC0_16B_CEC;
+ } else
+ pr_debug("%s-%d do not support double counter yet!\n",
+ node->name, i);
+
+ node->access->write(regs_p, ERXMISC0, ce_threshold);
+ node->interface.ce_threshold[i] = ce_threshold;
+
+ aest_sync(node);
+ }
+}
+
+static int __init aest_init_interface(struct acpi_aest_hdr *hdr,
+ struct aest_node *node)
+{
+ struct acpi_aest_node_interface *interface;
+ struct resource *res;
+ int size;
+
+ interface = ACPI_ADD_PTR(struct acpi_aest_node_interface, hdr,
+ hdr->node_interface_offset);
+
+ if (interface->type >= ACPI_AEST_XFACE_RESERVED) {
+ pr_err("invalid interface type: %d\n", interface->type);
+ return -EINVAL;
+ }
+
+ node->interface.type = interface->type;
+ node->interface.phy_addr = interface->address;
+ node->interface.record_start = interface->error_record_index;
+ node->interface.record_end = interface->error_record_index +
+ interface->error_record_count;
+ node->interface.flags = interface->flags;
+ node->interface.record_implemented = interface->error_record_implemented;
+ node->interface.status_reporting = interface->error_status_reporting;
+ node->interface.addressing_mode = interface->addressing_mode;
+ node->access = &aest_access[interface->type];
+
+ /*
+ * Currently SR based handling is done through the architected
+ * discovery exposed through SRs. That may change in the future
+ * if there is supplemental information in the AEST that is
+ * needed.
+ */
+ if (interface->type == ACPI_AEST_NODE_SYSTEM_REGISTER)
+ return 0;
+
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+ if (!res)
+ return -ENOMEM;
+
+ size = interface->error_record_count * sizeof(struct ras_ext_regs);
+ res->name = "AEST";
+ res->start = interface->address;
+ res->end = res->start + size;
+ res->flags = IORESOURCE_MEM;
+
+ if (insert_resource(&iomem_resource, res)) {
+ pr_notice("request region conflict with %s\n",
+ res->name);
+ }
+
+ node->interface.regs = ioremap(res->start, size);
+ if (!node->interface.regs) {
+ pr_err("Ioremap for %s failed!\n", node->name);
+ kfree(res);
+ return -EINVAL;
+ }
+
+ node->interface.ce_threshold = kzalloc(sizeof(u64) *
+ interface->error_record_count, GFP_KERNEL);
+ if (!node->interface.ce_threshold)
+ return -ENOMEM;
+
+ aest_set_ce_threshold(node);
+
+ return 0;
+}
+
+static int __init aest_init_common(struct acpi_aest_hdr *hdr,
+ struct aest_node *node)
+{
+ int ret;
+
+ set_aest_node_name(node);
+
+ ret = aest_init_interface(hdr, node);
+ if (ret) {
+ pr_err("failed to init interface\n");
+ return ret;
+ }
+
+ return aest_init_interrupts(hdr, node);
+}
+
+static int __init aest_init_node_default(struct acpi_aest_hdr *hdr)
+{
+ struct aest_node *node;
+ union aest_node_spec *node_spec;
+ int ret;
+
+ node = kzalloc(sizeof(struct aest_node), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+
+ node->type = hdr->type;
+ node_spec = ACPI_ADD_PTR(union aest_node_spec, hdr,
+ hdr->node_specific_offset);
+
+ memcpy(&node->spec, node_spec,
+ hdr->node_interface_offset - hdr->node_specific_offset);
+
+ ret = aest_init_common(hdr, node);
+ if (ret)
+ kfree(node);
+
+ return ret;
+}
+
+static int __init aest_init_processor_node(struct acpi_aest_hdr *hdr)
+{
+ struct aest_node *node;
+ union aest_node_spec *node_spec;
+ union aest_node_processor *proc;
+ int ret;
+
+ node = kzalloc(sizeof(struct aest_node), GFP_KERNEL);
+ if (!node)
+ return -ENOMEM;
+
+ node->type = hdr->type;
+ node_spec = ACPI_ADD_PTR(union aest_node_spec, hdr,
+ hdr->node_specific_offset);
+
+ memcpy(&node->spec, node_spec,
+ hdr->node_interface_offset - hdr->node_specific_offset);
+
+ proc = ACPI_ADD_PTR(union aest_node_processor, node_spec,
+ sizeof(acpi_aest_processor));
+
+ switch (node->spec.processor.resource_type) {
+ case ACPI_AEST_CACHE_RESOURCE:
+ memcpy(&node->proc, proc,
+ sizeof(struct acpi_aest_processor_cache));
+ break;
+ case ACPI_AEST_TLB_RESOURCE:
+ memcpy(&node->proc, proc,
+ sizeof(struct acpi_aest_processor_tlb));
+ break;
+ case ACPI_AEST_GENERIC_RESOURCE:
+ memcpy(&node->proc, proc,
+ sizeof(struct acpi_aest_processor_generic));
+ break;
+ }
+
+ ret = aest_init_common(hdr, node);
+ if (ret)
+ kfree(node);
+
+ return ret;
+}
+
+static int __init aest_init_node(struct acpi_aest_hdr *node)
+{
+ switch (node->type) {
+ case ACPI_AEST_PROCESSOR_ERROR_NODE:
+ return aest_init_processor_node(node);
+ case ACPI_AEST_MEMORY_ERROR_NODE:
+ case ACPI_AEST_VENDOR_ERROR_NODE:
+ case ACPI_AEST_SMMU_ERROR_NODE:
+ case ACPI_AEST_GIC_ERROR_NODE:
+ return aest_init_node_default(node);
+ default:
+ return -EINVAL;
+ }
+}
+
+static void __init aest_count_ppi(struct acpi_aest_hdr *header)
+{
+ struct acpi_aest_node_interrupt *interrupt;
+ int i;
+
+ interrupt = ACPI_ADD_PTR(struct acpi_aest_node_interrupt, header,
+ header->node_interrupt_offset);
+
+ for (i = 0; i < header->node_interrupt_count; i++, interrupt++) {
+ if (interrupt->gsiv >= 16 && interrupt->gsiv < 32)
+ num_ppi++;
+ }
+}
+
+static int aest_starting_cpu(unsigned int cpu)
+{
+ int i;
+
+ for (i = 0; i < num_ppi; i++)
+ enable_percpu_irq(ppi_irqs[i], IRQ_TYPE_NONE);
+
+ return 0;
+}
+
+static int aest_dying_cpu(unsigned int cpu)
+{
+ int i;
+
+ for (i = 0; i < num_ppi; i++)
+ disable_percpu_irq(ppi_irqs[i]);
+
+ return 0;
+}
+
+int __init acpi_aest_init(void)
+{
+ struct acpi_aest_hdr *aest_node, *aest_end;
+ struct acpi_table_aest *aest;
+ int i, ret = 0;
+
+ if (acpi_disabled)
+ return 0;
+
+ if (!IS_ENABLED(CONFIG_ARM64_RAS_EXTN))
+ return 0;
+
+ if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_AEST, 0, &aest_table)))
+ return -EINVAL;
+
+ ret = aest_node_pool_init();
+ if (ret) {
+ pr_err("Failed init aest node pool.\n");
+ goto fail;
+ }
+
+ INIT_WORK(&aest_work, aest_node_pool_process);
+
+ aest = (struct acpi_table_aest *)aest_table;
+
+ /* Get the first AEST node */
+ aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest,
+ sizeof(struct acpi_table_header));
+ /* Pointer to the end of the AEST table */
+ aest_end = ACPI_ADD_PTR(struct acpi_aest_hdr, aest,
+ aest_table->length);
+
+ while (aest_node < aest_end) {
+ if (((u64)aest_node + aest_node->length) > (u64)aest_end) {
+ pr_err("AEST node pointer overflow, bad table.\n");
+ return -EINVAL;
+ }
+
+ aest_count_ppi(aest_node);
+
+ aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest_node,
+ aest_node->length);
+ }
+
+ aest_ppi_data = kcalloc(num_ppi, sizeof(struct aest_node_data *),
+ GFP_KERNEL);
+ if (!aest_ppi_data) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ ppi_irqs = kcalloc(num_ppi, sizeof(int), GFP_KERNEL);
+ if (!ppi_irqs) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ for (i = 0; i < num_ppi; i++) {
+ aest_ppi_data[i] = alloc_percpu(struct aest_node);
+ if (!aest_ppi_data[i]) {
+ pr_err("Failed percpu allocation.\n");
+ ret = -ENOMEM;
+ goto fail;
+ }
+ }
+
+ aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest,
+ sizeof(struct acpi_table_header));
+
+ while (aest_node < aest_end) {
+ ret = aest_init_node(aest_node);
+ if (ret) {
+ pr_err("failed to init node: %d", ret);
+ goto fail;
+ }
+
+ aest_node = ACPI_ADD_PTR(struct acpi_aest_hdr, aest_node,
+ aest_node->length);
+ }
+
+
+
+ return cpuhp_setup_state(CPUHP_AP_ARM_AEST_STARTING,
+ "drivers/acpi/arm64/aest:starting",
+ aest_starting_cpu, aest_dying_cpu);
+
+fail:
+ for (i = 0; i < num_ppi; i++)
+ free_percpu(aest_ppi_data[i]);
+ kfree(aest_ppi_data);
+ return ret;
+}
+subsys_initcall(acpi_aest_init);
diff --git a/include/linux/acpi_aest.h b/include/linux/acpi_aest.h
new file mode 100644
index 000000000000..679187505dc6
--- /dev/null
+++ b/include/linux/acpi_aest.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef AEST_H
+#define AEST_H
+
+#include <acpi/actbl.h>
+#include <asm/ras.h>
+
+#define AEST_INTERRUPT_MODE BIT(0)
+
+#define ACPI_AEST_PROC_FLAG_GLOBAL (1<<0)
+#define ACPI_AEST_PROC_FLAG_SHARED (1<<1)
+
+#define ACPI_AEST_INTERFACE_CLEAR_MISC (1<<0)
+
+#define ERXFR 0x0
+#define ERXCTLR 0x8
+#define ERXSTATUS 0x10
+#define ERXADDR 0x18
+#define ERXMISC0 0x20
+#define ERXMISC1 0x28
+#define ERXMISC2 0x30
+#define ERXMISC3 0x38
+
+struct aest_node_interface {
+ u8 type;
+ u64 phy_addr;
+ u16 record_start;
+ u16 record_end;
+ u32 flags;
+ unsigned long record_implemented;
+ unsigned long status_reporting;
+ unsigned long addressing_mode;
+ struct ras_ext_regs *regs;
+ u64 *ce_threshold;
+};
+
+union aest_node_processor {
+ struct acpi_aest_processor_cache cache_data;
+ struct acpi_aest_processor_tlb tlb_data;
+ struct acpi_aest_processor_generic generic_data;
+};
+
+union aest_node_spec {
+ struct acpi_aest_processor processor;
+ struct acpi_aest_memory memory;
+ struct acpi_aest_smmu smmu;
+ struct acpi_aest_vendor vendor;
+ struct acpi_aest_gic gic;
+};
+
+struct aest_access {
+ u64 (*read)(u64 base, u32 offset);
+ void (*write)(u64 base, u32 offset, u64 val);
+};
+
+struct aest_node {
+ char *name;
+ u8 type;
+ struct aest_node_interface interface;
+ union aest_node_spec spec;
+ union aest_node_processor proc;
+ struct aest_access *access;
+};
+
+struct aest_node_llist {
+ struct llist_node llnode;
+ char *node_name;
+ int type;
+ /*
+ * Different nodes have different meanings:
+ * - Processor node : processor number.
+ * - Memory node : SRAT proximity domain.
+ * - SMMU node : IORT proximity domain.
+ * - Vendor node : hardware ID.
+ * - GIC node : interface type.
+ */
+ u32 id0;
+ /*
+ * Different nodes have different meanings:
+ * - Processor node : processor resource type.
+ * - Memory node : Non.
+ * - SMMU node : subcomponent reference.
+ * - Vendor node : Unique ID.
+ * - GIC node : instance identifier.
+ */
+ u32 id1;
+ int index;
+ unsigned long addressing_mode;
+ struct ras_ext_regs *regs;
+};
+
+#endif /* AEST_H */
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 624d4a38c358..f0dda08dbad2 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -186,6 +186,7 @@ enum cpuhp_state {
CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_TI_GP_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
+ CPUHP_AP_ARM_AEST_STARTING,
/* Must be the last timer callback */
CPUHP_AP_DUMMY_TIMER_STARTING,
CPUHP_AP_ARM_XEN_STARTING,
--
2.33.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 0/2] ARM Error Source Table V1 Support
From: Ruidong Tian @ 2024-03-21 2:53 UTC (permalink / raw)
To: catalin.marinas, will, lpieralisi, guohanjun, sudeep.holla,
xueshuai, baolin.wang, linux-kernel, linux-acpi, linux-arm-kernel,
rafael, lenb, tony.luck, bp, linux-edac
Cc: tianruidond, Ruidong Tian
This series adds support for the ARM Error Source Table (AEST) based on
the 1.1 version of ACPI for the Armv8 RAS Extensions [0].
The Arm Error Source Table (AEST) enable kernel-first handling of errors
in a system that supports the Armv8 RAS extensions. In kernel-first mode,
kernel controls almost all RAS configuration, include CE threshold and
interrupt enable/disable. Hardware errors will trigger a RAS interrupt
to kernel, kernel scan all AEST node to find error node which occur
error in irq context and process the RAS error. Kernel will act as
follow for different types error:
- CE, DE: use a workqueue to log this hardware errors.
- UER, UEO: call memory_failure.
- UC, UEU: panic.
I have tested this series on PTG Yitian710 SOC. Both corrected and
uncorrected errors were tested to verify the non-fatal vs fatal
scenarios.
Future work:
1. Add CE storm mitigation.
2. Support AEST V2.
This series is based on Tyler Baicar's patches [1], which do not have v2
sended to mail list yet. Change from origin patch:
1. Add a genpool to collect all AEST error, and log them in a workqueue
other than in irq context.
2. Just use the same one aest_proc function for system register interface
and MMIO interface.
3. Reconstruct some structures and functions to make it more clear.
4. Accept all comments in Tyler Baicar's mail list.
Change from V1:
https://lore.kernel.org/all/20240304111517.33001-1-tianruidong@linux.alibaba.com/
1. Marc Zyngier
- Use readq/writeq_relaxed instead of readq/writeq for MMIO address.
- Add sync for system register operation.
- Use irq_is_percpu_devid() helper to identify a per-CPU interrupt.
- Other fix.
2. Set RAS CE threshold in AEST driver.
3. Enable RAS interrupt explicitly in driver.
4. UER and UEO trigger memory_failure other than panic.
[0]: https://developer.arm.com/documentation/den0085/0101/
[1]: https://lore.kernel.org/all/20211124170708.3874-1-baicar@os.amperecomputing.com/
Tyler Baicar (2):
ACPI/AEST: Initial AEST driver
trace, ras: add ARM RAS extension trace event
MAINTAINERS | 11 +
arch/arm64/include/asm/ras.h | 71 +++
drivers/acpi/arm64/Kconfig | 10 +
drivers/acpi/arm64/Makefile | 1 +
drivers/acpi/arm64/aest.c | 839 +++++++++++++++++++++++++++++++++++
include/linux/acpi_aest.h | 92 ++++
include/linux/cpuhotplug.h | 1 +
include/ras/ras_event.h | 55 +++
8 files changed, 1080 insertions(+)
create mode 100644 arch/arm64/include/asm/ras.h
create mode 100644 drivers/acpi/arm64/aest.c
create mode 100644 include/linux/acpi_aest.h
--
2.33.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2] clk: imx: imx8mp: Add pm_runtime support for power saving
From: Shengjiu Wang @ 2024-03-21 2:37 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Shengjiu Wang, abelvesa, peng.fan, mturquette, sboyd, shawnguo,
s.hauer, kernel, festevam, linux-imx, linux-clk, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240320-posing-quit-ab4b13557cc9-mkl@pengutronix.de>
On Wed, Mar 20, 2024 at 5:50 PM Marc Kleine-Budde <mkl@pengutronix.de> wrote:
>
> On 20.03.2024 17:10:51, Shengjiu Wang wrote:
> > Add pm_runtime support for power saving. In pm runtime suspend
> > state the registers will be reseted, so add registers save
> > in pm runtime suspend and restore them in pm runtime resume.
> >
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > Reviewed-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > changes in v2:
> > - move pm_runtime_enable before the clk register
> >
> > drivers/clk/imx/clk-imx8mp-audiomix.c | 150 +++++++++++++++++++++++---
> > 1 file changed, 137 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > index 55ed211a5e0b..6042280d6404 100644
> > --- a/drivers/clk/imx/clk-imx8mp-audiomix.c
> > +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
> > @@ -7,10 +7,12 @@
> >
> > #include <linux/clk-provider.h>
> > #include <linux/device.h>
> > +#include <linux/io.h>
> > #include <linux/mod_devicetable.h>
> > #include <linux/module.h>
> > #include <linux/of.h>
> > #include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> >
> > #include <dt-bindings/clock/imx8mp-clock.h>
> >
> > @@ -18,6 +20,7 @@
> >
> > #define CLKEN0 0x000
> > #define CLKEN1 0x004
> > +#define EARC 0x200
> > #define SAI1_MCLK_SEL 0x300
> > #define SAI2_MCLK_SEL 0x304
> > #define SAI3_MCLK_SEL 0x308
> > @@ -26,6 +29,12 @@
> > #define SAI7_MCLK_SEL 0x314
> > #define PDM_SEL 0x318
> > #define SAI_PLL_GNRL_CTL 0x400
> > +#define SAI_PLL_FDIVL_CTL0 0x404
> > +#define SAI_PLL_FDIVL_CTL1 0x408
> > +#define SAI_PLL_SSCG_CTL 0x40C
> > +#define SAI_PLL_MNIT_CTL 0x410
> > +#define IPG_LP_CTRL 0x504
> > +#define REGS_NUM 16
>
> not needed
>
> >
> > #define SAIn_MCLK1_PARENT(n) \
> > static const struct clk_parent_data \
> > @@ -182,13 +191,65 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
> > CLK_SAIn(7)
> > };
> >
> > +struct clk_imx8mp_audiomix_regs {
> > + u32 regs_num;
> > + u32 regs_off[];
>
> nitpick: if the offsets fit into an u16 you can save some space.
>
> > +};
> > +
> > +static const struct clk_imx8mp_audiomix_regs audiomix_regs = {
> > + .regs_num = REGS_NUM,
> > + .regs_off = {
> > + CLKEN0,
> > + CLKEN1,
> > + EARC,
> > + SAI1_MCLK_SEL,
> > + SAI2_MCLK_SEL,
> > + SAI3_MCLK_SEL,
> > + SAI5_MCLK_SEL,
> > + SAI6_MCLK_SEL,
> > + SAI7_MCLK_SEL,
> > + PDM_SEL,
> > + SAI_PLL_GNRL_CTL,
> > + SAI_PLL_FDIVL_CTL0,
> > + SAI_PLL_FDIVL_CTL1,
> > + SAI_PLL_SSCG_CTL,
> > + SAI_PLL_MNIT_CTL,
> > + IPG_LP_CTRL
> > + },
> > +};
>
> You only need an array with the offsets, use ARRAY_SIZE() to get the
> number of entries in the array.
>
> > +
> > +struct clk_imx8mp_audiomix_drvdata {
> > + void __iomem *base;
> > + u32 regs_save[REGS_NUM];
>
> make use of ARRAY_SIZE() here
>
> > +};
> > +
> > +static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
> > +{
> > + struct clk_imx8mp_audiomix_drvdata *drvdata = dev_get_drvdata(dev);
> > + void __iomem *base = drvdata->base;
> > + int i;
> > +
> > + if (save) {
> > + for (i = 0; i < audiomix_regs.regs_num; i++)
> > + drvdata->regs_save[i] = readl(base + audiomix_regs.regs_off[i]);
> > + } else {
> > + for (i = 0; i < audiomix_regs.regs_num; i++)
> > + writel(drvdata->regs_save[i], base + audiomix_regs.regs_off[i]);
> > + }
> > +}
> > +
> > static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> > {
> > + struct clk_imx8mp_audiomix_drvdata *drvdata;
> > struct clk_hw_onecell_data *priv;
> > struct device *dev = &pdev->dev;
> > void __iomem *base;
> > struct clk_hw *hw;
> > - int i;
> > + int i, ret;
> > +
> > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>
> You already allocate memory with devm_kzalloc() below. Why not increase
> the size?
>
> Rename clk_imx8mp_audiomix_drvdata to clk_imx8mp_audiomix_priv
> and add struct clk_hw_onecell_data to it.
Ok, I will update according to all the comments in the next version.
best regards
wang shengjiu
>
> > + if (!drvdata)
> > + return -ENOMEM;
> >
> > priv = devm_kzalloc(dev,
> > struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
> > @@ -202,6 +263,18 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> > if (IS_ERR(base))
> > return PTR_ERR(base);
> >
> > + drvdata->base = base;
> > + dev_set_drvdata(dev, drvdata);
> > +
> > + /*
> > + * pm_runtime_enable needs to be called before clk register.
> > + * That is to make core->rpm_enabled to be true for clock
> > + * usage.
> > + */
> > + pm_runtime_get_noresume(dev);
> > + pm_runtime_set_active(dev);
> > + pm_runtime_enable(dev);
> > +
> > for (i = 0; i < ARRAY_SIZE(sels); i++) {
> > if (sels[i].num_parents == 1) {
> > hw = devm_clk_hw_register_gate_parent_data(dev,
> > @@ -216,8 +289,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> > 0, NULL, NULL);
> > }
> >
> > - if (IS_ERR(hw))
> > - return PTR_ERR(hw);
> > + if (IS_ERR(hw)) {
> > + ret = PTR_ERR(hw);
> > + goto err_clk_register;
> > + }
> >
> > priv->hws[sels[i].clkid] = hw;
> > }
> > @@ -232,8 +307,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> >
> > hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
> > base + 0x400, &imx_1443x_pll);
> > - if (IS_ERR(hw))
> > - return PTR_ERR(hw);
> > + if (IS_ERR(hw)) {
> > + ret = PTR_ERR(hw);
> > + goto err_clk_register;
> > + }
> > priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
> >
> > hw = devm_clk_hw_register_mux_parent_data_table(dev,
> > @@ -241,26 +318,71 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
> > ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
> > CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> > base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
> > - if (IS_ERR(hw))
> > - return PTR_ERR(hw);
> > + if (IS_ERR(hw)) {
> > + ret = PTR_ERR(hw);
> > + goto err_clk_register;
> > + }
> > +
> > priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
> >
> > hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
> > 0, base + SAI_PLL_GNRL_CTL, 13,
> > 0, NULL);
> > - if (IS_ERR(hw))
> > - return PTR_ERR(hw);
> > + if (IS_ERR(hw)) {
> > + ret = PTR_ERR(hw);
> > + goto err_clk_register;
> > + }
> > priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
> >
> > hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
> > "sai_pll_out", 0, 1, 2);
> > - if (IS_ERR(hw))
> > - return PTR_ERR(hw);
> > + if (IS_ERR(hw)) {
> > + ret = PTR_ERR(hw);
> > + goto err_clk_register;
> > + }
> > +
> > + ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> > + priv);
> > + if (ret)
> > + goto err_clk_register;
> > +
> > + pm_runtime_put_sync(dev);
> > + return 0;
> > +
> > +err_clk_register:
> > + pm_runtime_put_sync(dev);
> > + pm_runtime_disable(dev);
> > + return ret;
> > +}
> > +
> > +static int clk_imx8mp_audiomix_remove(struct platform_device *pdev)
> > +{
> > + pm_runtime_disable(&pdev->dev);
> >
> > - return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
> > - priv);
> > + return 0;
> > }
> >
> > +static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev)
> > +{
> > + clk_imx8mp_audiomix_save_restore(dev, true);
> > +
> > + return 0;
> > +}
> > +
> > +static int clk_imx8mp_audiomix_runtime_resume(struct device *dev)
> > +{
> > + clk_imx8mp_audiomix_save_restore(dev, false);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dev_pm_ops clk_imx8mp_audiomix_pm_ops = {
> > + SET_RUNTIME_PM_OPS(clk_imx8mp_audiomix_runtime_suspend,
> > + clk_imx8mp_audiomix_runtime_resume, NULL)
> > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> > + pm_runtime_force_resume)
> > +};
> > +
> > static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
> > { .compatible = "fsl,imx8mp-audio-blk-ctrl" },
> > { /* sentinel */ }
> > @@ -269,9 +391,11 @@ MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
> >
> > static struct platform_driver clk_imx8mp_audiomix_driver = {
> > .probe = clk_imx8mp_audiomix_probe,
> > + .remove = clk_imx8mp_audiomix_remove,
> > .driver = {
> > .name = "imx8mp-audio-blk-ctrl",
> > .of_match_table = clk_imx8mp_audiomix_of_match,
> > + .pm = &clk_imx8mp_audiomix_pm_ops,
> > },
> > };
> >
> > --
> > 2.34.1
> >
> >
> >
>
> regards,
> Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Embedded Linux | https://www.pengutronix.de |
> Vertretung Nürnberg | Phone: +49-5121-206917-129 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v7 16/22] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Initialize bmc gpio state
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 235 ++++++++++++++++++
1 file changed, 235 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 79e3c956bc00..d59542a9ef75 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1271,6 +1271,7 @@ temperature-sensor@1f {
};
};
+
&adc0 {
ref_voltage = <2500>;
status = "okay";
@@ -1298,3 +1299,237 @@ &ehci1 {
&uhci {
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+ bus-frequency = <48000>;
+};
+
+&pinctrl {
+ pinctrl_gpio0_unbiased: gpio0_unbiased {
+ /* GPIOB0, GPIOB1 */
+ pins = "J26", "K23";
+ bias-disable;
+ };
+ pinctrl_gpio2_unbiased: gpio2_unbiased {
+ /* GPIOI5, GPIOI6, GPIOI7,
+ GPIOL6 */
+ pins = "E16", "B16", "A15", "B14";
+ bias-disable;
+ };
+ pinctrl_gpio3_unbiased: gpio3_unbiased {
+ /* GPIOM2, GPIOM3, GPIOM4, GPIOM5,
+ GPION0, GPION1, GPION2, GPION3, GPION5,
+ GPIOO0, GPIOO1, GPIOO2, GPIOO3,
+ GPIOP0, GPIOP1, GPIOP2, GPIOP3, GPIOP4, GPIOP5, GPIOP6 */
+ pins = "A12", "E14", "B12", "C12", "P25", "N23", "N25", "N24", "M23", "AD26", "AD22", "AD23", "AD24", "AB22", "W24", "AA23", "AA24", "W23", "AB23", "AB24";
+ bias-disable;
+ };
+ pinctrl_gpio4_unbiased: gpio4_unbiased {
+ /* GPIOR0, GPIOR1, GPIOR2, GPIOR3, GPIOR4, GPIOR5, GPIOR6, GPIOR7
+ GPIOS0, GPIOS1, GPIOS2, GPIOS3, GPIOS5, GPIOS6, GPIOS7 */
+ pins = "V25", "U24", "V24", "V26", "U25", "T23", "W26", "U26", "R23", "T25", "T26", "R24", "P24", "P23", "T24";
+ bias-disable;
+ };
+ pinctrl_gpio5_unbiased: gpio5_unbiased {
+ /* GPIOV0, GPIOV1, GPIOV2, GPIOV3, GPIOV4, GPIOV5, GPIOV6, GPIOV7
+ GPIOX1, GPIOX2 */
+ pins = "AB15", "AF14", "AD14", "AC15", "AE15", "AE14", "AD15", "AF15", "AA9", "AC9";
+ bias-disable;
+ };
+ pinctrl_gpio6_unbiased: gpio6_unbiased {
+ /* GPIOY2, GPIOY5, GPIOY6
+ GPIOZ0, GPIOZ1, GPIOZ3, GPIOZ4 */
+ pins = "AE11", "AF12", "AC12", "AC10", "AD10", "AB11", "AC11";
+ bias-disable;
+ };
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
+ &pinctrl_gpiu4_default &pinctrl_gpiu6_default
+ &pinctrl_gpio0_unbiased &pinctrl_gpio2_unbiased
+ &pinctrl_gpio3_unbiased &pinctrl_gpio4_unbiased
+ &pinctrl_gpio5_unbiased &pinctrl_gpio6_unbiased>;
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "FLT-HSC-SERVER-SLOT8-N","AC-ON-OFF-BTN-CPLD-SLOT5-N",
+ "PWRGD-SLOT1-STBY","PWRGD-SLOT2-STBY",
+ "PWRGD-SLOT3-STBY","PWRGD-SLOT4-STBY","","",
+ /*C0-C7*/ "","","","","FM-NIC0-WAKE-N",
+ "FM-NIC1-WAKE-N","","RST-PCIE-SLOT2-N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "PRSNT-NIC1-N","PRSNT-NIC2-N","","RST-PCIE-SLOT1-N",
+ "","","","",
+ /*F0-F7*/ "FM-RESBTN-SLOT1-BMC-N","FM-RESBTN-SLOT2-BMC-N",
+ "FM-RESBTN-SLOT3-BMC-N","FM-RESBTN-SLOT4-BMC-N",
+ "PRSNT-SB-SLOT1-N","PRSNT-SB-SLOT2-N",
+ "PRSNT-SB-SLOT3-N","PRSNT-SB-SLOT4-N",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","ALT-MEDUSA-ADC-N",
+ "ALT-SMB-BMC-CPLD2-N",
+ "INT-SPIDER-ADC-R-N",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","ALT-MEDUSA-P12V-EFUSE-N","",
+ /*M0-M7*/ "EN-NIC0-POWER-BMC-R","EN-NIC1-POWER-BMC-R",
+ "INT-MEDUSA-IOEXP-TEMP-N","PRSNT-NIC3-N",
+ "INT-SMB-BMC-SLOT1-4-BMC-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT6-N","","",
+ /*N0-N7*/ "FLT-HSC-SERVER-SLOT1-N","FLT-HSC-SERVER-SLOT2-N",
+ "FLT-HSC-SERVER-SLOT3-N","FLT-HSC-SERVER-SLOT4-N",
+ "FM-BMC-READY-R2","RST-SMB-NIC0-R-N","","",
+ /*O0-O7*/ "AC-ON-OFF-BTN-CPLD-SLOT8-N","RST-SMB-NIC1-R-N",
+ "RST-SMB-NIC2-R-N","RST-SMB-NIC3-R-N",
+ "","","","",
+ /*P0-P7*/ "ALT-SMB-BMC-CPLD1-N","'BTN-BMC-R2-N",
+ "EN-P3V-BAT-SCALED-R","PWRGD-P5V-USB-BMC",
+ "FM-BMC-RTCRST-R","RST-USB-HUB-R-N",
+ "FLAG-P5V-USB-BMC-N","",
+ /*Q0-Q7*/ "AC-ON-OFF-BTN-CPLD-SLOT1-N","AC-ON-OFF-BTN-CPLD-SLOT2-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT3-N","AC-ON-OFF-BTN-CPLD-SLOT4-N",
+ "PRSNT-SB-SLOT5-N","PRSNT-SB-SLOT6-N",
+ "PRSNT-SB-SLOT7-N","PRSNT-SB-SLOT8-N",
+ /*R0-R7*/ "AC-ON-OFF-BTN-CPLD-SLOT7-N","INT-SMB-BMC-SLOT5-8-BMC-N",
+ "FM-PWRBRK-NIC-BMC-R2","RST-PCIE-SLOT4-N",
+ "RST-PCIE-SLOT5-N","RST-PCIE-SLOT6-N",
+ "RST-PCIE-SLOT7-N","RST-PCIE-SLOT8-N",
+ /*S0-S7*/ "FM-NIC2-WAKE-N","FM-NIC3-WAKE-N",
+ "EN-NIC3-POWER-BMC-R","SEL-BMC-JTAG-MUX-R",
+ "","ALT-P12V-AUX-N","FAST-PROCHOT-N",
+ "SPI-WP-DISABLE-STATUS-R-N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","RST-PCIE-SLOT3-N","",
+ "","PRSNT-NIC0-N","","",
+ /*V0-V7*/ "FM-RESBTN-SLOT5-BMC-N","FM-RESBTN-SLOT6-BMC-N",
+ "FM-RESBTN-SLOT7-BMC-N","FM-RESBTN-SLOT8-BMC-N",
+ "","","","",
+ /*W0-W7*/ "PRSNT-TPM-BMC-N","PRSNT-OCP-DEBUG-BMC-N","ALT-TEMP-BMC-N","ALT-RTC-BMC-N",
+ "","","","",
+ /*X0-X7*/ "","LT-HSC-SERVER-SLOT6-N","FLT-HSC-SERVER-SLOT7-N","","","",
+ "PWRGD-SLOT5-STBY","PWRGD-SLOT6-STBY",
+ /*Y0-Y7*/ "","","SPI-LOCK-REQ-BMC-N","PWRGD-SLOT7-STBY",
+ "","","EN-NIC2-POWER-BMC-R","",
+ /*Z0-Z7*/ "EN-P5V-USB-CPLD-R","'FLT-HSC-SERVER-SLOT5-N",
+ "PWRGD-SLOT8-STBY","","","","","";
+
+ pin_gpio_b4 {
+ gpios = <ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_b5 {
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_f0 {
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f1 {
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f2 {
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f3 {
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f4 {
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f5 {
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f6 {
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f7 {
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l6 {
+ gpios = <ASPEED_GPIO(L, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l7 {
+ gpios = <ASPEED_GPIO(L, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s0 {
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s1 {
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v0 {
+ gpios = <ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v1 {
+ gpios = <ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v2 {
+ gpios = <ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v3 {
+ gpios = <ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w0 {
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w1 {
+ gpios = <ASPEED_GPIO(W, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w2 {
+ gpios = <ASPEED_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w3 {
+ gpios = <ASPEED_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w4 {
+ gpios = <ASPEED_GPIO(W, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w5 {
+ gpios = <ASPEED_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w6 {
+ gpios = <ASPEED_GPIO(W, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w7 {
+ gpios = <ASPEED_GPIO(W, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z3 {
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z4 {
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z5 {
+ gpios = <ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
--
2.25.1
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* [PATCH v7 22/22] ARM: dts: aspeed: yosemite4: Revise i2c duty-cycle
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise duty cycle SMB11 and SMB16 to high: 40%, low: 60%,
to meet 400kHz-i2c clock low time spec (> 1.3 us) from EE request
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index c7bba7d68ce1..3a4da189f2c3 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -761,6 +761,7 @@ eeprom@54 {
&i2c10 {
status = "okay";
bus-frequency = <400000>;
+ i2c-clk-high-min-percent = <40>;
i2c-mux@74 {
compatible = "nxp,pca9544";
i2c-mux-idle-disconnect;
@@ -1306,6 +1307,7 @@ &i2c15 {
mctp-controller;
multi-master;
bus-frequency = <400000>;
+ i2c-clk-high-min-percent = <40>;
mctp@10 {
compatible = "mctp-i2c-controller";
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 21/22] ARM: dts: aspeed: yosemite4: support NIC eeprom
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Add NIC eeprom devicetree config
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index d2ad6c8ea165..c7bba7d68ce1 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1330,6 +1330,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux25: i2c@1 {
@@ -1346,6 +1351,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux26: i2c@2 {
@@ -1362,6 +1372,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
imux27: i2c@3 {
@@ -1378,6 +1393,11 @@ temperature-sensor@3c {
compatible = "smsc,emc1403";
reg = <0x3c>;
};
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
};
};
};
--
2.25.1
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* [PATCH v7 20/22] ARM: dts: aspeed: yosemite4: support medusa board adc sensors
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Add ina233/ina28 support for medusa board adc sensors
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 373eacd3186e..d2ad6c8ea165 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -915,6 +915,19 @@ power-sensor@40 {
reg = <0x40>;
};
+ power-sensor@41 {
+ compatible = "ti,ina233";
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
+ reg = <0x41>;
+ };
+
+ power-sensor@44 {
+ compatible = "ti,ina238";
+ shunt-resistor = <1000>;
+ reg = <0x44>;
+ };
+
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
--
2.25.1
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* [PATCH v7 18/22] ARM: dts: aspeed: yosemite4: add mctp config for NIC
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
add mctp config for NIC
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index e0ca0f7b65ea..0d2f0c589944 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1273,40 +1273,64 @@ imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
+ mctp-controller;
temperature-sensor@1f {
compatible = "ti,tmp421";
reg = <0x1f>;
};
+
+ temperature-sensor@3c {
+ compatible = "smsc,emc1403";
+ reg = <0x3c>;
+ };
};
};
};
--
2.25.1
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* [PATCH v7 19/22] ARM: dts: aspeed: yosemite4: support mux to cpld
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Mux pca9544 to cpld was added on EVT HW schematic design,
so add dts setting for devices behind mux pca9544 to cpld
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 64 ++++++++++++++-----
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 0d2f0c589944..373eacd3186e 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -36,6 +36,10 @@ aliases {
i2c31 = &imux31;
i2c32 = &imux32;
i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
};
chosen {
@@ -951,24 +955,54 @@ &i2c12 {
status = "okay";
bus-frequency = <400000>;
- temperature-sensor@48 {
- compatible = "ti,tmp75";
- reg = <0x48>;
- };
+ i2c-mux@70 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x70>;
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
+ imux34: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
- eeprom@54 {
- compatible = "atmel,24c64";
- reg = <0x54>;
- };
+ temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
- rtc@6f {
- compatible = "nuvoton,nct3018y";
- reg = <0x6f>;
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ rtc@6f {
+ compatible = "nuvoton,nct3018y";
+ reg = <0x6f>;
+ };
+ };
+
+ imux35: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux36: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux37: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
};
--
2.25.1
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* [PATCH v7 17/22] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise fan tach config for max31790 driver change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 48 +++++++++++++++++--
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index d59542a9ef75..e0ca0f7b65ea 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1095,8 +1095,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1108,8 +1118,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
@@ -1145,8 +1165,18 @@ adc@1f {
pwm@20{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x20>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
gpio@22{
@@ -1158,8 +1188,18 @@ gpio@22{
pwm@2f{
compatible = "maxim,max31790";
- pwm-as-tach = <4 5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x2f>;
+ channel@4 {
+ reg = <4>;
+ sensor-type = "TACH";
+ };
+
+ channel@5 {
+ reg = <5>;
+ sensor-type = "TACH";
+ };
};
adc@33 {
--
2.25.1
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* [PATCH v7 15/22] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Remove idle state setting for yosemite4 NIC connection
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 011c8d0bba73..79e3c956bc00 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1227,7 +1227,6 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- i2c-mux-idle-disconnect;
reg = <0x72>;
imux24: i2c@0 {
--
2.25.1
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* [PATCH v7 14/22] ARM: dts: aspeed: yosemite4: Revise ina233 config for yosemite4 schematic change
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise ina233 config for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 20 ++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 130283ccefc4..011c8d0bba73 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1026,28 +1026,38 @@ adc@37 {
};
power-sensor@40 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x40>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@41 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x41>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@42 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x42>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@43 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x43>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
power-sensor@44 {
- compatible = "ti,ina230";
+ compatible = "ti,ina233";
reg = <0x44>;
+ resistor-calibration = /bits/ 16 <0x0a00>;
+ current-lsb= /bits/ 16 <0x0001>;
};
temperature-sensor@4e {
--
2.25.1
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* [PATCH v7 12/22] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Remove temperature sensor for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index b52241b0559c..95901f651f7a 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -921,16 +921,6 @@ temperature-sensor@49 {
reg = <0x49>;
};
- temperature-sensor@4a {
- compatible = "ti,tmp75";
- reg = <0x4a>;
- };
-
- temperature-sensor@4b {
- compatible = "ti,tmp75";
- reg = <0x4b>;
- };
-
eeprom@54 {
compatible = "atmel,24c128";
reg = <0x54>;
--
2.25.1
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* [PATCH v7 07/22] ARM: dts: aspeed: yosemite4: Add gpio pca9506
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Add gpio pca9506 I/O expander for yv4 use
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 251 ++++++++++++++++++
1 file changed, 251 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index af9f7067c57c..ed8f529a381e 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -175,6 +175,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -193,6 +221,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -211,6 +267,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -229,6 +313,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -247,6 +359,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -265,6 +405,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -283,6 +451,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -301,6 +497,34 @@ mctp@10 {
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
};
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
power-sensor@40 {
compatible = "adi,adm1281";
reg = <0x40>;
@@ -683,6 +907,33 @@ rtc@6f {
&i2c13 {
status = "okay";
bus-frequency = <400000>;
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
&i2c14 {
--
2.25.1
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* [PATCH v7 13/22] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode for yosemite4 schematic change
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise adc128d818 adc mode for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 95901f651f7a..130283ccefc4 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1010,19 +1010,19 @@ &i2c14 {
adc@1d {
compatible = "ti,adc128d818";
reg = <0x1d>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
- adc@35 {
+ adc@36 {
compatible = "ti,adc128d818";
- reg = <0x35>;
- ti,mode = /bits/ 8 <2>;
+ reg = <0x36>;
+ ti,mode = /bits/ 8 <1>;
};
adc@37 {
compatible = "ti,adc128d818";
reg = <0x37>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
power-sensor@40 {
--
2.25.1
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* [PATCH v7 09/22] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Enable interrupt setting for pca9555
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 56 +++++++++++++++++--
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index f6527f0dbeb4..d1ee5a6bd7d3 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -832,30 +832,78 @@ power-sensor@12 {
gpio@20 {
compatible = "nxp,pca9555";
- reg = <0x20>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "P48V-OCP-GPIO1","P48V-OCP-GPIO2",
+ "P48V-OCP-GPIO3","FAN-BOARD-0-REVISION-0-R",
+ "FAN-BOARD-0-REVISION-1-R","FAN-BOARD-1-REVISION-0-R",
+ "FAN-BOARD-1-REVISION-1-R","RST-MUX-R-N",
+ "RST-LED-CONTROL-FAN-BOARD-0-N","RST-LED-CONTROL-FAN-BOARD-1-N",
+ "RST-IOEXP-FAN-BOARD-0-N","RST-IOEXP-FAN-BOARD-1-N",
+ "PWRGD-LOAD-SWITCH-FAN-BOARD-0-R","PWRGD-LOAD-SWITCH-FAN-BOARD-1-R",
+ "","";
};
gpio@21 {
compatible = "nxp,pca9555";
- reg = <0x21>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x21>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "HSC-OCP-SLOT-ODD-GPIO1","HSC-OCP-SLOT-ODD-GPIO2",
+ "HSC-OCP-SLOT-ODD-GPIO3","HSC-OCP-SLOT-EVEN-GPIO1",
+ "HSC-OCP-SLOT-EVEN-GPIO2","HSC-OCP-SLOT-EVEN-GPIO3",
+ "ADC-TYPE-0-R","ADC-TYPE-1-R",
+ "MEDUSA-BOARD-REV-0","MEDUSA-BOARD-REV-1",
+ "MEDUSA-BOARD-REV-2","MEDUSA-BOARD-TYPE",
+ "DELTA-MODULE-TYPE","P12V-HSC-TYPE",
+ "","";
};
gpio@22 {
compatible = "nxp,pca9555";
- reg = <0x22>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "CARD-TYPE-SLOT1","CARD-TYPE-SLOT2",
+ "CARD-TYPE-SLOT3","CARD-TYPE-SLOT4",
+ "CARD-TYPE-SLOT5","CARD-TYPE-SLOT6",
+ "CARD-TYPE-SLOT7","CARD-TYPE-SLOT8",
+ "OC-P48V-HSC-0-N","FLT-P48V-HSC-0-N",
+ "OC-P48V-HSC-1-N","FLT-P48V-HSC-1-N",
+ "EN-P48V-AUX-0","EN-P48V-AUX-1",
+ "PWRGD-P12V-AUX-0","PWRGD-P12V-AUX-1";
};
gpio@23 {
compatible = "nxp,pca9555";
- reg = <0x23>;
+ pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
+ reg = <0x23>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+ gpio-line-names =
+ "HSC1-ALERT1-R-N","HSC2-ALERT1-R-N",
+ "HSC3-ALERT1-R-N","HSC4-ALERT1-R-N",
+ "HSC5-ALERT1-R-N","HSC6-ALERT1-R-N",
+ "HSC7-ALERT1-R-N","HSC8-ALERT1-R-N",
+ "HSC1-ALERT2-R-N","HSC2-ALERT2-R-N",
+ "HSC3-ALERT2-R-N","HSC4-ALERT2-R-N",
+ "HSC5-ALERT2-R-N","HSC6-ALERT2-R-N",
+ "HSC7-ALERT2-R-N","HSC8-ALERT2-R-N";
};
temperature-sensor@48 {
--
2.25.1
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* [PATCH v7 08/22] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Remove space for adm1272 compatible
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ed8f529a381e..f6527f0dbeb4 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -821,12 +821,12 @@ imux29: i2c@1 {
&i2c11 {
status = "okay";
power-sensor@10 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x10>;
};
power-sensor@12 {
- compatible = "adi, adm1272";
+ compatible = "adi,adm1272";
reg = <0x12>;
};
--
2.25.1
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* [PATCH v7 11/22] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Add eeprom for yosemite4 use
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 175bb5849e1a..b52241b0559c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -932,7 +932,7 @@ temperature-sensor@4b {
};
eeprom@54 {
- compatible = "atmel,24c256";
+ compatible = "atmel,24c128";
reg = <0x54>;
};
@@ -971,6 +971,11 @@ eeprom@50 {
reg = <0x50>;
};
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
rtc@6f {
compatible = "nuvoton,nct3018y";
reg = <0x6f>;
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 10/22] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Add power sensor for power module reading
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index d1ee5a6bd7d3..175bb5849e1a 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -906,6 +906,11 @@ gpio@23 {
"HSC7-ALERT2-R-N","HSC8-ALERT2-R-N";
};
+ power-sensor@40 {
+ compatible = "mps,mp5023";
+ reg = <0x40>;
+ };
+
temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
@@ -930,6 +935,26 @@ eeprom@54 {
compatible = "atmel,24c256";
reg = <0x54>;
};
+
+ power-sensor@62 {
+ compatible = "pmbus";
+ reg = <0x62>;
+ };
+
+ power-sensor@64 {
+ compatible = "pmbus";
+ reg = <0x64>;
+ };
+
+ power-sensor@65 {
+ compatible = "pmbus";
+ reg = <0x65>;
+ };
+
+ power-sensor@68 {
+ compatible = "pmbus";
+ reg = <0x68>;
+ };
};
&i2c12 {
--
2.25.1
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* [PATCH v7 06/22] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise power sensor adm1281 for yosemite4 schematic change
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 24 ++++++++++++-------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 23006dca5f26..af9f7067c57c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -176,8 +176,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -193,8 +194,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -210,8 +212,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -227,8 +230,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -244,8 +248,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -261,8 +266,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -278,8 +284,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
@@ -295,8 +302,9 @@ mctp@10 {
};
power-sensor@40 {
- compatible = "adi,adm1278";
+ compatible = "adi,adm1281";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <500>;
};
};
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 04/22] ARM: dts: aspeed: yosemite4: Enable watchdog2
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
enable watchdog2 setting
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index ea8fd3ec0982..f8bfdefbefc6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -120,6 +120,13 @@ &wdt1 {
aspeed,ext-pulse-duration = <256>;
};
+&wdt2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst2_default>;
+ aspeed,reset-type = "system";
+};
+
&mac2 {
status = "okay";
pinctrl-names = "default";
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 00/22] Add i2c-mux and eeprom devices for Meta Yosemite 4
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick
Cc: Delphine CC Chiu, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel
Changelog:
- v7
- Revise pca9506 i2c address
- v6
- Revise i2c duty-cycle for meeting 400khz spec
- v5
- Support medusa board adc sensors
- support NIC eeprom
- v4
- Re-format gpio linename
- Revise i2c device node names
- Split patches by logic changes
- v3
- Correct patch for revising gpio name
- v2
- Revise mx31790 fan tach config
- Add mctp config for NIC
- Support mux to cpld
- Revise gpio name
- v1
- Add gpio and eeprom behind i2c-mux
- Remove redundant idle-state setting for i2c-mux
- Enable adc 15, wdt2,spi gpio for yosemite4 use
- Revise quad mode to dual mode to avoid WP pin influnece the SPI
- Revise power sensor adm1281 for yosemite4 schematic change
- Add gpio pca9506 I/O expander for yosemite4 use
- remove space for adm1272 compatible
- enable interrupt setting for pca9555
- add eeprom for yosemite4 medusa board/BSM use
- remove temperature sensor for yosemite4 schematic change
- add power sensor for power module reading
- Revise adc128d818 adc mode for yosemite4 schematic change
- Revise ina233 for yosemite4 schematic change
- Remove idle state setting for yosemite4 NIC connection
- Initialize bmc gpio state
- Revise mx31790 fan tach config
- Add mctp config for NIC
- Support mux to cpld
- Revise gpio name
Delphine CC Chiu (22):
ARM: dts: aspeed: yosemite4: Revise i2c-mux devices
ARM: dts: aspeed: yosemite4: Enable adc15
ARM: dts: aspeed: yosemite4: Enable spi-gpio setting
ARM: dts: aspeed: yosemite4: Enable watchdog2
ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic
change
ARM: dts: aspeed: yosemite4: Add gpio pca9506
ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible
ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555
ARM: dts: aspeed: yosemite4: Add power sensor for power module reading
ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use
ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4
schematic change
ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode for yosemite4
schematic change
ARM: dts: aspeed: yosemite4: Revise ina233 config for yosemite4
schematic change
ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4
NIC connection
ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config
ARM: dts: aspeed: yosemite4: add mctp config for NIC
ARM: dts: aspeed: yosemite4: support mux to cpld
ARM: dts: aspeed: yosemite4: support medusa board adc sensors
ARM: dts: aspeed: yosemite4: support NIC eeprom
ARM: dts: aspeed: yosemite4: Revise i2c duty-cycle
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 1258 +++++++++++++++--
1 file changed, 1151 insertions(+), 107 deletions(-)
--
2.25.1
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^ permalink raw reply
* [PATCH v7 05/22] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise quad mode to dual mode to avoid WP pin influnece the SPI
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index f8bfdefbefc6..23006dca5f26 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -149,15 +149,17 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
- spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
spi-max-frequency = <50000000>;
};
};
--
2.25.1
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^ permalink raw reply related
* [PATCH v7 01/22] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices
From: Delphine CC Chiu @ 2024-03-21 2:12 UTC (permalink / raw)
To: patrick, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery
Cc: Delphine CC Chiu, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240321021236.1823693-1-Delphine_CC_Chiu@wiwynn.com>
Revise Yosemite 4 devicetree for devices behind i2c-mux
- Add gpio and eeprom behind i2c-mux
- Remove redundant idle-state setting for i2c-mux
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 381 ++++++++++++++++--
1 file changed, 347 insertions(+), 34 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 64075cc41d92..dac58d3ea63c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -17,6 +17,25 @@ aliases {
serial6 = &uart7;
serial7 = &uart8;
serial8 = &uart9;
+
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
};
chosen {
@@ -259,9 +278,109 @@ &i2c8 {
bus-frequency = <400000>;
i2c-mux@70 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x70>;
+
+ imux16: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux17: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux18: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux19: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
@@ -270,15 +389,174 @@ &i2c9 {
bus-frequency = <400000>;
i2c-mux@71 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x71>;
+
+ imux20: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux21: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux22: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
+
+ imux23: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ gpio@49 {
+ compatible = "nxp,pca9537";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+ };
};
};
&i2c10 {
status = "okay";
bus-frequency = <400000>;
+ i2c-mux@74 {
+ compatible = "nxp,pca9544";
+ i2c-mux-idle-disconnect;
+ reg = <0x74>;
+
+ imux28: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9506";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@21 {
+ compatible = "nxp,pca9506";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9506";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@23 {
+ compatible = "nxp,pca9506";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9506";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "","","","",
+ "NIC0-MAIN-PWR-EN","NIC1-MAIN-PWR-EN",
+ "NIC2-MAIN-PWR-EN","NIC3-MAIN-PWR-EN",
+ "","","","","","","","",
+ "","","","","","","","",
+ "","","","","","","","";
+ };
+ };
+
+ imux29: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
};
&i2c11 {
@@ -433,16 +711,14 @@ eeprom@51 {
reg = <0x51>;
};
- i2c-mux@71 {
- compatible = "nxp,pca9846";
+ i2c-mux@74 {
+ compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
- reg = <0x71>;
+ reg = <0x74>;
- i2c@0 {
+ imux30: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -450,26 +726,26 @@ i2c@0 {
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -492,34 +768,34 @@ gpio@61 {
};
};
- i2c@1 {
+ imux31: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@1f {
compatible = "ti,adc128d818";
reg = <0x1f>;
- ti,mode = /bits/ 8 <2>;
+ ti,mode = /bits/ 8 <1>;
};
pwm@20{
- compatible = "max31790";
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
- pwm@23{
- compatible = "max31790";
- reg = <0x23>;
- #address-cells = <1>;
- #size-cells = <0>;
+ pwm@2f{
+ compatible = "maxim,max31790";
+ pwm-as-tach = <4 5>;
+ reg = <0x2f>;
};
adc@33 {
@@ -547,12 +823,10 @@ i2c-mux@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
-
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x73>;
- i2c@0 {
+ imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -563,10 +837,10 @@ adc@35 {
};
};
- i2c@1 {
+ imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
+ reg = <1>;
adc@35 {
compatible = "maxim,max11617";
@@ -589,9 +863,48 @@ mctp@10 {
i2c-mux@72 {
compatible = "nxp,pca9544";
- idle-state = <0>;
i2c-mux-idle-disconnect;
reg = <0x72>;
+
+ imux24: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux25: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux26: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
+
+ imux27: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ temperature-sensor@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+ };
};
};
--
2.25.1
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